11.

A 380-MHz CMOS Linear-in-dB Signal-summing Variable Gain

Amplifier with Gain Compensation Techniques for CDMA Systems
Osamii Watanabe, Slioji Otaka, Mitsuyuki Ashida and Tetsuro Itakura
Corporate R&D Center, Toshiba Corporation, Kawasaki, .Japan

Abstract
CSCl Signal-summing VGA
A linear-in-dB signal-summing VGA is fabricated in 0.25
pm CMOS technology. Two gain compensation techniques are
proposed in order to compensate the gain deviations due to a
MOSFET characteristic which has a square-law characteristic
or an exponential-law characteristic determined by its current
density. Temperature conipensation techniques are also pro-
posed. A gain range of 80 dB, a gain error of within i 3 dB,
an NF of 11 dB are obtained a t 380 MHz by measurement.
Introduction
CDMA systems require variable gain amplifiers (VGAs)
with wide dynamic range in both transmitter(TX) and re-
ceiver(RX). Especially for a wide-band CDMA (W-CDMA)
system, not only the wide dynamic ranae but also a hiah ~

frequency operation should be simultaneously satisfied in the

Figure CMOS signal-summing V~~ with CsC
VGA. Although CMOS linear-in-dB VGAs have been reported
11, 21, a linear-in-dB VGA with signal-summing technique suit-
able for wide dynamic range and high frequency operation has
not been realized with CMOS technology, because gain com-
pensation seems complicated for ohtaining a linear-in-dB char-
acteristic as described in the next section. This paper mainly
discusses gain compensation techniques suitable for a CMOS
linear-in-dB VGA with signal-summing technique. T h e mea-
sured results indicate that the VGAs with the proposed gain
compensation techniques are applicable for W-CDMA system.
Gain deviation in signal-summing VGA
I
A signal-summing VGA with control signal converter(CSC1)
using bipolar transistors has been proposed for ohtaining a
4 -
square-law region exponential-law region
linear-in-dB characteristic. where CSCl comeensat,rs a gain
~~
I ~~~~~

characteristic of the signai-summing VGA[3]. Fig. 1 shows a

CMOS version of the signal-summing VGA with CsC1. Cur- Figure 2: G a i n deviation from linear-in-dB characteristic
rent densities of MlO-M11 and M1-M4 are set to the same
value so as to have differential pairs of M1-M2, M3-M4 op-
where g m M l o , gmM1l are transconductances of M10 and
erate as a current mirror of a differential pair of MlO-M11 in
M11, respectively, I D I , I D ~are drain currents of M10
order to determine a current gain GI,(=AIaut/AItn)by CSCl.
and M11. Equation (2) indicates that the gain-slope is
I D I ( = I o e x p { - R I x / ( a V ~ ) } ) is generated at M21 by a cun-
exp{-RIx/(SnVT)} and the gain decreases 3 dB a t I D I =
trol signal current I x , a resistor R, and M20, M21 operated
I m ( V v = 0) from a linear-in-dB gain line(line A).
in exponential-law region such as bipolar transistors, where
In the case that M1, M3, M10 operate in exponential-law
ID,, lo are drain currents of M21 and MZO, respectively. How- region; that is lower gain region, the current gain G I is ap-
ever, a crucial deviation from linear-in-dB characteristic occurs
proximately cxpressed by
as shown in Fig. 2, because an operating region of M1, M3, M10
is changed from square-law region to exponential-law region as
the current gain is decreased as described below.
In the case that M1, M3, M10 operate in square-law re-
gion; that is, in higher gain region, the current gain of GI is
expressed by
where p = ( l / Z ) p C o x ( W / L ) ,p is a mobility, C o x is gate
oxide capacitance per unit area, n is a constant related on
process parameters, and VT is the thermal voltage. Equation
(3) indicates that the gain-slope is twice of that in square-law
region.

136 02002 IEEE

0-7803-7310-3/02/$17.00 2002 Symposium On VLSl Circuits Digest of Technical Papers

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 Gain compensation techniques
Fig. 3 sliowis a block diagram for aht,ainirig linear-in-dB char-
acterist,ics for a CMOS ~:irrrcnt-surrirriilIgVGA with CSCI,
where CSC:< a n d VGAR with CSCZ compensate t h c gain devia-
tions caused by two st.agcs VGA I , VGA2 of t h e VGA. Proposcrl
gain compensa1,ion strategies arc ns follows: ( A ) A control sig-
nal convcrter(CSC3), which mnverts ext,ernal control signal
VCNT t o Ix and has a gain change(g;tin ratio = 211) at a baund-
ary voltage V c , is applied for making t.he gain-slopes of the
square-law region(eq. ( 2 ) ) and exponential-law region(eq. (3))
equal. (B) Add anothcr signal-surnrning VGA(VGA3) with
a control signal converter(CSC2) for compensating a gain de-
crease of V G A l and VGA2 at around I D , = r~~ simultane-
ously, where a maximum of the gain decrease due to V G A l
a n d VGA2 is 6 dR in this case.
. .
F i g u r e 3: Block d i a g r a m for g a i n c o m p e n s a t i o n and g a i n
characteristics
A. Gain-slope Compensation in Lower Gain Region
......................................................................
--Bm
I.
. .-
.........................................................................
F i g u r e 4: CSC3 for gain-slope compensation
CSCY compensates the gain-slope change due to a tran-
sition of MOSFET's operation region from square-law re-
gion to exponential-law region. For achieving this compensa-
tion, CSC3 comprises two-parallel connected differential am-
plifiers(AMP1, AMPZ) of the same gain as shown in Fig.4,
where Rlo = R41 = Ra2 = R13 = R s . AMP2 saturates output
current over the boundary voltagec'l of R s l o l l . An input
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range ol A M P l can bc about twice that of .4MP2 by applying
an appropriate offset vokage V s B ( - RsIo/2) to gates of M41
and R.143. T h e boundary Vc is determined by circuit simula-
t.ion to obtain an accurate linear-in-dB characteristic.
T h e CMOS VGAs arc rlesigiied t,o have the maxirnum gain
at IX=O mA. 'rhereforc; diflerential pairs of M40-M41 and
M46-M47 are added to canccl DC currents from A M P l and
AMP2 at, the cont.rol voltage V C N T =V.~
B. Gain Compensation in Higher Gain Rrgion
T h e gain of VG1\3 should be set t o (1 + Z m l I o ) in
order t o compensate the gain error due t,o V G A l and VGAZ as
indicated from the cquation ( 2 ) . To realizc this, CSCZ which
comprises CSCI with input current generated by a square
circuit[4] is proposed as shown in Fig. 5. T h e reasons for adopt-
ing the square circuit used in CSCZ are as follows: (i) it has
a n even function of VY, (ii) it senses VY = 0 as the condi-
tion of ID,= I D 2 or the condition of a product IDLIDS being
maximum, where a gain-increase of 6 dB is required t o obtain
linear-in-dB characteristic.
..........CSCI
........................................... c5c2
,
, I. ......................
F i g u r e 5 : G a i n compensation i n higher g a i n region
A VGA3's gain(GjVGA3)) in CSC2 is expressed by
&/(& + 6) as shown in equation ( I ) , where ISZ =
l o - I s ] , Is, a n d Isz are drain currents of M34 and M35, re-
spectively. T h e gain compensation within 6 dB gain range
is achieved by changing Is, from 0.2510 t o 0.9Io, namely
GjVGA3)is 0.75, 0.37 at I s , = 0.9Io,0.25Io, respectively, and
0.75/0.37-6 dB. VGA3 are placed in back of VGAI-VGAZ t o
avoid noise degradation, because VGA3 does not have maxi-
mum current gain a t maximum gain of the VGA.
I s , are a sum current of I B ( = 0.2510) and a n output current
of the square circuit(1spn). A maximum current 0.6510 of
I S Q R at VY = 0 can be designed by setting a n appropriate
W/L of MOSFET described below. In a n input voltage IVY[5
d m , I S Q R of the square circuit is expressed by
where Pu is 0 of M31, M33, K is W/L ratio of M30, M32 and
M31, M33[4]. I s ~ approaches
n 0 when IVY~becomes
T h e equation (4) indicates t h a t I S Q R is approximately 0.6510
m.
a t VY = 0 by setting the W/L ratio K to 2. Io and Bu,
which determine the voltage range IVY 1 5 of VGA3
for compensating the gain error, are set from simulated results.
2002 Symposium On VLSl Circuits Digest of Technical Papers 137
 Temperature c o m p e n s a t i o n t e c h n i q u e s
Temperature compensation for both a transconductance
(9,) of the differential pair M5-M6 shown in Fig. 1 and a ther-
mal voltage VT in equations (2), (3) is required for the pro-
posed VGA. Fig. 6 shows a block diagram of the proposed V G A
including the two temperature compensation blocks.
,.~~...~~~~.,
Y i
Figure 6: Block diagram of t h e CMOS VGA
The temperature dependence of transconductance g,
m)
of a differential pair M5-M6 is caused by that of mo-
bility p in MOSFET, where p = (1/2)pCox(W/L), and Io is
a drain current of M 5 or M6. A temperature-independent gm
can b e obtained by changing I o , i.e., tail current 210 so as to
cancel the temperature dependence of the mobility p. In this
case, however, drain currents of M20, M21 in CSCl need to
have the same temperature dependency as the differential pair
in order to obtain the linear-in-dB characteristic. 5 3 d B gain
deviation is approximately estimated at only the lower gain
region in a temperature range of 4 0 ° C to 80°C, because the
equation (3) indicates that GI depends on a bias current(Io) of
M20. In the above discussion, V T is supposed ~ t o be approx-
imately independent of temperature, because p is expressed by
po (T/To)-' and fiis inversely proportional t o temperature,
where To is a nominal temperature, po is a mobility at To,
and k is about 2. I t seems difficult to compensate this gain
deviation in only the lower gain region. Therefore, a gm com-
pensation circuit (TCVGA) regardless of the operating region
of MOSFETs is introduced, while a tail current 2Io of the dif-
ferential pair M5-M6 and drain currents lo of M20, M21 in
C S C l are kept independent of temperature.
TCVGA composed of the signal-summing VGA and C S C l
blocks with temperature-independent bias current I o are pro-
posed for compensating the temperature-dependent g, as
shown in Fig. 6 . The temperature-independent Io is applied for
VGAl-VGA3, TCVGA, B U F F and CSCI-CSC3, where B U F F
is an output buffer for driving external 50 R load. T h e VG.4
has temperature dependency of the gain inversely proportional
to temperature in this case, because the differential ampli-
fier used in VGAl only has no source degeneration resistor
whereas that used in VGA2 and VGA3 has source degenera-
tion resistor and the temperature dependency of V G A l ' s g...
(Efi OL ( T / T o ) - ' )is dominant for the VGA. TCVGA and
CSCl are almost the same as that shown in Fig. 1, except that
temperature compensation c u r r e n t ( I r c ) of Io(m - AT/To) is
applied in place of I x , where AT = T To, and m is a con-
~
stant. I T c is generated by subtracting temperature-dependent
138
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+
current of Io(1 AT/To) from temperature-independent CUI-
+
rent of lo(1 m). Thus, TCVGA's gain increases as tem-
perature increases and TCVGA cancels the temperature de-
pendency of the V G A l ' s gXn. m is set at about 0.3 to avoid
a useless gain-decrease, considering that a maximum value of
AT/T is 0.2 in the temperature range. Our estimation of g,
deviation of differential amplifiers used i n VGAl-VGA3 is ap-
proximately f 3 d B i n the temperature range. Therefore, the
gain range of about 6 d B around the maximum gain in square-
law region(Fig. 2 ) is assigned for TCVGA. TCVCA is placed
between VGAI-VGA2 and VGA3 far consideration on low-
noise performance.
A Widlar current source(V~ref in Fig.6) is used for the
implementation of the temperature-dependent current source
as shown in Fig. 7. A ratioed MOSFET-pair, M60-M61 o p
erates in exponential-law region for generating PTAT char-
acteristic. Temperature-independent current Io is generated
by summing output currents from a VT-reference bias circuit
and output current from a Vm-reference bias circuit[5], where
VTH is threshold voltage. Then, the temperature dependence
of Io is canceled because the temperature coefficient of the
VT-reference bias circuit has a polarity opposite to that of
Vm-reference bias circuit.
(=
'.................................... ......................................... .
Figure 7: Block diagram for t e m p e r a t u r e compensation
The other temperature Compensation block is TC1, which
reduces the gain deviation due t o thermal voltage VT as ex-
pressed in equations (Z), ( 3 ) . This temperature compensation
is achieved by multiplying the control signal current Ix from
CSCJ and a temperature-dependent current Io(1 AT/To) +
as shown in Fig. 7131. A linear multiplier is realized using a
current divider consisting of two differential amplifiers, M i 0 -
M71 and M72-M73. This multiplier operates so as t o obtain
I x / l o = Ix('l')/{Io(l +
AT/To)}. For achieving an accu-
rate multiplication, four MOSFETs M70-M73 are operated in
exponential-law region in the same manner as bipolar transis-
tors.
Measured results
A micrograph of the CMOS VGA is shown in Fig. 8. The
die size is 1.42 mm x 1.42 m m The CMOS VGA is fabricated
in 0.25-pm CMOS process. The performance of the IC was
measured using a glass-epoxy circuit board.
The VGA attained cut-off frequency(3-dB frequency) of
280 MHz. The cut-off frequency is higher than that of the pre-
vious reports[l, 21. The VGA can be applied to W-CDMA sys-
2002 Symposium On VLSl Circuits Digest of Technical Papers

Figure 8: Micrograph of the CMOS VGA
tem because a gain deviation in 4 MHz bandwidth a t 380 MHz
is less than 0.2 dB. Fig. 9 shows a linear-in-dB characteristic
of the proposed VGA a t 25.5 "C, when the signal frequency is
380 MHz. The gain range of80 d B and the gain error of within
+ 3 d B were achieved. Fig. 9 also shows gain characteristics of
VGA without compensation, in which AMP2 in CSC3 and the
square circuit in CSCZ were inacbive. A narrower gain range of
the VGA without compensation compared t o the compensated
VGA is caused by inactive AMP2. Comparison shows that t h e
proposed compensation scheme works well within 3-dB gain
error.
p'..
Withod cbm~nsationi ! e'.o
Fig. 10 shows linear-in-dB gain and noise characteristics for
the proposed VGA at 25.5 "C, 85 "C, and -32 "C, when the
signal frequency is 380 MHe. The gain deviation within 3 dB
are achieved over a gain range of 80 d B throughout the tem-
perature range. This figure indicates that the proposed VGA
is successfully compensated for temperature variations of the
gain. An NF of less than 11 dB was obtained a t the maximum
gain of 11 dB. The measured results are summarized in Table
1.
Conclusions
Two gain compensation techniques are applied t o a signal-
summing VGA, which is suitable for a wide dynamic range and
high frequency response. One is to conipensate a gain-slope
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75
6
50 P
Y
z
25
Figure 10: T e m p e r a t u r e dependency of CMOS VGA
Table 1: Measured results
Gain deviationQ4 MHz
Gain range -
5 0.2 dB0380 MHz signal
-70 dB 11 d B
5 3 dB
Gain error
NF 5 11 dBQGain=ll d B
Adj. channel leakage 5 -40 dBc@-19 dBm output
Supply voltage/current 2.5 V125.3 mA
change due t o a transition of MOSFET's operation region from
square-law region t o exponential-law region by a control signal
converter with two-parallel connected differential amplifiers.
The other is a gain increase in higher gain region by using a
control signal converter with a square circuit.
A temperature-dependent transconductance(g,) is compen-
sated by adding additional VGA with a control signal con-
verter having temperature-dependent signal input. Moreover,
temperature-dependent linear-in-dB characteristics are com-
pensated by revising the conventional temperature compensa-
tion techniques for a CMOS version of the VGA.
The measured results indicate that these gain compensation
techniques and temperature compensation techniques work
well and the VGA is applicable for a transmitter of W-CDMA.
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