Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering

(RACE-2014), 28-29 March 2014

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Combinational Circuit Design using
Advanced Quantum Dot Cellular Automata
Aditi Dhingra, Aprana Goel, Gourav Verma, Rashmi Chawla

Department of Electronics and Communication Engineering
YMCAUST, Faridabad (www.ymcaust.ac.in)
aditidhingra639@gmail.com, aprana02.goel@gmail.com, gouravneeb059@gmail.com

Abstract - This paper describes the design of different type of combinational such as adder , subtractor preceding NAND,
NOR, XOR, XNOR based on QCA design, with comparatively less number of cells and area. It is efficient for its faster
speed ,smaller size and low power consumption than transistor technology.QCA provides for nano-level computations
using molecular component .QCA Designer gives the designer the ability to quickly layout a QCA design by providing an
extensive set of CAD tools.By taking full advantage of the unique features of this technology, we are able to create
complete circuits on a single layer of QCA.

Keywords-component, QCA, combinational circuits, majority gates, QCA designer.

I.INTRODUCTION

The size of CMOS transistors are decreasing day by day and it will eventually hits its limitations hence it become
necessary to develop an alternate to continually improve the development of electronics devices .Devices based on
quantum-mechanical principles hold the promise of faster speeds and greatly reduced sizes. Most quantum device
designs examined have been similar to classical device implementations in that they use currents and voltages to
encode information.QCA is a potential device
That can be used to implement the sequential and the combinational circuits. It is a different type of technology that
will replace MOSFET in future. QCAs were introduced in 1993 by lent et al, and experimentally verified in 1997. It
is expected to achieve high device density, extremely low power consumption and very high switching speed .The
QCA offers a new transistorless computing paradigm in nanotechnology. QCA can be used to create s smaller
electronics device with high computation switching speed and low power consumption. this make research on QCA
popular and important to replace CMOS transistors in Nano-scale technology fabrication.

II.QCA BASICS

A QCA consists of an array of quantum-dot cells connected locally by the interactions of the electrons contained in
each cell. The scheme is non-conventional in that the quantum state of each cell is used to encode binary
information. The Coulombic interaction connects the state of one cell to the state of its neighbors. Thus the
problems associated with small output currents and parasitic capacitances of connecting wires do not occur. Binary
wires composed of linear arrays of cells are effective in transmitting information, coded in the cell states, from one
place to another. By applying these layouts, the hardware requirements for a QCA design can be reduced.
QCA is based on electrons confining in dots and each cell has four quantum Dots . The four dots are located in
the corners of squares structure as shown in fig 1.The cell contains two extra mobile electrons, which are allowed to
tunnel between neighboring sites of the cell. Coulombic repulsion causes the electrons to occupy antipodal sites
within the cell. These two bistable states result in cell polarizations of P = +1(binary 1) and P = -1(binary 0) and one
Null state , P=0 as shown below in Fig.1.
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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QCA cells transfer information by the propagation of polarized charge instead of flow of current thus, QCA circuits
have lower energy and higher processing speed. The power needed to perform the polarization changes in cells (that
support logic operations) is supplied by the clock signal.
A.QCA WIRE
In a QCA wire, the binary signal propagates from input to output because of the electrostatic interactions between
cells. Since the polarization of each cell tends to align with that of its neighbors, a linear arrangement of standard
cells can be used to transmit binary information from one point to another.
A QCA wire is needed to transmit signals. The wire consists of chain of cells where the cells are coupled to each
other. Logic values are passed from cell to cell due to the coloumbic interactions. The polarization of input cell is
propagated down the wire .Any cell along the wire that are anti polarized to the input would be at a higher energy
level and would soon settle to the correct ground state. The propagation in a 90 QCA wire is shown in Fig. 2.
Another is 45 QCA wire, in Fig.3. In this case, the propagation of the binary signal alternates between the two
polarizations.

B.QCA INVERTER

Two standard cells in a diagonal orientation are geometrically similar to two rotated cells in a horizontal orientation.
For this reason, standard cells in a diagonal orientation tend to align in opposite polarization directions as in the
inverter chain. This anti aligning behavior can be used in designing a QCA inverter. The electrostatic interaction is
inverted, as the quantum dots corresponding to different polarizations are misaligned between the cells as in Fig.
4(a). There are several inverter types. Inverter of two cells is shown in Fig. 4(b).

Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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The signal comes in from the left on a binary and splits into two parallel wires which are offset from the original.
Because the incoming wire extends one cell beyond the beginning of the offset wires, aligning effects dominate at
the branch point. Since the horizontal and vertical interactions are dominant, the signal in the two offset wires
always matches that of the incoming wire. At the right end of the inverter, the offset wires rejoin into one. However,
there are no horizontal or vertical interactions at this end, so the diagonal interactions cause the signal to be inverted.

C.PROGRAMMABLE LOGIC GATE
The fundamental QCA logical device is a 3 input majority gate, shown in Fig.5. from which more complex circuits
can be built. The central cell, labeled the device cell, has three fixed inputs, labeled A, B, and C. The device cell has
its lowest energy state if it assumes the polarization of the majority of the three input cells. The inputs to a particular
device can come from previous calculations or be directly fed in from array edges.
Figure 5(a) shows an arrangement of five standard cells. The states of the cells on the top, left, and bottom are fixed,
while the center and right cells are free to react to the fixed charge. In an actual implementation, the three neighbors
would not be fixed; they would be driven by results of previous calculations or by inputs at the edge of the QCA. In
the particular case shown, two of the inputs are in the one state, and the other is in the zero state. When we solve
for the ground state of the free cells, we find that they both match the state of the majority of the fixed neighbors.
We refer to this result, which is true for all combinations of the three inputs, as majority voting logic. To represent
this new logical function, we will use the symbol shown in Fig. 5(b). As this symbol demonstrates, there are three
inputs and one output for such a logic gate. Figure 5(c) shows the truth table for a majority voting logic gate. This is
a summary of our simulation of all eight combinations of the three inputs. The majority voting logic function can be
expressed in terms of fundamental Boolean operators as
M(A,B,C) =AB+ BC+AC.

Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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Figure 5 Qca Majority Gate

III.QCA DEFECTS

The types of defect that are likely to occur in the manufacturing of QCA devices are illustrated in Fig. 6.They can be
categorized as follows:
i). In a cell displacement defect, the defective cell is displaced from its original position. For example, in Fig.
6(b),the cell with input B is displaced to the north by nm from its original position.
ii). In a cell misalignment defect, the direction of the defective cell is not properly aligned. For example, in Fig.6(c),
the cell with input B is misaligned to the east by nm from its original position.
iii). In a cell omission defect, the defective cell is missing as compared to the defect-free case. For example, in Fig.
6(d), the cell with input B is not present.

Figure 6 QCA Defects
IV.CLOCKING
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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The QCA circuits require a clock, not only to synchronize and control information flow but also to provide the
power to run the circuit since there is no external source for powering cells (serial add, shifter). With the use of four
phases clocking scheme as shown in Fig7 in controlling cells, QCA processes and forwards information within
cells in an arranged timing scheme The circuit area is divided into four sections and they are driven by four phase
clock signals.The four phases correspond to switch , hold , release and relax . In the switch phase, cells begin
unpolarized and with low potential barriers but the barriers are raised during this phase. In the hold phase, the
barriers are held high while in the release phase, the barriers are lowered. In the last phase, namely relax, the
barriers remain lowered and keep the cells in an unpolarized state. As shown in Figure7, there is a 90degree phase
shift from one section to the next. In each clock zone, the clock signal has four states: high-to-low, low, low-to-high,
and high. The cell begins computing during the high-to-low state and holds the value during the low state. The cell
is released when the clock is in the low to- high state and inactive during the high state.

V.LOGIC GATES DESIGN
The AND and OR gates are realized by fixing the polarization to one of the inputs of the majority gate to either
P = 1 (logic 0) or P = 1 (logic 1) as shown in Fig. below . Since NAND and NOR are complements of AND and OR.
Hence, are designed by adding an inverter to respective structures as shown in Fig.8
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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Figure 8. QCA AND,OR,NANAD,NOR GATES
For XOR gate, if inputs are different , then ouput is HIGH, else LOW. In case of, XNOR gate, the output is
complement of XOR gate. The layouts are designed with less number of cells as shown in Fig.9 .

FIG. 9 QCA XOR GATE

VI.COMBINATIONAL CIRCUITS DESIGN

A Combinational circuit consists of input variables, logic gates and output variables. The logic gates accept signals
from the inputs and generate the outputs which are different logic function combinations of the inputs. Firstly we
design the adder circuit, then all other Boolean functional circuits like subtractor, multiplier, divisor, comparator,
multiplexer, demultiplexer, encoder, decoder, differentiator, integrator etc can be easily constructed by the adder
circuit alone.


Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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A. Adder Circuit Design
Digital computers perform various arithmetic operations. The most basic operation is the addition . The addition
operation is achieved by majority logic that can reduce the overall number of gates required to create the adder .The
adder circuits design both half adder and full adder circuit.
B. Half Adder Circuit Design
Half adder circuit is designed conventionally by simple digital logic gates i.e. by Exclusive-Or (EX-OR), AND
gates etc. When two binary inputs A and B are added, according to the half adder truth table, the sum and the carry
are written as mentioned below:
Sum, S1 = A (+) B = AB'+A'B, where (+) is exclusive or (XOR) function or gate,
Carry, T1 = AB.
This half adder circuit is also designed by CMOS gates as well as QCA gates like MV, NOT, AOI, NNI, AND-
NAND, OR-NOR gates etc. the schematic and layout of half adder circuit is shown in fig. 10

Fig.10 schematic and layout of half adder
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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C. Full Adder Circuit Design
Full adder circuit is implemented by digital logic gates. If three binary inputs A, B and C are adding, the full
adder outputs i.e. the sum and the carry at par the truth table are as:
Sum:
S2=A(+)B(+)C
= AB'C'+A'BC'+A'B'C+ABC,
Carry,
T2 = AB + BC + CA.
Generally one full adder circuit is constructed by the two half adder circuits as shown in Fig. 11

FIG.11 Full Adder Using Two Half Adders
Full adder circuits designed with MV and NOT gates are shown in Fig. 12. It consists of three number MV
gates and two number NOT (Inverter) gates. Thus this full adder circuit with three binary inputs is comprising
with total five gates which are all based on QCA technology. It severely reduces the requirement of total gates and
circuitry as described in earlier cases. For making half adder circuit from this full adder circuit, one input is taken as
zero.

Fig 13. Full Adder Circuit
D. Subtractor Circuit Design
Subtraction of binary numbers is performed by taking the complement of the subtrahend and adding to the minued
as the same manner in addition. It is also possible to subtract binary numbers directly using logic gates. If the
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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minued bit is smaller than the subtrahend bit, a 1 is borrowed from the next higher significant bit position and it
is treated as the input for the next higher stage.
Half subtractor logic according to the truth table is like,
Subtract, D1 = X (+) Y = XY'+X'Y and
Borrow, B1 = X'Y, where X is minued and Y is subtrahend bit. Figure 14 shows the schematic and layout of half
subtractor.

Fig.14 schematic and layout of half adder
Full subtractor logic is also from the truth table like,
Subtract, D2 = X (+) Y (+) Z = XY'Z'+X'YZ'+X'Y'Z+XYZ,
Borrow, B2 = YZ + X'Y + X'Z.
The difference between adder and subtractor circuits is that Carry (T) and Borrow (B) differs by inverting the
first inputas shown in fig 15. Hence the same circuit with certain inputs can be used adder as well as subtractor
circuits by using a control input.
Proceedings of National Conference on Recent Advances in Electronics and Communication Engineering
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Figure 15 schematic of full subtractor
VII.CONCLUSION
Quantum dot Cellular Automata (QCA) is one of the emerging technologies for Nano scale computation.
We had discussed the QCA technology which is becoming emerging technology in quantum computation.
We had surveyed different logic gate designs for QCA. The adder and subtractor using QCA has been
designed and tested using QCA Designer software. The operation of the adder and subtractor has been verified
according to the truth table. The design works satisfactorily and
the ALU thus designed may be used as a basic building block of a general purpose Nan processor which
may be a future technical advancement of this work. This may pave way for the design and development
of other application oriented processors. .The results show that any QCA circuit can be made using only majority
gates and inverters.
VIII.REFERENCES

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