International Journal of EmergingTrends & Technology in Computer Science(IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org
Volume 3, Issue 3, May June 2014 ISSN 2278-6856
Volume 3, Issue 3 May June 2014 Page 14
Abstract: Today inverter is used for maximum control techniques of output voltage and current. That power semiconductor device able to reduces the harmonics and provide the high o/p voltage. Three reference signals are used for switching. This paper first discuss about single phase seven level inverter and that help we are implement the three phase seven level inverter and the switching combination for output voltage or level is (Vdc,2Vdc/3,Vdc/3,0,-2Vdc/3,-Vdc/3) for dc supply. Three phase inverter made by using that seven level o/p of single phase seven level inverter o/p. Result is compared with the conventional single phase seven level inverter grid connected PV inverter. THD and EMI result also in this paper with reduce the losses.THD reduce till 17%.
1. INTRODUCTION Recently we discuss about the number level inverter are increases and see the output voltage in different levels like three, five, seven etc. and the only one logic are used. In this paper we discuss with the help of 1-phase seven level inverter made a 3-phase seven level inverter. In the circuit model we used the combination of the resistance and capacitance in parallel with dc common source. MOSFET is high switching device used for the high efficiency output voltage[1]. FFT is used for harmonics analysis of output of three phase seven level inverter. In recently year multi level inverters have become more attractive for researchers and manufacturers due to their advantages over the five level inverters. They offer improved output waveforms, smaller filter size and lower EMI , and lower Total Harmonics Distortion(THD). Mainly three topologies used for inverters 1. Diode clamped (neutral clamped) 2. Capacitor clamped (flying capacitor) 3. Cascade H-bridge inverter.
To overcome this limitation, this paper presents a seven level inverter whose output voltage can be represented in following seven levels: Level Zero, Level +2/3Vdc Level +Vdc/3 Level Vdc Level -2/3Vdc Level -Vdc/3 Level Vdc.
As the number of output level increases, the harmonics content can be reduced. reference signals, instead of one reference signal or base signal to generate the PWM signals for the switches. Both the reference signals Vref1 and Vref2 are identical to each other , except for an offset value equivalent to the amplitude of the carrier signal V carrier, as shown in fig.
Figure 1 Reference and Carrier Signals.
2. SEVEN LEVEL PROPOSED INVERTER MODEL AND TOPOLOGY Multi level inverter are justify the wave form is near about the voltage output is sinusoidal and output current is reduced harmonics, very less switching losses, filter size is also small, THD is also low. The switching instant is determined from the crossing of the carrier and modulating signal.
Figure 2 Single-phase seven-level inverter. Simulation and Analysis of Single Phase Seven Level Inverter with Number of Switches are Reduce
1 Asst. Prof., Department of Electrical & Electronics,L.I.S.T Bhopal, India 2 M.Tech Scholar, Lakshmi Narain College of Technology Bhopal, India 3 M. Tech Scholar, Technocrats Institute of Technology(Excellence) Bhopal, India International Journal of EmergingTrends & Technology in Computer Science(IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org Volume 3, Issue 3, May June 2014 ISSN 2278-6856
Volume 3, Issue 3 May June 2014 Page 15
3. WORKING PRINCIPLE OF PROPOSED INVERTER In this model the switching chercherteristics are same pattern as five level inverter but the voltage level are different of switching. We use the PV system in this model for the input source we also use dc source when the no. of pv system employing in the circuit the known as Varrays. This Varrays boosted by dc-dc boost converter to exceed 1.414Vg. The principle operation of seven level inverter is based on reference signal and voltage levels(Zero, +2/3Vdc, +Vdc/3, Vdc, -2/3Vdc, -Vdc/3). The required seven levels of output voltage were generated as follows[2].
1) Maximum positive output (Vdc):- S1 is ON, connecting the load positive terminal to Vdc, and S4 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is Vdc. Fig. 3(a) shows the current paths that are active at this stage.
2) Two-third positive output (2Vdc/3): The bidirectional switch S5 is ON, connecting the load positive terminal, and S4 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is 2Vdc/3. Fig. 3(b) shows the current paths that are active at this stage.
3) One-third positive output (Vdc/3): The bidirectional switch S6 is ON, connecting the load positive terminal, to ground. All other controlled switches are OFF; the voltage applied to the load terminals is Vdc/3. Fig. 3(c) shows the current paths that are active at this stage.
4) Zero output: This level can be produced by two switching combinations; switches S3 and S4 are ON, or S1 and S2 are ON, and all other controlled switches are OFF; terminal ab is a short circuit, and the voltage applied to the load terminals is zero. Fig. 3(d) shows the current paths that are active at this stage.
5) One-third negative output (Vdc/3): The bidirectional switch S5 is ON, connecting the load positive terminal, and S2 is ON, connecting the load negative terminal to Vdc. All other controlled switches are OFF; the voltage applied to the load terminals is Vdc/3. Fig. 3(e) shows the current paths that are active at this stage.
6) Two-third negative output (2Vdc/3): The bidirectional switch S6 is ON, connecting the load positive terminal, and S2 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is 2Vdc/3. Fig. 3(f) shows the current paths that are active at this stage.
7) Maximum negative output (Vdc): S2 is ON, connecting the load negative terminal to Vdc, and S3 is ON, connecting the load positive terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is Vdc. Fig. 3(g) shows the current paths.
International Journal of EmergingTrends & Technology in Computer Science(IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org Volume 3, Issue 3, May June 2014 ISSN 2278-6856
Volume 3, Issue 3 May June 2014 Page 16
Figure 3 (Continued.) Switching combination required to generate the output voltage (V ab ). (e) V ab =V dc /3. (f) V ab =2V dc /3. (g) V ab =V d
Figure 4 Switching pattern for the single-phase seven- level inverter[3]. Table 1: OUTPUT VOL TAGE FROM SWITCH ON/OFF
4. SIMULATION OF SEVEN LEVEL INVERTER AND ITS WAVE FORMS
Figure 5 S1-S6 Switching signals
Figure 6: Simulation of seven level inverter. International Journal of EmergingTrends & Technology in Computer Science(IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org Volume 3, Issue 3, May June 2014 ISSN 2278-6856
Volume 3, Issue 3 May June 2014 Page 17
0 100 200 300 400 500 600 700 800 900 1000 -800 -600 -400 -200 0 200 400 600 800 TIME V O L T A G E (V ) SINGLE PHASE SEVENLEVEL INVERTER- VOLTAGE
Figure 7 Output voltage of seven level inverter. 0 100 200 300 400 500 600 700 800 900 1000 -0.005 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 C U R R E N T SINGLE PHASE SEVENLEVEL INVERTER- CURRENT TIME
Figure 8: Output current of seven level inverter.
5. SIMULATION AND WAVFORMS The proposed model can be practically implemented in a photovoltaic system simulation were performed by using MATLAB SIMULINK. The two carrier reference waveform is compare with the triangular carrier signal for produce PWM switching signals for switches. The simulation result are more efficent and accurate. The THD(Total Harmonics distortion) result is also calculated with the help of FFT. The implementation in three phase seven level inverter simulation result is also show in the paper. Simulation and wave form of this model shown in fig 5,6 and 7. Use of reference signal convert with the help of PWM method in seven level and simulation result in shown in fig. With the help of this signal can convert in three phase with the help of zig-zag transformer and also can convert with 120 degree phase shift in each reference signal or pulses.
6. FFT ANALYSIS FOR THD The harmonics distortion principally comes from Nonlinear-Type Loads. The application of power electronics is causing increased level of harmonics due to switching. Harmonic distortion can cause serious failure/damage problem. Harmonics are important aspect of power operation that requires Mitigation. Over-Sizing and power filtering methods are commonly used to limit overheating effects of sustained harmonics.
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 -500 0 500 Single Phase Seven Level Inverter FFT Time (s) v o l t a g e ( v ) 0 200 400 600 800 1000 0 1 2 3 4 5 Frequency (Hz) Fundamental (50Hz) =683.4 , THD=17.83% M a g
( %
o f
F u n d a m e n t a l )
7. RESULT AND CONCLUSION In this dissertation work I have carried out simulation for single phase seven level inverter by comparing sinusoidal reference wave with repetitive triangular as a carrier wave of a frequency 4KHz the output of inverter seven level. Because as a level increase so output waveform of a inverter near to sinusoidal of 50Hz frequency. The method is used to get this output reduces the number of switches compare other seven level multilevel inverter. Multi level inverter offers improved output waveform and lower THD. The new PWM switching scheme for in this proposed model . The behavior of multilevel inverter was analyzed in detail. By controlling the modulation index, the desired number of level of the inverter output voltage can be achieved. Some number of conclusion: 1. Harmonics decreases as the number of levels increase. 2. Increasing output voltage does not require an increase in voltage rating of individual devices. 3. It increases output voltage levels without any transformer. International Journal of EmergingTrends & Technology in Computer Science(IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org Volume 3, Issue 3, May June 2014 ISSN 2278-6856
Volume 3, Issue 3 May June 2014 Page 18
4. Multi level inverter offers improved output voltage waveform and lower THD.
References [1]. T.Karthikeyan and P. Satheesh kumar A Single phase seven level inverter for grid connected photovoltaic system by employing PID controller EEE Mailam Enggineering College, Villupuram, India [2]. Nasrudin A. Rahim, Krismadinata Chaniago, Jeyraj Selvaraj,Single-Phase Seven-Level Grid-Connected Inverter for Photovoltaic System IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 6, JUNE 2011 [3]. Thanuj kumar jala and G. Srinivasa rao A novel nine level grid-connected inverter for photovoltaic system IJMER Vol.2, Issue.2, March-April 2012 pp 154-459 [4]. M. Calais and V. G. Agelidis, Multilevel converters for single-phase grid connected photovoltaic systemsAn overview, in Proc. IEEE Int. Symp. Ind. Electron., 1998, vol. 1, pp. 224229. [5]. S.B. Kjaer, J. K. Pedersen, and F. Blaabjerg, A review of single-phase grid connected inverters for photovoltaic modules, IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 12921306, Sep./Oct. 2005. [6]. P. K. Hinga, T. Ohnishi, and T. Suzuki, A new PWM inverter for pho- tovoltaic power generation system, in Conf. Rec. IEEE Power Electron. Spec. Conf., 1994, pp. 391395. [7]. Y. Cheng, C. Qian, M. L. Crow, S. Pekarek, and S. Atcitty, A comparison of diode-clamped and cascaded multilevel converters for a STATCOM with energy storage, IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. . [8]. M. Saeedifard, R. Iravani, and J. Pou, A space vector modulation strategy for a back-to-back five- level HVDC converter system, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 452466, Feb. 2009.
AUTHOR
Naresh Kumar Varathe received the degree of B.E. in Electrical & Electronics Engg. from NRI Institute of Information Science and Technology Bhopal (MP) at 2009 and Master of Engg. (M.E) in Electrical Machines & Drives from SATI Vidisha,Under R.G.P.V. Bhopal at 2013. Presently working as a Asst. Prof. in Department of Electrical & Electronics Engineering of Laxmipati Institute of Science & Technology Bhopal, M.P.
Ketan Mishra is M.Tech Scholar (VLSI Design) from Lakshmi Narain College of Technology, Bhopal(M.P.), Under R.G.P.V. Completed his Bachelor of Engineering in Electronics & Tele Communication from Priyadarshini College of Engineering, Nagpur (M.H.)at 2012. Under Rashtra Santh Tukadogi Maharaj Nagpur University.
Shubham Shivhare received the degree of B.E. in Electronics & Communication from SAM College Of Engineering & Technology, Bhopal (M.P.) Under R.G.P.V. Bhopal (M.P.) in June 2012 And Pursuing M.Tech in Electronics & Communication from Technocrats Institute of Technology(Excellence), Bhopal (M.P.) Under R.G.P.V. Bhopal.