International Journal of Emerging Technologies and Engineering (IJETE)

Volume 1 Issue 5, June 2014, ISSN 2348 8050

131
www.ijete.org
Design, Implementation & Simulation of High Speed Low Area
Comparator with Different Architectures
Sumit Singh* ParikhaChawla**
*M.Tech Scholar, CBS Group of Institutions, Jhajjar
**Asst. Prof. ECE Deptt.,CBS Group of Institutions, Jhajjar
ABSTRACT
In A High Speed CMOS Comparator is proposed to
get high speed, low power dissipation, and low offset.
It uses the conventional data to form the new design as
base for improvement in design. The comparator is
having low voltage but not reduce to zero due to
internal parameters whose effect will be reduced in
future. The circuit designing obtained from Hysteresis
effects obviously having positive feedback. The
proposed structure is also immune against noise and
offset voltage.
The required area is reduced up to 2m from
conventional design. Structures are improved from
previous size to 80nm between areas of gate-to-drain
of Mosfet. Tested Circuit exhibited low propagation
delay, high speed, low area and low power dissipation.
These are compared to get superior circuits for digital
devices.
Keywords:CMOS, OFFSET, COMPARA, TORBER,
GATE, DRAIN, MOSFET.
1. INTRODUCTION
The basic Cmos Comparator & its schematic symbol
with operation of a voltage comparator are shown in
fig 1.1. The comparator can be thought of as a decision
making circuit based on input conditions.
Fig.1.1 Comparator
whereVp is Non-Inverting input, Vn is Inverted Input
& Vo is output voltage of comparator[3]. It is seen
from literature that a comparator is having 3 stages
namely: Preamplification, Decision circuit &Output
buffer. Stage 1 is responsible for amplification of
incoming signal so as to help in making a decision of
which voltage is high. Stage 2 is for making decision
& Stage 3 is for output buffer[7]. Conventional 3 stage
comparator uses in digital logic circuit. The circuit can
be implemented using GDPK 80m technology. In this
gate to drain channel size is 80m. The above
technique is also used in latched comparator &
hysteresis comparator also.
2. SYSTEM STRUCTURE FOR DIFFERENT
COMPARATORS.
3-Stage Comparator
Fig. 2.1 shows the circuit diagram for the model of 3-
Stage comparator. As we have already seen from the
circuit diagram. It uses a differential self-biased
amplifier with Output driver. It also consists of Latch
& preamplifier to perform the required functions.
Fig.2.1 Circuit Diagram for 3-Stage Comparator[6].
Performance Analysis of 3-Stage Comparator
The first stage is consisting of pre amplifier input is
voltage and output is current which relates as:
where,i
0+
& i
0-
are the current at the output of
preamplifier and v
+
& v
-
are the voltages at inputs.
Transconductance consider as gm.For the second
stage, we have consider i0+ is higher than i0- and
A
,

B
is consider as gain factor for nMOS&pMOS then
where, V
THN
is drain-to-source voltage for nMOS.For
saturated Mosfet, the current is written as
International Journal of Emerging Technologies and Engineering (IJETE)
Volume 1 Issue 5, June 2014, ISSN 2348 8050
132
www.ijete.org
Further increasing i0+ and decreasing i0- yield point as
Thus from above equations we can drive the relation
between switching point voltages as
&
V
SPL
= -V
SPH
for low & high voltages[4].
Fig.2.2 Transient Analysis circuit diagram of
Conventional 3-Stage Comparator.
Fig2.4 Extracted Layout of conventional comparator
Latched Based Comparator
The basic circuit diagram is shown in fig2.4. A
dynamic latch is defined as the memory unit that stores
the charge on the gate capacitance of the inverter.
Basic operation is based on the 2 phase of the clock.
First phase clock is high & switching transistor closes
& set to certain DC voltage around midpoint of
VCC[1]. In second phase inverter pair amplifies the
imbalance charge into digital voltage level.
Performance Analysis of latched-based
Comparator
The main parameters that affect the performance are:
Kick-Back Noise & Regenerative Time constant of
Latch. Isolation Transistors, preamplifier based design
or Neutralization is some commonly implemented
Techniques used to overcome from Kick-Back Noise.
Regenerative time constant can be reducing by
increasing time constant RC factor by changing gain of
inverter[5].
Fig 2.5 shows latched based comparator[2]
The Systematic circuit diagram is shown in fig 2.5.
Designing and simulation of circuit is done inOrCAD
or PSpice from Cadence Design System, Inc.
Fig 2.6 Systematic diagram of Latched based
Comparator.
From the simulation mode we can obtained the
different parameters valuelike voltage, current, time
delay, area of layout etc.
International Journal of Emerging Technologies and Engineering (IJETE)
Volume 1 Issue 5, June 2014, ISSN 2348 8050
133
www.ijete.org
Fig2.7 Extracted Layout of Latch-based Comparator
3. RESULT ANALYSIS
The simulation result for conventional 3-Stage
comparator is given in Table 1.
PARAMETER VALUE
OBTAINED
DELAY 0.152ns
SPEED 5.59 GHz
POWER
DESSIPATION
0.1032mW
AREA 195.39m2
It shows that Vir = 153.7ps and Vor = 0.224ns of first
cycle and Vir = 5.630ns and Vir = 5.396ns in second
cycle. The total average delay can be obtained by
taking the difference in time of first and second clock
cycle and divided by 2.
Table 2 Simulation result of Latch-based comparator
PARAMETER VALUE OBTAINED
DELAY 0.05485ns
SPEED 8.81GHz
POWER
DESSIPATION
1.74mW
AREA 166.32m2
It shows that Vir = 0.0150ns and Vor = 0.0971ns of
first cycle and Vir = 5.224ns and Vir = 5.50ns in
second cycle. By modification is done as per GDPK
80m.
The circuit has following analysis
Fig 3.1 Output Waveform of Comparator and Decision
Circuit
The circuit is analysis & the complete waveform is
shown in fig 2.2 above. It is seen from the simulation
result the switching speed is increased & area becomes
low.
Fig.3.2 Transient Analysis Waveform
4. CONCLUSION
The simulation result shows that Time delay in case of
conventional 3-Stage comparator is 0.152nanoseconds
while in case of Latch-based comparator it is
0.05485nanoseconds. The total decrease in time in
latch-based comparator is about 35% to that of
conventional comparator.
Power dissipation is 0.1032mW & 1.74mW in
Conventional comparator and latch-based comparator
respectively. It is clearly seen from the above result
that total power dissipation is increased. The total area
of the layout in Latch-based comparator is reduced
upto 14% from its counterpart conventional 3-Stage
comparatorcase.
REFERENCES
[1]. Journal on Design of Low power High Speed
CMOS Comparator for A/D Converter Application
by ShubharaYewale, RadheshyamGamad, Published
Online April 2012.
International Journal of Emerging Technologies and Engineering (IJETE)
Volume 1 Issue 5, June 2014, ISSN 2348 8050
134
www.ijete.org
[2]. International Journal on Design and Simulation of
a High Speed CMOS Comparator
bySmritiShubhanand, Dr. H.P. Shukla and A.G. Rao at
National Institute of Electronics and Information
Technology, Gorakhpur.
[3]. P Philip E. Allen and Douglas R. Holberg, CMOS
Analog Circuit Design (oxford University Press, Inc,
USA, 2002), 2
nd
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[4]. Noor Aizad, Design and implementation of
comparator for sigma-delta modulator.
[5]. B.Razavi and B.A.Wooley, Design Techniques
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1992.
[6].AllertH.P. Le, A. Zayegh, and J. Singh,
"Performance analysis of optimized
CMOScomparator," Electronics Letter, vol. 39, pp.
833-835, May 2003.
[7]. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, A
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