Professional Documents
Culture Documents
FEATURES
Recovers Signal from +100 dB Noise
2 MHz Channel Bandwidth
45 V/s Slew Rate
120 dB Crosstalk @ 1 kHz
Pin Programmable Closed Loop Gains of 1 and 2
0.05% Closed Loop Gain Accuracy and Match
100 V Channel Offset Voltage (AD630BD)
350 kHz Full Power Bandwidth
Chips Available
Balanced Modulator/Demodulator
AD630
FUNCTIONAL BLOCK DIAGRAM
CM OFF
ADJ
CM OFF
ADJ
DIFF OFF
ADJ
DIFF OFF
ADJ
2.5k
RINA
CHA+
AD630
AMP A
CHA 20
12
COMP
11
+VS
13
VOUT
14
RB
15
RF
16
RA
2.5k
RINB 17
AMP B
10k
CHB+ 18
10k
CHB 19
5k
PRODUCT DESCRIPTION
The AD630 is a high precision balanced modulator which combines a flexible commutating architecture with the accuracy and
temperature stability afforded by laser wafer trimmed thin-film
resistors. Its signal processing applications include balanced
modulation and demodulation, synchronous detection, phase
detection, quadrature detection, phase sensitive detection,
lock-in amplification and square wave multiplication. A network
of on-board applications resistors provides precision closed loop
gains of 1 and 2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer
gains of +1, +2, +3 or +4. Alternatively, external feedback may
be employed allowing the designer to implement his own high
gain or complex switched feedback topologies.
The AD630 may be thought of as a precision op amp with two
independent differential input stages and a precision comparator
which is used to select the active front end. The rapid response
time of this comparator coupled with the high slew rate and fast
settling of the linear amplifiers minimize switching distortion. In
addition, the AD630 has extremely low crosstalk between channels of 100 dB @ 10 kHz.
The AD630 is intended for use in precision signal processing
and instrumentation applications requiring wide dynamic range.
When used as a synchronous demodulator in a lock-in amplifier
configuration, it can recover a small signal from 100 dB of interfering noise (see lock-in amplifier application). Although optimized
for operation up to 1 kHz, the circuit is useful at frequencies up
to several hundred kilohertz.
Other features of the AD630 include pin programmable frequency
compensation, optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment,
and a channel status output which indicates which of the two
differential inputs is active. This device is now available to Standard Military Drawing (DESC) numbers 5962-8980701RA and
5962-89807012A.
COMP
SEL B 9
CHANNEL
STATUS
B/A
SEL A 10
8
VS
PRODUCT HIGHLIGHTS
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Model
Min
GAIN
Open Loop Gain
1, 2 Closed Loop Gain Error
Closed Loop Gain Match
Closed Loop Gain Drift
CHANNEL INPUTS
VIN Operational Limit1
Input Offset Voltage
Input Offset Voltage
TMIN to TMAX
Input Bias Current
Input Offset Current
Channel Separation @ 10 kHz
COMPARATOR
VIN Operational Limit1
Switching Window
Switching Window
TMIN to TMAX2
Input Bias Current
Response Time (5 mV to +5 mV Step)
Channel Status
ISINK @ VOL = VS + 0.4 V3
Pull-Up Voltage
AD630J/A
Typ
Max
110
0.1
0.1
2
90
100
200
AD630K/B
Typ
Max
120
800
300
50
100
10
100
2.0
300
100
200
10
160
300
50
2.0
300
100
200
90
90
5
110
110
4
16.5
5
0
25
(VS + 33 V)
90
90
5
0
25
V
nA
nA
dB
Volts
mV
mV
nA
ns
mA
Volts
MHz
V/s
s
110
110
dB
dB
Volts
mA
16.5
5
Volts
mA
25
+70
+85
Volts
V
2
45
3
25
+70
+85
2.5
300
10
10
25
1000
300
50
1.6
(VS + 33 V)
Units
dB
%
%
ppm C
2
45
3
16.5
5
110
0.1
0.1
2
100
10
100
1.6
105
110
Max
(VS +4 V) to (+VS 1 V)
500
2
45
3
OUTPUT VOLTAGE, @ RL = 2 k
TMIN to TMAX2
Output Short Circuit Current
90
(VS +4 V) to (+VS 1 V)
100
(VS + 33 V)
85
90
5
AD630S
Typ
1.6
OPERATING CHARACTERISTICS
Common-Mode Rejection
Power Supply Rejection
Supply Voltage Range
Supply Current
Min
0.05
0.05
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Slew Rate4
Settling Time to 0.1% (20 V Step)
TEMPERATURE RANGES
Rated PerformanceN Package
Rated PerformanceD Package
100
(VS + 4 V) to (+VS 1 V)
500
100
10
100
Min
N/A
55
+125
C
C
NOTES
1
If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.
2
These parameters are guaranteed but not tested for J and K grades. For A, B and S grades they are tested.
3
ISINK @ VOL = (VS + 1) volt is typically 4 mA.
4
Pin 12 Open. Slew rate with Pins 12 and 13 shorted is typically 35 V/ s.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 600 mW
Output Short Circuit to Ground . . . . . . . . . . . . . . . . Indefinite
Storage Temperature, Ceramic Package . . . . 65C to +150C
Storage Temperature, Plastic Package . . . . . . 55C to +125C
Lead Temperature Range (Soldering, 10 sec ) . . . . . . . +300C
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150C
THERMAL CHARACTERISTICS
JC
JA
24C/W
35C/W
35C/W
61C/W
120C/W
120C/W
2
Model
Temperature
Range
Package
Description
Package
Option
AD630JN
AD630KN
AD630AD
AD630BD
AD630SD
AD630SD/883B
5962-8980701RA
AD630SE/883B
5962-89807012A
AD630J Chip
AD630S Chip
0C to +70C
0C to +70C
25C to +85C
25C to +85C
55C to +125C
55C to +125C
55C to +125C
55C to +125C
55C to +125C
0C to +70C
55C to +125C
Plastic DIP
Plastic DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
LCC
LCC
Chip
Chip
N-20
N-20
D-20
D-20
D-20
D-20
D-20
E-20A
E-20A
REV. A
AD630
CHIP METALIZATION AND PINOUT
PIN CONFIGURATIONS
20 CH A
CH A+ 2
19 CH B
18 CH B+
17 RIN B
AD630
CM OFF ADJ 5
16 RA
TOP VIEW
CM OFF ADJ 6 (Not to Scale) 15 RF
14 RB
CHANNEL STATUS B/A 7
VS 8
13 VOUT
SEL B 9
12 COMP
SEL A 10
11 +VS
CH A
1 20 19
CH B
RIN A
CHIP AVAILABILITY
CH A+
DIFF
OFF ADJ
18 CH B+
17 RIN B
CM OFF ADJ 5
AD630
CM OFF ADJ 6
TOP VIEW
(Not to Scale)
16 RA
15 RF
14 R
B
VS 8
15
5k
Vi
5k
5k
VO
2k
100pF
CL = 100pF
f = 1kHz
10
5k
5k
Vi
VO
RL
CAP IN
1k
10k
100k
FREQUENCY Hz
1M
100
1k
10k 100k
RESISTIVE LOAD
VO
5
f = 1kHz
CL = 100pF
5
10
15
SUPPLY VOLTAGE V
60
120
100pF
10
1M
5k
Vi
2k
80
20
40
0
COMPENSATED
20
40
20
dt
60
100
OPEN LOOP GAIN dB
40
V/s
100
10
100
1k
10k
FREQUENCY Hz
100k
Figure 4. Common-Mode
Rejection vs. Frequency
REV. A
60
5 4 3 2 1 0 1 2 3
INPUT VOLTAGE V
Figure 5.
45
80
60
40
90
COMPENSATED
135
20
0
dVO
vs. Input Voltage
dt
3
UNCOMPENSATED
10
100
1k 10k 100k
FREQUENCY Hz
1M
180
10M
UNCOMPENSATED
DVO
10
100pF
OUTPUT VOLTAGE V
OUTPUT VOLTAGE V
OUTPUT VOLTAGE V
15
10
VOUT
+VS
18
15
RL= 2k
CL = 100pF
COMP
SEL A
SEL B
9 10 11 12 13
15
16
5k
20
CH
A
VO
13
Vi
TOP
TRACE
12
CH
B
2 CH A
12
1k
10k
14
Vi
10k
14 10k 15 20
19
18
10k
10k
MIDDLE
TRACE
(A)
30pF
VO
BOTTOM
TRACE
13
Vi
TOP
TRACE
14
15
10k
20
2 CH A
12
VO
BOTTOM
TRACE
13
10k
10k
10k
10k
(B)
MIDDLE
TRACE
HP5082-2811
TEKTRONIX
7A13
10
The functional block diagram of the AD630 also shows the pin
connections of the internal functions. An alternative architectural diagram is shown in Figure 10. In this diagram, the
individual A and B channel preamps, the switch, and the integrator output amplifier are combined in a single op amp. This
amplifier has two differential input channels, only one of which
is active at a time.
Vi
RA 5k
VO
10
RB
10k
2.5k
RF
10k
When channel B is selected, the resistors RA and RF are connected for inverting feedback as shown in the inverting gain
configuration diagram in Figure 12. The amplifier has sufficient
loop gain to minimize the loading effect of RB at the virtual
ground produced by the feedback connection. When the sign of
the comparator input is reversed, input B will be deselected and
A will be selected. The new equivalent circuit will be the noninverting gain configuration shown below. In this case RA will appear
across the op-amp input terminals, but since the amplifier drives
this difference voltage to zero the closed loop gain is unaffected.
13
19
B
12
2.5k
17
7
SEL B
13
B
18
18
RF
10k
14
14
20
19
RB
10k
11
16
15
20
+VS
15
RA
16 5k
B/A
SEL A 10
8
VS
The two closed loop gain magnitudes will be equal when RF/RA
= 1 + RF/RB, which will result from making RA equal to RFRB/
(RF + RB) the parallel equivalent resistance of RF and RB.
The 5k and the two 10k resistors on the AD630 chip can be
used to make a gain of two as shown here. By paralleling the
10k resistors to make RF equal 5k and omitting RB the circuit
can be programmed for a gain of 1 (as shown in Figure 18a).
These and other configurations using the on chip resistors
present the inverting inputs with a 2.5k source impedance. The
more complete AD630 diagrams show 2.5k resistors available at
the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents.
REV. A
AD630
faster the output signal will move. This feature helps insure
rapid, symmetric settling when switching between inverting and
noninverting closed loop configurations.
RF 10k
RA
5k
Vi
RB
10k
RF
V
RA i
VO =
RA
5k
VO = (1+
RF
RB
) Vi
RF
10k
RB
10k
20
+VS
CH B
CH A+ CH B+
CH A
18
19
11
Q33
Q35
Q34
Q36
i55
i73
Q44
SEL A
10
Q52
Q53
Q62
Q65
Q67
Q70
13
C121
SEL B
Q30
12
COMP
Q31
Q28
C122
Q29
Q24
Q3
VS
VO
Q74
Q4
i22
Q32
Q25
i23
8
3
DIFF
OFF ADJ
DIFF
OFF ADJ
CM
OFF ADJ
CM
OFF ADJ
2k
10k
100k
Vi
2
20
The collectors of each switching cell connect to an input transconductance stage. The selected cell conveys bias currents i22
and i23 to the input stage it controls causing it to become active.
The deselected cell blocks the bias to its input stage which, as a
consequence, remains off.
13
VO
19
11.11k
18
12
7
9
10
8
V S
while the low frequency components will be amplified. This arrangement is useful in demodulators and lock-in amplifiers. It
increases the circuit dynamic range when the modulation or
interference is substantially larger than the desired signal amplitude. The output signal will contain the desired signal multiplied by the low frequency gain (which may be several hundred
for large feedback ratios) with the switching signal and interference superimposed at unity gain.
2k
AD630
This is because the open collector channel status output inverts
the output sense of the internal comparator.
+5V
100k
1M
100k
9
10
8
15V
100
FREQUENCY COMPENSATION
+5V
+15V
6.8k
When the AD630 is used as a multiplexer, or in other configurations where one or both inputs are connected for unity gain
feedback, the phase margin will be reduced to less than 20.
This may be acceptable in applications where fast slewing is a
first priority, but the transient response will not be optimum.
For these applications, the self-contained compensation capacitor may be added by connecting Pin 12 to Pin 13. This connection reduces the closed loop bandwidth somewhat, and improves
the phase margin.
100k
AD630
22k
IN 914's
TTL INPUT
2N2222
8
15V
For intermediate conditions, such as gain of 1 where loop attenuation is 2, use of the compensation should be determined
by whether bandwidth or settling response must be optimized.
The optional compensation should also be used when the AD630
is driving capacitive loads or whenever conservative frequency
compensation is desired.
OFFSET VOLTAGE NULLING
MODULATION
INPUT
10k
CM
ADJ
DIFF
ADJ
4
2.5k
1
AMP A
12
11
20
2.5k
17
18
B
AMP B
CARRIER
INPUT
10k
14
19
+VS
13
10k
AD630
COMP
MODULATED
OUTPUT
SIGNAL
15
16
5k
7
9
10
8
VS
REV. A
AD630
10k
MODULATION
INPUT
10k
CM
ADJ
DIFF
ADJ
Many transducers function by modulating an ac carrier. A Linear Variable Differential Transformer (LVDT) is a transducer of
this type. The amplitude of the output signal corresponds to
core displacement. Figure 20 shows an accurate synchronous
demodulation system which can be used to produce a dc voltage
which corresponds to the LVDT core position. The inherent
precision and temperature stability of the AD630 reduce demodulator drift to a second order effect.
2.5k
1
AMP A
12
11
20
2.5k
17
B
AMP B
19
CARRIER
INPUT
10k
14
18
+VS
13
10k
AD630
COMP
MODULATED
OUTPUT
SIGNAL
15
16
E1000
AD544
SCHAEVITZ
FOLLOWER
LVDT
16 B 5k
5k
7
10
8
AD630
2 DEMODULATOR
15
2.5kHZ
2V pk-pk
SINUSOIDAL
EXCITATION
VS
2.5k
14
10k
20
10k
A
C 13 100k
19
B
17
12
1F
2.5k
PHASE
SHIFTER
10
Bridge circuits which use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the
electronics, and line noise pick-up. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the
carrier frequency and can be removed by means of a low-pass
filter. Dynamic response of the bridge must be traded off against
the amount of attenuation required to adequately suppress these
residual carrier components in the selection of the filter.
Figure 21 is an example of an ac bridge system with the AD630
used as a synchronous demodulator. The oscilloscope photograph shows the results of a 0.05% bridge imbalance caused by
the 1 Meg resistor in parallel with one leg of the bridge. The top
trace represents the bridge excitation, the upper-middle trace is
the amplified bridge output, the lower-middle trace is the output of the synchronous demodulator and the bottom trace is the
filtered dc system output.
This system can easily resolve a 0.5 ppm change in bridge impedance. Such a change will produce a 3.2 mV change in the
low-pass filtered dc output, well above the RTO drifts and noise.
1kHz
BRIDGE
EXCITATION
A
1k
AD630
2 DEMODULATOR
1k
AD524
GAIN 1000
1k
16
1k
5k
15
2.5
k
20
1M
17
2.5
k
10k
A
B
FILTER
5k 5k 5k
13
2
12
10k
14
PHASE
SHIFTER
9
10
2F
2F
D
2F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C
B 16
AD542
5k
AD630
15
20
19
100R
10k
1 2.5k
17 2.5k
100dB
ATTENUATION
C784a27/84
AD630
AD542
13
B
100R
14 10k
C
OUTPUT
10
0.1Hz
9
MODULATED
400Hz
CARRIER
CARRIER
PHASE
REFERENCE
LOW PASS
FILTER
PRINTED IN U.S.A.
LCC (E-20A)
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.095 (2.41)
0.075 (1.90)
0.028 (0.71)
0.022 (0.56)
20
0.011 (0.28)
0.007 (0.18)
R TYP
0.088 (2.24)
0.054 (1.37)
0.015 (0.38)
MIN
0.075
(1.91)
REF
0.200 (5.08)
BSC
0.100
(2.54)
BSC
0.055 (1.40)
0.045 (1.14)
BOTTOM
VIEW
13
9
0.150
(3.81)
BSC
0.050
(1.27)
BSC
45
TYP
REV. A