International Journal of Nanoscience

© World Scientific Publishing Company

Vol.7, pp.81 - 84, April & June 2008.

QUANTUM CONFINEMENT EFFECTS IN STRAINED SILICON MOSFETS

M. JAGADESH KUMAR†
Department of Electrical Engineering, Indian Institute of Technology,
New Delhi 110 016, India

TARUN VIR SINGH

Department of Electrical Engineering, Indian Institute of Technology,
New Delhi 110 016, India

Received (Day Month Year)

Revised (Day Month Year)

In this paper, we have examined the effect of quantum confinement of carriers on the threshold
voltage of strained-silicon (s-Si) nanoscale Metal Oxide Semiconductor Field Effect Transistors
(MOSFETs). Using results from quantum theory and two-dimensional simulation, we show that
strain-induced threshold voltage roll-off in s-Si nanoscale MOSFETs can be overcome by
decreasing s-Si layer thickness. Based on our simulation study, we provide an optimization
between threshold voltage, strain and s-Si layer thickness.

Keywords: Strained-silicon; Quantum confinement; MOSFET, Threshold voltage.

1. Introduction
Strained-silicon Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are
gaining popularity due to enhanced mobility and high field velocity1-3. Strained-silicon on
insulator (SSOI) MOSFETs combine the carrier transport advantages of s-Si with
reduced parasitic capacitance and increased scalability of SOI MOSFETs4,5. A major
concern with s-Si MOSFETs is the decrease in the threshold voltage as strain increases6-8
due to the decrease in the bandgap of s-Si with strain9. In this paper, we show that this
effect can be reversed by decreasing the thickness of the s-Si layer, which increases the
effective bandgap due to quantum confinement.
Although quantum confinement effects are well known10, to the best of our
knowledge its impact on optimizing the threshold voltage of s-Si MOSFETs has not been
studied so far. Using two-dimensional simulation, we demonstrate in this study that the
decrease in the threshold voltage of s-Si MOSFETs with strain can be minimized by

†
Author for correspondence – M. Jagadesh Kumar (email: mamidala@ieee.org).

1
2 Authors’ Names

reducing the s-Si layer thickness. We show that the threshold voltage can be optimized by
choosing different combinations of strain and s-Si layer thickness.
SiO2 s-Si SiGe

q=2

q=1
EC
E’g Eg
EV
q=1

q=2

ΔEg= E’g- Eg

Fig. 1. Cross-sectional view of the strained-Si on SGOI MOSFET and its energy band diagram along the middle
of the device in the Y-direction.

2. Quantum Confinement Effects

The s-Si SOI MOSFET structure used in the present study and its associated energy band
diagram in the middle of the channel are shown in Fig.1. The s-Si layer forms a quantum
well between the two potential barriers formed by the gate oxide and the SiGe layer. The
confinement of electrons into a very thin region increases the energy gap between
allowed energy levels. The first energy level in the conduction band is above EC, while
the first energy level in the valence band is below EV. This leads to an increase in the
energy bandgap10. The increase in the bandgap for s-Si can be modeled as:
η2π 2
ΔE g = (1)
2mr t s2− Si
1 1 1
where = +
m r me m h
me and mh are the effective masses of the electron and hole respectively, ts-Si is the s-Si
layer thickness. Using η = h(2π ) −1 and substituting h=6.63×10-34 J.s in Eq. (1), we get
75 meV
ΔE g = (2)
mrr t s2− Si
mr
where mrr =
m0
 Instructions for Typing Manuscripts (Paper’s Title) 3

and m0 is the mass of electron in free space. Strain-induced decrease in the bandgap of
silicon is given by9:
ΔE g = −0.4 x (3)
Where x is the mole fraction of Ge in SiGe. Hence, the overall change in the bandgap of
strained silicon is given by
Table 1: Device parameters used in the simulation

Parameter Value
Ge mole fraction of SiGe substrate, x 0 – 0.4 (0 – 40%)
Strained-Silicon film thickness, ts-Si 2-7 nm
Channel Length, L 50 nm, 100 nm
Source/Drain doping, ND 1019 cm-3
Doping in SiGe layers, NA 1016 cm-3
Doping in s-Si layer, NA 1016 cm-3
Drain bias, VDS 50 mV
Gate Oxide Thickness, t ox 2.0 nm
Work function of gate material, φM 4.8 eV

⎛ 0.075 ⎞
ΔE g = ⎜⎜ 2
− 0.4 x ⎟⎟eV (4)
⎝ mrr t s − Si ⎠
Thus, bandgap increases with decreasing ts-Si and decreases with increasing
strain. These two opposing effects can be used to optimize the threshold voltage of s-Si
MOSFETs, since the threshold voltage is positively related to the bandgap Eg.

3. Results and Discussion

To verify the above theoretical predictions, the 2-D device simulator ATLAS11 was used
to simulate the structure shown in Fig.1. The parameters used in our simulation are given
in Table 1. To incorporate the effects of quantum confinement, we have used the self-
consistent coupled Schrödinger-Poisson model12 in which the Schrödinger and Poisson’s
equations are solved alternately. Once the Schrödinger equation is solved, the calculated
carrier concentration is substituted into the charge part of Poisson’s equation. The
potential derived from the solution of the Poisson’s equation is substituted back into
Schrödinger equation. This solution process (alternating between Schrödinger and
Poisson equations) continues until convergence and a self-consistent solution to both
equations is reached. The electron concentration calculated using the above process is
shown in Fig. 2 along the Y-direction in the middle of the device. We notice that the
inversion layer charge is confined to the s-Si layer. To estimate the threshold voltage, we
have used the electron concentration profile along the X-direction plotted at the peak of
electron concentration shown in Fig. 2. Threshold voltage is defined as the value of gate
voltage at which the minimum of this concentration profile becomes equal to the
background doping concentration NA forming a conducting path.
 4 Authors’ Names

Fig.3 shows the electron concentration profile from source to drain in the centre
of s-Si layer along X-direction, for s-Si layer thicknesses of 2 nm and 7 nm with a Ge
mole fraction x = 0.4. The lower electron concentration in the 2 nm s-Si layer device is
due to its higher bandgap caused by quantum confinement effects. This device therefore
requires a higher gate voltage for increasing its carrier concentration to a value high
enough for conduction to take place, thereby increasing its threshold voltage. Therefore a

1017
s-Si SiGe
ts-Si = 5 nm
1016 L = 100 nm
Electron Concentration (cm-3)

VDS = 50 mV
VGS = 0.28 V
1015 x = 0.2

1014

1013

1012
0 2 4 6 8 10 12 14 16
Distance (nm)
Fig. 2. Electron concentration profile along the middle of the device in the Y-direction.

1020
L = 100 nm
10 19
Source VDS = 50 mV Drain
Electron Concentration (cm-3)

VGS = 0.2 V
1018 x = 0.4
ts-Si = 7 nm
1017

1016

1015
ts-Si = 2 nm
14
10

1013
0 10 20 30 40 50 60 70 80 90 100
Position along the Channel (nm)
 Instructions for Typing Manuscripts (Paper’s Title) 5

Fig. 3. Electron concentration profile along the middle of the strained-Silicon layer in the X-direction.

L = 100nm
0.5 L = 50nm
Threshold Voltage (volts)

x=0 VDS = 50 mV
0.4
x = 0.2
0.3

0.2

0.1 x = 0.4

0
2 3 4 5 6 7
s-Si Layer Thickness (nm)

Fig. 4. Variation of the threshold voltage with strained-Si film thicknesses for different values of strain x (Ge
content in the SiGe film).

reduction in the threshold voltage due to increased Ge mole fraction can be compensated
by decreasing the s-Si layer thickness.
Fig.4 shows the variation in the threshold voltage of the device as a function of
s-Si layer thickness for various values of strain (Ge mole fraction in SiGe) and for two
different channel lengths. The threshold voltage increases as ts-Si decreases as indicated by
equation (4) for the strained-silicon MOSFET. We notice from Fig. 4 that even for the
largest Ge mole fraction (x = 0.4), s-Si MOSFETs with reasonable threshold voltages can
be realized if the thickness of the s-Si layer is reduced to 2 nm. This becomes even more
important for lower channel lengths (e.g. 50 nm) as indicated in the Fig. 4 where the
threshold voltage enhancement is more than 100 % for x = 0.4. However it may be
pointed out that when the strained silicon film thickness is reduced below 5 nm, the
inversion layer electron mobility does come down. However, recently it has been shown
that in spite of this fall in mobility, strained silicon MOSFETs with body thickness below
5 nm do have a significantly larger mobility than the ultrathin body SOI MOSFETs13.
Fig.5 shows the variation in the threshold voltage of the device as a function of
strain for various values of s-Si layer thickness and channel length. The threshold voltage
decreases linearly as strain increases. Threshold voltage roll-off can also be observed as
channel length decreases from 100 nm to 50 nm. Threshold voltage roll-off with
increasing strain and decreasing channel length can both be overcome by decreasing ts-Si.
For two different channel lengths, Fig. 6 shows the various combinations of Ge
mole fraction x and s-Si film thickness ts-Si that results in a particular constant threshold
6 Authors’ Names

voltage. We can, therefore, clearly see that the benefits of strained strained-silicon using
higher Ge mole fraction can still be retained while keeping the threshold voltage
reasonably large if the strained-silicon film thickness is reduced to values below 3 nm.
 Instructions for Typing Manuscripts (Paper’s Title) 7

0.6
L = 100nm
L = 50nm
0.5
VDS = 50 mV
Threshold Voltage (volts)

0.4 ts-Si = 2 nm

0.3

0.2 ts-Si = 4 nm

0.1
ts-Si = 7 nm
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Strain (%Ge)
Fig. 5. Variation of the threshold voltage with strain x (Ge content in the SiGe film) for different strained-Si
film thicknesses.

0.45
0.4 L = 100 nm
0.35 L = 50 nm
Strain (%Ge)

VDS = 50 mV
0.3
0.25
0.2 VT = 0.25
0.15
0.1
VT = 0.35
0.05
0
2 3 4 5 6 7
s-Si Layer Thickness (nm)
Fig. 6. The relation between strain x and strained-Si film thickness ts-Si for constant threshold voltages.
8 Authors’ Names

5. Conclusions
In this work, we have examined the effect of s-Si layer thickness on the threshold voltage
of strained-silicon MOSFETs using simulation. We have shown that by reducing the s-Si
layer thickness to the quantum mechanical regime, the effective bandgap of s-Si can be
increased counter balancing the reduction in threshold voltage due to increased strain.
This, therefore, permits the designer to realize nanoscale strained-silicon MOSFETs with
good gate control while allowing a higher Ge mole fraction for increased strain and hence
a better device performance.

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