Interesting and informative Paper that I used in EM trace modeling with HFSS.
Authors:
Mohammad Almalkawi, Zulfiqar Khan, Vijay Devabhaktuni, Charles Bunting
Original Title
Far-End Crosstalk Reduction in Adjacent PCB Traces employing High/Low-Z Configurations
Interesting and informative Paper that I used in EM trace modeling with HFSS.
Authors:
Mohammad Almalkawi, Zulfiqar Khan, Vijay Devabhaktuni, Charles Bunting
Interesting and informative Paper that I used in EM trace modeling with HFSS.
Authors:
Mohammad Almalkawi, Zulfiqar Khan, Vijay Devabhaktuni, Charles Bunting
Mohammad Almalkawi #1 , Zulfiqar Khan #2 , Vijay Devabhaktuni #3 , Charles Bunting *4
# EECS Department, University of Toledo, Toledo, OH 43606, USA.
1 mohammad.almalkawi@utoledo.edu 2 zulfiqar.khan@utoledo.edu 3 vijay.devabhaktuni@utoledo.edu * Department of Electrical and Computer Engineering, Oklahoma State University, Stillwater, OK 74078, USA. 4 reverb@okstate.edu
AbstractThis paper introduces a new High/Low-Z trace configuration to reduce far-end crosstalk in adjacent printed circuit board (PCB) interconnects. The emphasis is made to reduce crosstalk without using additional PCB components in the design. Specifically, we employ stepped impedance elements of uniform length on the victim traces to suppress high-frequency electromagnetic interference. The overall design is much simpler than the usual low-pass filter configurations which are difficult to implement in the prototype testing. The proposed approach shows remarkably better results as compared to conventional intervening guard trace schemes. Further, the proposed configuration can be combined with the conventional schemes to achieve even higher reduction in crosstalk. I. INTRODUCTION Crosstalk in PCB traces is a well known EMC and signal integrity problem. A typical scenario involves coupling of a high-frequency signal (e.g. a digital clock) onto a low frequency trace (e.g. a power or a ground trace). Since low- frequency traces are typically long traces routed on multiple layers on a PCB, high-frequency interference may easily radiate from multiple and/or little suspected locations on the printed board. Therefore, it is usually very difficult to determine the actual location of the radiating area on the board. Normally, the first line of defence is to mitigate the radiation source by reducing the current strength, slewing the rise/fall time of the digital signal (e.g. by adding series resistors or ferrites [1]) or shortening/straightening the high-frequency trace. Though such countermeasures may provide a limited improvement, they may not even be an option for a given design (e.g. for signal integrity constraints). Another way to reduce crosstalk is to exploit the inherent parasitic effects (i.e. mutual capacitance and inductance) among PCB traces [2-4]. To this end, different configurations of guard traces have been employed in between adjacent interconnects [2, 5, 6]. However, routing additional traces may not be possible in a crowded layout. Furthermore, crosstalk reduction provided by guard traces is limited and is usually not sufficient [2, 7]. Therefore, it is highly desirable to explore new trace configurations that may provide better crosstalk reduction and can be routed in a crowded layout. One way is to employ the low-pass filter (LPF) configuration on the victim traces. A typical LPF employs multiple stepped impedance elements on the victim trace with much better performance compared to that achieved by using guard traces alone. However, since stepped elements have non-uniform lengths and widths, it is very difficult to implement different LPF configurations on PCB traces in a prototype testing. To this end, this paper introduces a new High/Low-Z victim trace configuration to reduce far-end crosstalk coupling between two adjacent PCB traces. The far-end crosstalk is of particular interest due to the significantly stronger coupling as compared to that at the near-end [8]. The proposed configuration has LPF characteristics [9] as it employs stepped impedance elements. However, here elements have uniform lengths and, therefore, are easier to implement in the prototype testing in EMC pre-compliance/compliance chambers. Furthermore, the proposed configuration shows similar performance to the LPF design and can be combined with the guard traces for even better results. The conventional and proposed crosstalk reduction configurations are given in Section II. Section III compares these PCB configurations in terms of crosstalk reduction in adjacent PCB traces, while conclusions are given in Section IV. II. CROSSTALK REDUCTION SCHEMES Fig. 1 illustrates a PCB structure (40 mm x 40 mm) with two adjacent traces that are spaced 8 mm apart. Both traces are 3 mm wide and 40 mm long. As illustrated, the PCB structure is supported by a 1.575 mm thick FR4 substrate. We assume that one trace (acting as an aggressor) is carrying digital or high-frequency signals. These signals may couple onto the adjacent trace (hereby referred as the victim trace) carrying low-frequency or DC currents. To reduce this coupling, referred to as crosstalk, various configurations can be employed. Below, we discuss conventional configurations as well as our proposed configuration. A. Guard Trace for Far-End Crosstalk Reduction As illustrated in Fig. 2, a guard trace is usually introduced (as a shield) in between the aggressor and the victim trace. For additional shielding, one may also ground the guard trace with 760 U.S. Government work not protected by U.S. copyright
Fig. 1. PCB structure with two uniform adjacent traces.
Fig. 2. PCB structure with a guard trace between two uniform parallel traces. via fences (see Fig. 3). In this paper, we will assume that the guard trace is 1 mm wide and is terminated at both ends by the matched impedance (i.e. 87 ). We further assume that the spacing between each via on the guard trace is 2 mm. B. Low-Pass Filter (LPF) Configuration If victim trace is a low-frequency or a DC trace, one may employ a stepped impedance LPF configuration, i.e. using elements of high and low impedance alternatively on the trace (see Fig. 4). Length Hi l of the high impedance ( H Z ) element can be calculated using the electrical length defined as [9], H Hi Z LR l 0 = , (1) where 2 = , corresponds to the cut-off frequency of the LPF, and 0 R represents the feed trace characteristic impedance. Similarly, length Li l of the low impedance element ( L Z ) can be calculated as, 0 R CZ l L Li = , (2) where L and C are the lumped element values [10]. The width of elements is chosen corresponding to impedances H Z and L Z . It is worth mentioning that the difference between the two impedances should be as high as possible for an excellent filter performance (i.e. sharper cutoff). For higher crosstalk reduction, LPF configuration can also be employed with guard
Fig. 3. Guard trace with ground vias.
Fig. 4. Stepped impedance configuration with 5 elements.
Fig. 5. Stepped impedance configuration along with a guard trace.
Fig. 6. Stepped impedance configuration with a guard trace grounded by vias. 761 traces (Fig. 5) and grounded guard traces (Fig. 6). However, in our case, sharper cutoff is not an essential requirement. Fig. 7 illustrates an example of a 5 element LPF design. Here, we chose H Z = 120 , L Z = 20 , and 0 R = 50 . As well, we selected a cutoff frequency of 4 GHz and 7 dB insertion loss at 4.4 GHz. The calculated values using (1) and (2) are given in Table I.
Fig. 7. A 5 element LPF design. TABLE I 5 ELEMENT LPF DESIGN FOR A 4 GHZ CUT-OFF FREQUENCY. Element Value Impedance () Electrical Length Length
(mm) Width
(mm) C 1 =0.618 Z L =20 14.163 0 l L1 =1.492 w L =11 L 2 =1.618 Z H =120 38.626 0 l H2 =4.657 w H= 0.4 C 3 =2.000 Z L =20 45.836 0 l L3 =4.828 w L= 11 L 4 =1.618 Z H =120 38.626 0 l H4 =4.657 w H= 0.4 C 5 =0.618 Z L =20 14.163 0 l L5 =1.492 w L= 11 C. Proposed High/Low-Z Configuration The proposed High/Low-Z configuration (Fig. 4) is based on the LPF design. However, unlike LPF, the proposed structure employs uniform lengths ( i l ) for all elements. This length may be selected to lie within the minimum and the maximum values calculated for the LPF design. For example, for the 5 element design given in Table I, the length for an element in the proposed configuration can be selected between 1.492 mm and 4.828 mm. Choosing a particular length uniformly for all elements will affect the cutoff frequency and the return loss of the filter. However, since we are assuming low-frequency or DC signals on the victim trace, cutoff frequency and return loss are not the primary concerns. Fixing the element lengths simplifies the LPF design procedure and makes it easier to implement it in EMC prototype testing (e.g. using copper tape). Furthermore, selecting a particular number of elements is arbitrary and affects the performance of the proposed configuration in terms of crosstalk. In our investigation, however, we have selected 3, 5, 7 and 9 elements for comparison with the LPF and guard trace configurations. The proposed configuration was also investigated by employing the guard traces (with and without via fences) between the traces. III. RESULTS AND DISCUSSIONS Both conventional and proposed PCB configurations were simulated using Ansoft HFSS to calculate the far-end crosstalk (S 41 ) over a frequency range from 0 to 6 GHz. Below, we present a comparison of the calculated results. First, the crosstalk between adjacent PCB traces (Fig. 1) using conventional guard trace (Fig. 2) and guard trace with vias (Fig. 3) was calculated. The results, plotted in Fig. 8, show that the guard trace alone does not provide any significant improvement in the crosstalk reduction. Similarly, using the guard trace with via fences shows a slight but insignificant improvement in crosstalk reduction. Frequency (GHz) 0 1 2 3 4 5 6 S 4 1
( d B ) -80 -70 -60 -50 -40 -30 -20 -10 0 Uniform adjacent parallel traces (Fig. 1) With guard traces (Fig. 2) With guard traces grounded by vias (Fig. 3)
Fig. 8. Comparison of far-end crosstalk in adjacent PCB traces using guard trace and guard trace grounded with vias. Frequency (GHz) 0 1 2 3 4 5 6 -80 -70 -60 -50 -40 -30 -20 -10 0 Uniform adjacent parallel traces (Fig. 1) 3 elements proposed design 5 elements proposed design 7 elements proposed design 9 elements proposed design S 4 1
( d B )
Fig. 9. Far-end crosstalk in PCB traces using the proposed configuration. Next the performance of the High/Low-Z configuration (Fig. 4) employing 3 mm long elements was investigated. As can be seen in Fig. 9, the proposed design provides significant reduction in crosstalk as compared to guard trace configuration (Fig. 8). Moreover, it can be observed that the crosstalk can be further reduced by increasing the number of elements in the proposed configuration. We compared the performance of the proposed scheme with the conventional LPF design. To this end, Fig. 10 provides a comparison between a 5 element LPF design and a 5 element proposed design. Results show relatively similar performance for both designs in terms of far-end crosstalk. Moreover, the return loss (S 33 ) levels are acceptable for the proposed configuration. A comparison of the near-end coupling, as plotted in Fig. 11, shows that the proposed configuration provides crosstalk improvement similar to the LPF. A 9 element High/Low-Z configuration along with the guard traces was also investigated. Fig. 12 shows that adding 762 Frequency (GHz) 0 1 2 3 4 5 6 S 4 1
&
S 3 3
( d B ) -80 -70 -60 -50 -40 -30 -20 -10 0 S41 for the Proposed design S41 for the LPF S33 for the proposed design S33 for the LPF
Fig. 10. Comparison of the proposed configuration with the LPF. Frequency (GHz) 0 1 2 3 4 5 6 S 3 1
( d B ) -80 -70 -60 -50 -40 -30 -20 -10 0 S31 of the 5 elements LPF (Fig. 4) S31 of the proposed 5 elements (Fig. 4)
Fig. 11. Comparison of the proposed configuration with the LPF for the near-end crosstalk. Frequency (GHz) 0 1 2 3 4 5 6 S 4 1
( d B ) -80 -70 -60 -50 -40 -30 -20 -10 0 9 elements Proposed design (Fig. 4) With guard traces (Fig. 5) With guard traces grounded by vias (Fig. 6)
Fig. 12. Proposed configuration combined with guard traces. guard trace with vias helps, in general, reducing the crosstalk. However, employing guard traces without ground vias, in fact, increases the S41 coupling. Finally, 5-element High/Low-Z configurations with different element lengths were compared. The results, as plotted in Fig. 13, show that increasing the Frequency (GHz) 0 1 2 3 4 5 6 S 4 1
( d B ) -80 -70 -60 -50 -40 -30 -20 -10 0 li =1 mm li =2 mm li =3 mm li =4 mm li =5 mm
Fig. 13. Proposed configuration with different element lengths.
element length shifts the resonances towards the lower frequency values. IV. CONCLUSIONS A new High/Low-Z configuration employing uniform elements was investigated for reduced far-end crosstalk in adjacent PCB traces. The performance of the proposed design was found similar to the LPF design. However, unlike LPF, the proposed approach is easier to implement in the EMC prototype testing. The study shows that employing stand-alone guard traces with ground vias along with the proposed configuration helps reduce the far-end crosstalk. REFERENCES [1] K. Hu, H. Weng, D. Beetner, D. Pommerenke, J. Drewniak, K. Lavery, and J. Whiles, Application of chip-level EMC in automotive product design, IEEE EMC Int. Symp., Portland, OR., Aug. 2006, vol. 3, pp. 842-848. [2] K. Lee, H.-B. Lee, H.-K. Jung, J.-Y. Sim, and H.-J. Park A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines, IEEE Trans. Advanced Packaging, vol. 31, no. 4, pp. 809-817, Nov. 2008. [3] B. Eged, F. Mernyei, I. Novak, and P. Bajor, Reduction of far-end crosstalk on coupled microstrip PCB interconnects, Proc. IEEE Instrumentation and Measurement Tech., Hamamatsu, Japan, May 1994, vol. 1, pp. 287-290. [4] S.W. Park, F. Xiao, D.C. Park, and Y. Kami Crosstalk analysis for two bent lines using circuit model, IEICE Trans. Communications, vol. E90, no. 2, pp. 323-330, Feb. 2007. [5] A. Suntives, A. Khajooeizadeh, and R. Abhari, Using via fences for crosstalk reduction in PCB circuits, IEEE EMC-S Int. Symp., Portland, OR., Aug. 2006, vol. 1, pp. 34-37. [6] L. Zhi, W. Qiang, and S. Changsheng, Application of guard traces with vias in the RF PCB layout, Proc. 3 rd Int. Symp. Electromagnetic Compatibility, Beijing, China, May 21-24, 2002, pp. 771-774. [7] D. Brooks, Signal Integrity Issues and Printed Circuit Board Design, Upper Saddle River, New Jersey: Prentice Hall, 2003. [8] A. R. Djordjevic, T. K. Sarkar, and R. F. Harrington, Time-Domain Response of Multiconductor Transmission Lines, proc. IEEE, vol. 75, pp. 743-764, June 1987. [9] D. Pozar, Microwave Engineering, 3 rd ed. New York: Wiley, 2005, pp. 412-416. [10] G. Matthaei, L. Young, and E.M. Jones, Microwave Filters Impedance- Matching Networks, and Coupling Structures, Artech House, 1980s. 763