A l I d El i AnalogIntegratedElectronics

EE 4223
Textbook:
1. P. R. Gray, P. J . Hurst, S. H. Lewis, R. G. Meyer, "Analysis y, , , y , y
and Design of AnalogIntegrated Circuits," 4th Edition,
WILEY.
2. Sergio Franco, Design with Operational Amplifiers and
Integrated Circuits, 2nd edition McGraw Hill.
Reference Books:
D. J ohns & K. Martin,Analog Integrated Circuit Design, J ohn
Wiley & Sons.
Course outline Courseoutline
Review of BJTs and MOS models
Current mirrors and active loading Current mirrors and active loading
Op-amp stages and design:
Feed back and frequency response Feed back and frequency response
Stability compensation and slew rate of op-amp
Op-amp as an amplifier
Non-linear Circuits
Monolithic Timers:
Active and switched capacitor filters:
Phase Locked Loop (PLL)
Grading Policy GradingPolicy
Assignments: 15 % Assignments: 15%
MidtermExams/Tests: 45%
i l 0 % Final: 40%
Total: 100%
Theremaybeminorchangeinthegrading
policy. p y
Important Notes ImportantNotes
Tutorials may be arranged to compensate for any deficiency.
No any excuse will be accepted for any absence from the
class/test/quiz or late submission of homework/assignments.
Maximum absentees allowed in the course are six. No
correction form will be entertained. correction form will be entertained.
You are expected to bring your text book/notes to class every
ti time.
Important Notes ImportantNotes
You are expected to read the appropriate sections of
the text to gain a fuller understanding of the the text to gain a fuller understanding of the
material.
Assignments,noticesoranyotherinformationwillbe
announced in the class or will be put in Juweb announcedintheclassorwillbeputinJuweb
Jinnah/MRiaz/AnalogICs.Youmustcheckit
periodically.
Turnoffallelectroniccommunicationdeviceswhen
youentertheclassroom.
Academicintegrity/honestyisexpected
ofstudents
IfIsuspectyouofcheatingduringaquiz/test
nocreditwillbeawardedtoyouandthecase y
maybereportedtohigherauthorities.
Student should be honest in all their academic Studentshouldbehonestinalltheiracademic
workandfailuretocomplywiththis
commitment will result in disciplinary action commitmentwillresultindisciplinaryaction.
Semiconductor Review SemiconductorReview
PN Junction P NJunction
P N
-W
1
W
2 FromPoissonsEquation:
P ++N
++
2
2
A
qN d V
dx

= =
1
0 W x
Chargedensity
x
0 E t W
1
A
qN dV
x C
dx
= +
Efield
( )
1
A
qN dV
E x W
dx
= = +
1
0, E at x W = =
x
dx
1
0, V at x W = =
2 2
N W
Potential
2 2
1
1
2 2
A
qN W x
V W x

= + +


2
N W
x
2
1
1
2
A
qN W
V

= 0 at x =
Depletionwidths
2
1
1
2
A
qN W
V

=
p
Fromconservationofcharge
(17) W N W N =
( )
1
A
x
qN dV
E x W
dx
= =
2
similarly for 0<x<W
1 2
(1.7)
A D
W N W N =
2 2
2
2
0
2
W
D
x
qN W
V E dx

= =

2
0 x W
dx
( )
2 2
0 1 2 1 2
(1.6)
2
R A D
q
V V V N W N W

+ = + = +
Solving 1.6 and 1.7.
( )
1
2
0
2
R
V
W



+

=

( )
1
2
0
2
R
V
W



+

=

Solving1.6and1.7.
1
1
A
A
D
W
N
qN
N
=


+




2
1
D
D
A
W
N
qN
N

=


+




JunctionCapacitance p
1
j
dW dQ dQ
C = =
A
P
N
1
j
R R
dV dW dV
1 A
dQ AqN dW =
1
dW
x
1
2
1
2



1 A
dQ AqN dW
1
dW
x
Depletion
region
( )
( )
2
1
0
1
0
2 1
V
R
N
A
qN R R
A
A
N
D A R
dW d
dV dV
N
qN V
N

+





+




= =


+ +




( )
D
N



( )
1
2
1
A D
j
q N N
C


=


( )
0
2
j
A D
R
N N
V

+
+


JunctionCapacitance
1
2
1
A D
q N N


( )
0
0
1
2
1
A D
j
A D
D
q N N
C
N N
V

=

+



( )
1
2
0
2
A D
j
A D
q N N
C
N N

=

+


( )
0
0
1
j
j
D
C
C
V

=

0
1

GradedJunction
C it
ax =
Capacitance
x
0
3
1
j
j
D
C
C
V
=

3
0
1

MinorityCarriersconcentrations
of PNjunction
PN-Junction under
Bi
Depletion region
ofPNjunction
no Bias
Depletionregion
p
n
n
p
x=-W
1
x
n
=0
x=W
2
x
p
=0
0 p
x
n
x
: equilibrium concentration of electronsin P-region
p
n
: equilibrium concentration of holes in N-region
n
p
PNJunction
PN-Junction under
Reversed Biased
( )
p
n x
( )
n
p x
Depletionregion
Reversed Biased
n
p
R
V V =
p
n
x=-W
1
0
x=W
2
0
0
p
x
n
x
( )
1
R T
V V
p p p
n n e n

=
p p
x
n
=0 x
p
=0 n n
p p
( )
1
R T
V V
I I e I

( )
0 0
1
R T
I I e I =
1
( )
p
p W p =
( )
Minority Carriers Concentration
PN Junction Forward Biased
q
n
p
2
( )
n
p W p =
1
0 at
p
x x W = =
0at x x W = =
n p
PN Junction Forward Biased
T
q
V
kT
=
( )
p n
x L
p p
n x n e

=
( )
n p
x L
n n
p x p e

=
p
n
n
p
2
0 at
n
x x W = =
( ) Excess carriers N side =
x=-W
1
x
p
=0
x=W
2
x
n
=0
0
p
x
n
x p
L
Depletionregion
n
L
0
T
V V
p
V
n
p
n
e
p n

= = ( ) Excess carriers P side =

( )
0
( ) 1
T
V V
n n n n
p p x p p e = =
Theequilibrium
concentrationof
holesandelectrons
( V is biasing Voltage)
n p
p n
( )
0
( ) 1
T
V V
p p p p
n n x n n e = =
(V isbiasingVoltage)
oneithersideis
( )
0
1
T
V V
I I e =
( )
( ) 1
p n
T
x L
V V
p p
n x n e e

=
( )
0
( )
( )
( ) 1
n p
T
x L
V V
n n
p x p e e

=
Junction Forward Biased Static Diffusion Capacitance
ThediffusioncapacitanceC
D
istherateofchangeofinjectedchargew.r.t.
voltage.Largechargeispresentacrossthejunctionduetoforwardbiased.
dQ dI
StaticdiffusionCapacitance
DynamicdiffusionCapacitance
D
dQ dI
C g
dV dV r

= = = =
( )
0
1
T
V V
I I e =
2
n
D
C

=
g
AtLowfrequency
( )
0
D
T
I
C
V

=
2
g =Lowfreqconductance
At high frequency
D
C I
1
2
n
C


=

g
Athighfrequency
M lif i f i
2
D
C

=


o
g
Mean life time of carriers =
Junction Forward Biased Static Diffusion Capacitance
For transistors, the diffusion capacitance C
D
is measured from unity current
gain frequency f
T
as g q yf
T
C
m
g
2
D
T
C
f

m
g
Junction breakdown
I
( )
1
2
max
2
A D R
A D
qN N V
E
N N

=

+


( )

At a critical field (3x10
5
V/cm) the carriers
traversing the depletion region acquire sufficient
energy to create new holeelectron pairs in
V
gy p
collisions with silicon atoms. This is called
avalanche process. The newly created carriers
are also capable of producing avalanche.
RA R
I MI =
Zener breakdown occurs only in
1
1
n
R
M
V
=

Zenerbreakdownoccursonlyin
veryheavilydopedjunctionwhere
theelectricfieldbecomeslarge
enoughtostriptheelectronsaway
1
R
V
BV

fromvalenceband.Thisiscalled
tunneling.
Concentration Profile n-p-n Transistor
(Active region) ( g )
A A
x
=
0
x
=
W
B
CB
V
n p n
C C
A A
BE
V
CE
V
(0)
BE
T
V
V
n n e
B
n
nC p (0)
Depletion
Carrier Concentration
0
(0)
T
p p
n n e =
n
nC
p
C
n
nE
p
p
(x)
p
p
(0)
n
p
(0)
Region
Depletion Region
N
A
N
D
BE T
n po
V V
C
qAD n
I e =
Base Collector Emitter
x
x=0 x=W
B
p
nC
p
nE
n
p
(x)
A A
BE T
C
B A
V V
C S
I e
W N
I I e =
n po
S
B A
qAD n
I
W N
=
1
BE T
B po p
V V
i
B
qAW n qAD
n
I e

= +


2
B
b p D
C
B
L N
I
I

=
F

2
1
1
n po
B
F
qAD n
W
AW AD D
W W N
= =
2
1
2 2
F
B po p i p
B B A
b p D b n n p D
qAW n qAD n D
W W N
L N D D L N
+ +
( )
1
C F
I +
( )
1
C F
E C B C
F F
I
I I I I

+
= + = =
1 1 1
F
+
2
1 1 1
1
1
1
2
F
F
p
F B B A
F
b n n p D
D
W W N
D D L N

+
= = =
+
+ +
If F i l th
1
IfFisverylarge,than
Where
F T

2
1
1
2
T
B
b n
W
D

=
+
1
1
p
B A
D
W N
D L N
=
+
n p D
D L N
NPN Transistors Large Signal Model
I I
B C B C
BE
V
( ) BE on
V
F B
I
F B
I
B
I
B
I
E
E
BE
V
( ) BE on
F B
I
F B
I
V V
S
I
BE T
V V
S
B
F
I
I e

=
PNP Transistors Large Signal Model
B C B C
B
I
B
I
BE
V
( ) BE on
V
F B
I
F B
I
E
E
BE T
V V
S
B
F
I
I e

=
F

I
Output Characteristics of CE Amplifier
C
I
4 BE
V
5 BE
V
E t l t d
2 BE
V
3 BE
V
Extrapolated
xtics
Earlyvoltage
0
CE
V
A
V
1 BE
V
y g
1
B E T
V V
C E
C S
A
V
I I e
V

= +


Thedecreaseineffectivebase
width with increase in collector widthwithincreaseincollector
reversevoltageiscalledearly
effectofbasewidthmodulation.
Asaresult,therecombinationin
thebasedecreasesand and
henceI
C
=I
B
increases.
NPN transistor in saturation region
( ) C sat
I
B
I
B
C
( ) CE t
V
( ) BE on
V
E
( ) CE sat
V
( ) BE on
E
Common Base Configuration
C
I
E
I
CB
V
Common Emitter Configuration
Basic BJT Small Signal Model
i i i
c
i
b
B C
r
o
r
1 m
g v
b
C
1
v
i
v
+
Input Resistance Output Resistance Transconductance
Basecharging
b 1
E
i

0
i i
v v
r
i i

= =
C C
o
I I
r
V V

=

C
m
I
V

g
InputResistance OutputResistance Transconductance
g g
Capacitance
change in base charge
change in BE voltage
h
b
i
q
C
v
= =
0
b c
i
i
i i
v
r
v

=
m
g
1
1
CE CE
C C
CE A o
V V
I I
V V r
qV

= =

BE T
BE
V V
m S
BE
V
I e
V
I

g
e h C F
h c F
h c
Q Q I
q i
q i
C

= =
=
0
r

=
m
g
1
A
o
A
qV
r
kT
kT
qV

= =
=
m m
g g
C
m
T
C
m
I
V
qI
kT
=
=
g
g b F m
C = g
h c
b F F m
i i
q
C
v v
= = = g
A
qV kT

F
is the base transit time of the
carriers in the forward direction.
VerticalPNPBJT
LateralPNPBJT
Parasitic Elements in the Small-Signal Model
C B E
C
je
C
n
+
n
+
C
C

je
C
je
r
3 c
r
b
r
p
n
cs
C
cs
C

C
1 c
r
2 c
r
n
+
n
cs
C
p
Complete BJT Small Signal Model
B C
b
r
C

c
r
B C
r
1 m
v g
C
cs
C 1
v o
r
E
ex
r
E
m
r

=
g
1
o
m
r

=
g
A
kT
qV
=
1
CE
B
V
r
I

CollectorBaseResistance
m A
0
n
C
C
V

=

je b
C C C

= +
1
1
0
B
CE C
C B
I
V I
r
I I
r r

=

=
0
1
V

0 o
r r

Complete BJT Small Signal Model
B C
b
r
C

c
r
B C
r
1 m
v g
C
cs
C 1
v
E
ex
r
m
r

=
g
1
o
m
r

=
g
A
kT
qV
=
E
1
CE
B
V
r
I

CollectorBaseResistance
m A
0
n
C
C
V

=

je b
C C C

= +
1
1
0
B
CE C
C B
I
V I
r
I I
r r

=

=
0
1
V

0 o
r r

1 kT

C C C
C
qI
= g
m
r

=
g
o
m
r

=
g
A
qV
=
0
C
C

=
je b
C C C

= +
0 o
r r

=
m
kT
g
b F m
C = g
0
1
n
C
V

Complete Small Signal Model
20M
B C
300
5.6 fF 50
2.6k
1
0.038v
0.4 pF
10.5 fF
1
v 20k
5
E
Short Circuit unity gain frequency and forward current
transfer ratio (single Pole appoximation) ( g pp )
B C
b
r
C
c
r
r

1 m
v g
C

cs
C
1
v
E
B C
b
r
o
i
Neglecting r
c
1 o m
i v g
r

b
1 m
v g C

1
v
i
i
1 o m
( )
1
1
i
i
v
j C C
r

=
+ +
0
1
m
C C

=
+
g
E
r

( )
( )
1
1
i i
o m m
i i
i r
j r C C
j C C
r

=
+ +
+ +
g g
1
2
m
T
f
C C

=
+
g
r

( )
( )
1
1
o
m
i
i
j r
i
j r C C

= =
+ +
g
( )
( )
1
1
o
m
i
T
i
j r
i
j r C C

= = =
+
g
r g 1
2
( )
( )
0
1
1
m
r
j
s
j r C C

= =
+ +
+
g
( )
0 0
1
m
Half Power frequency
r C C
A r

= =
+
= = g
( )
2
10log j
m
T
g
Unity Gain frequency
C C

= =
+
60
0
20log
40
20dB/decade
0
20
20 dB/decade

0.1
T

T
0.01
T
TheMetalInsulatorSemiconductor
FET
62
AnenhancementtypenchannelMOSFET:(a)isometricviewofdeviceand
equilibriumbanddiagramalongchannel;(b)draincurrentvoltageoutput
characteristicsasafunctionofgatevoltage.
63
The gate capacitance per unit area is
ox
C

Thegatecapacitanceperunitareais
ox
ox
C
t
=
( )
1
2
2 V


+

( )
0
1
2
1
R
A
A
D
V
W
N
qN
N
+

=


+




0 GS T
V V
N N

2
D A
Si
N N
X
qN

=

0
A
R
qN
V = +
IdealizedNMOSdevicecrosssectionwithpositivevoltageappliedshowing
depletionregionsandtheinducedchannel.
64
MOSFET Threshold Voltage
ln
A
N q
=
2
ln
g
f
i
E
kT
f i c v
kT n
n N N e

=
=
MOS threshold voltage (sufficient
large V
GS
for strong inversion):
1 gate substrate work
0
2
2
A A Si
b A Si f
Q qN X qN
Q qN


= =
=
1.
ms
gatesubstrate work
function difference;
2. Q
ss
oxide and interface
charge;
3 Q surface potential and
( )
2
2
b A Si f SB
b ss
T ms f
Q qN V
Q Q
V
C C


= +
= + +
3. Q
b
surface potential and
induced depletion
layer charge offset;
4.
f
Fermi potential
5 constant
0 0
2
ms f
ox ox
b ss b b
ms f
ox ox ox
C C
Q Q Q Q
C C C


= + + +
5. constant
6. V
SB
substrate-bias
( )
0
2 2
2
t f SB f
Si A
V V
q N

= + +
=
ox
C

65
MOS Substrate Bias Effect Example Plot - 2
Note HJS Example 2.5 (pp. 5152).
For the example we have been working, plot V
T
versus V
SB
.
[Calculate V
T0
at V
SB
= 0 V for a polysilicon gate NMOS transistor with the following
parameters: N
A
(substrate) = 1 x 10
16
cm
-3
; N
D
(gate) = 2 x 10
20
cm
-3
; t
ox
= 500 , oxide-
interface fixed charge density N = 4 x 10
10
cm
-2
Answer = 0 40 V (see above) ] interface fixed charge density N
ox
= 4 x 10
10
cm
2
. Answer = 0.40 V (see above).]
66
MOSFET Operation
67
NMOS FET Regions of Operation
V
GS
> V
T0
shifts E
i
below E
f
,
making
s
positive and
inverting the surface.
Linear region
V
DS
> 0 I
DS
(drift current)
High field
V
D sat
Source-drainsubstrate
Saturation region
High field
V
D,sat
Source drain substrate
junction never forward-biased.
Saturation region
68
NMOS FET Gradual Channel Approximation
V
GS
> V
T0
shifts E
i
below E
f
, making V
GS
> V
T0
shifts E
i
below E
f
, making

s
positive and inverting the surface.
V
DS
> 0 I
DS
(drift current).
V
DS
wider depletion region at
drain, but we assume that the
difference is small.
G d l h l i i (1D I V)
Source-drainsubstrate
junction never forward-biased.
Gradual channel approximation (1D I-V):
V
T0
is constant from y = 0 to y = L
E
y
>> E
x y x
V
GD
= V
GS
V
DS
V
T0
69
NMOS FET Gradual Channel Approximation
( ) ( )
n ox GS T
Q y C V V y V =

; V
channel-to-source
= V(y); 0 V(y) V
DS
; V
GC
= V
GS
V(y)
( )
( )
( )
DS n
y
I xWJ xW v x vW Q y vW
dV y
v E
d


= = = =
= =
; charge/unit area (yz) x carrier velocity x channel width
; carrier velocity = mobility (cm
2
V
-1
s
-1
) x electric field
( )
y
DS ox GS T y
dy
I C V V y V W E =

; drain current in long channel approximation
; carrier velocity = mobility (cm
2
V
1
s
1
) x electric field
70
NMOS FET Linear Region, First Order
( )
DS ox GS T y
I C V V y V W E =

Only V(y) on the rhs depends on y
( )
( )
( )
DS
DS ox GS T y
DS ox GS T
L V
y
I dy W C V V y V dV

=


Note boundary conditions:
( )
( )
0 0
2
DS
DS ox
DS
GS T
I dy
V W
I C V V V
W V C V V dV

=

=

Note boundary conditions:
V(y=0) = 0; V(y=L) = V
DS
Drain current: linear region;
gradual, long-channel approximation
( )
2
DS ox GS T DS
I C V V V
L
=


g , g pp
71
NMOS FET Linear Region, First Order
( )
2
DS
DS ox GS T DS
V W
I C V V V

=

( )
2
'
DS ox GS T DS
ox
L
k C
W

= =
Process transconductance parameter (A/V
2
)
( )
2
'
W
k k
L
k
=

Device transconductance parameter
( )
2
2
2
DS GS T DS DS
k
I V V V V

=

Drain current: linear region;
gradual, long-channel approximation
72
NMOS FET Saturation Region, First Order
What happens as V
DS
is
increased?
Drain current saturates
and "rolls over" with
increasing drain voltage.
Th I d V Thus, I
D,sat
and V
D,sat
.
( ) [ ]
2
2
2
DS DS T GS DS
V V V V
k
I =
( )
2
, T GS sat D
V V
k
I
V V V
=
=
( )
,
2
T GS sat DS
V V I =
73
NMOS FET Saturation Region, First Order
pinchoff (no inversion layer) when V
DS
V
GS
V
T0
( )
2
,
2
DS sat GS T
k
I V V =
( )
,
2
DS sat GS T
k
I V V =
( ) ( ) [ ]
T GS ox n
V y V V C y Q =
[V
channel-to-source
= V(y); 0 V(y) V
DS
; V
GC
= V
GS
V(y)]
74
NMOS FET I-V
I
DS
versus V
DS
I
DS
versus V
GS
( ) [ ]
DS DS T GS DS
V V V V
k
I = 2
2
2
( )
T GS sat DS
V V
k
I =
2
2
2
,
; (I
ds
)
0.5
versus V
DS
is linear
; slope = k/2, x-intercept = V
T
; V
T
(V
SB
)
( )
T GS sat DS
V V
k
I =
2
,
; V
T
(V
SB
)
75
NMOS FET Channel Length Modulation
I
D,sat
is in fact dependent on V
DS
:
1. Depletion region shortens
( ) V V
k
I
2
effective channel length;
2. Channel charge density
increases.
( )
( ) ( )
DS T GS sat DS
T GS sat DS
V V V
k
I
V V I
+ =
=
1
2
2
2
,
( ) ( )
DS T GS sat DS
V V V
2
,
; lambda channel length modulation parameter
(empirical approximation); units are V
-1
76
NMOS FET Channel Length Modulation
I
DS
versus V
DS
[ ]
k
( ) [ ]
( ) ( )
DS DS T GS DS
V V V
k
I
V V V V
k
I
+
=
1
2
2
2
2
( ) ( )
DS T GS sat DS
V V V I + = 1
2
,
77
Shortchannel Device Short channelDevice
The vertical and horizontal field are large they Theverticalandhorizontalfieldarelargethey
interactwithoneanother.
The pinch off occurs (when carriers reaches Thepinchoffoccurs(whencarriersreaches
velocitysaturation)earlythanpredictedby
the first order model thefirstordermodel.

78
Effect of high field Effectofhighfield
The horizontal field is E
y
=V
DS
/L. ThehorizontalfieldisE
y
V
DS
/L.
Thehorizontalfieldwas10
5
V/cmupto1995.
The horizontal field pushes the carriers to Thehorizontalfieldpushesthecarriersto
theirvelocitylimitandmobilityofcarriers
decreases. decreases.
Theverticalfieldcanbeapproximatedas
E
x
=V
DD
/t
ox
. E
x
V
DD
/t
ox
.
E
x
producesmorecarriersatoxideinterface,
where the mobility is reduced. wherethemobilityisreduced.
79
1980 1995 2001 1980 1995 2001
4
5
/
V 4
3.3
94 10 /
V
E V
5
1.2
12 10 /
V
E V
4
5
10 /
5
y
V
E V cm
m
= =
4
9.4 10 /
0.35
y
E V cm
m
= =
5
1.2 10 /
0.1
y
E V cm
m
= =
4
5
50 10 /
1000
x o
V
E V cm
A
= =
6
3.3
4.4 10 /
x o
V
E V cm = =
6
1.2
5.5 10 /
22
x o
V
E V cm
A
= =
1000A
75A
22A
80
A first order for mobility is

0
Afirstorderformobilityis

+
=
ox
T GS
e
t
V V
1
0

0
isnominalmobilityforlongchannel.
and are empirical values and areempiricalvalues.
thehorizontalfieldactstoreducethemobilityevenfurther.
7
10 /
sat
v V cm =
81
Short-Channel Devices (< 1 m) --- A New Regime
Gradual channel approximation: Gradual channel approximation:
V
T0
is constant from y = 0 to y = L
E
y
>> E
x
V
GD
= V
GS
V
DS
V
T0
None of these are valid for deep None of these are valid for deep
submicron devices.
E
x
is larger relative to E
y
, and E
y
approaches 10 MV/m, the limit of
linear electron drift. linear electron drift.
Saturation occurs before pinchoff.
High fields velocity saturation.
L
Channel Electric Fields
L
eff
x
j
Channel Electric Fields
1980 1995 2005
E
y
5.0 V / 5.0 m 3.3 V / 0.35 m 1.0 V / 0.07 m
1 MV/m 10 MV/m 14 MV/m
E
x
5.0 V / 100 nm 3.3 V / 75 nm 1.0 V / 1.7 nm
50 MV/m 440 MV/m 590 MV/m
V
GD
= V
GS
V
DS
V
T0
E
x
produces more carriers at oxide interface, where the
mobility is reduced.
E
y
, exceeds E
critical
where velocity saturates.
82
Carrier Velocity Saturation
Mobility reduction at high vertical field (E
x
)
results from interface effects results from interface effects.

+
=
T GS
e
V V
1
0

+
ox
t
1
Mobility reduction at high lateral field (E
y
)
results from velocity saturation, which we can esu ts o e oc ty satu at o , c e ca
represent in a piecewise linear function of E
y
.
C y
y
y
e
E E
E
E
v <

=
1

C y sat
C
y
E E v v
E
=

+

1
C y sat
sat C e C
v
E
E E 2
so
Note, for continuity at velocity saturation boundary:
e
sat
C
C e
C
C
C
e sat
E
E
E
v v

so ,
2
1
= =

+
= =
83
NMOS FET Linear Region, Short Channel
h l idth h / it ( ) i l it
DS n
I WQ v =
; channel width x charge/unit area (yz) x carrier velocity
( ) ( )
1
e y
DS ox GS T
y
E
I WC V V V y
E

=


( )
1
y
C
E
dV y
E

+

=
y
E
dy
( ) ( ) ( )
DS
I
I dy W C V V V y dV y

=

( ) ( ) ( )
( ) ( ) ( )
DS
DS e ox GS T
e C
L V
DS
DS GS T
I dy W C V V V y dV y
W E
I
I dy W C V V V y dV y

=



=


84
( ) ( ) ( )
0 0
DS e ox GS T
e C
I dy W C V V V y dV y
W E

NMOS FET Linear Region, Short Channel
( ) ( ) ( )
DS
L V
DS
DS GS T
I
I dy W C V V V y dV y

=


( ) ( ) ( )
( )
0
2
0
2
e ox
DS GS T DS DS
DS e ox GS T
e C
C W
I V V V V
I dy W C V V V y dV y
W E

=





; drain current in linear region with velocity saturation
( )
2 1
DS GS T DS DS
DS
C
L
V
E L


+


85
I WQ
NMOS FET Saturation Region, Short Channel
( )
DS n sat
DS ox GS T DS sat
I WQ v
I WC V V V v
=
=
( )
( )
, , DS linear DS sat
GS T c
D sat
I I
V V E L
V
V V E L
=

=
( )
E L
( )
( )
( )
,
2
D sat
GS T c
GS T
DS t
V V E L
V V
I Wv C
+

=
( )
( )
( )
,
1
c
D sat GS T
GS T c
c
E L
V V V
V V E L
E L
V V E L
=
+
<
+
( )
DS sat ox
GS T c
I Wv C
V V E L +
; drain current in saturation region with velocity saturation
( )
GS T c
Dsat
V V E L
The value of V will be lower
than the 1st order model.
+
Long channel device long channel behavior
( )
T GS C
V V L E >>
Very short channel device linear, not quadratic
( )
T GS C
V V L E <<
( )
2
2
T GS ox e DS
V V C
L
W
I =
( )
( )
T GS ox sat DS
T GS C
V V C Wv I =
86
0 18 m NMOS PMOS Saturation Voltages 0.18 m NMOS, PMOS Saturation Voltages
Low-Field Mobility
NMOS PMOS Units
400 85 cm
2
V
1
s
1
400 85 cm
2
V
-1
s
-1
87
HJS Example 2 7 Compute the saturation currents per micron of width for a 0 13 m
0.13 m NMOS, PMOS Saturation Currents
HJS Example 2.7 Compute the saturation currents per micron of width for a 0.13 m
technology. Assume a channel length of 100 nm, t
ox
= 22 , V
TN
= 0.4 V, V
TP
= -0.4 V,
V
DD
= 1.2 V, v
sat
= 8 x 10
6
cm/s.
1 5 1 4
( )
( )
2
1 5 1 4
4 . 2 10 4 . 2 60 . 0 10 0 . 6

=
= =
V V
C v
I
V cm V E V cm V E
T GS
ox sat
DS
CP CN
( )
[ ] ( )( )
( )
( )
2
2 6 1 1 6
6 0 40 0 2 1
40 . 0 2 . 1
10 6 . 1 10 0 . 8


=
+
V V V
V V
cm F s cm NMOS
L E V V W
C T GS
ox sat
[ ] ( )( )
( )
( )
2
1
590
6 . 0 40 . 0 2 . 1

=
+
m A
V V V

[ ] ( )( )
( )
( )
1
2
2 6 1 1 6
260
4 . 2 40 . 0 2 . 1
40 . 0 2 . 1
10 6 . 1 10 0 . 8

+

=
A
V V V
V V
cm F s cm PMOS
1
260 = m A
88
NMOS FET Subthreshold Region
( )

( )
1

=

e e I I
T k
qV
T nk
V V V q
s sub
B
DS
B
offset T GS
( ) 10 ln = =
q
T nk
V S
B
GS
; slope factor, mV/decade
89
d) Th d t f h i th t d i b f NMOS d f PMOS d) The advantage of having the gate doping be n+ for NMOS and p+ for PMOS
could be seen from analysis above. Doping the gates in such a way leads to
devices with lower threshold voltages, but enables the implant adjustment with
the same kind of impurities that used in the bulk (ptype for NMOS and ntype for p (p yp yp
PMOS). If we were to use the same kind of doping in gate as in the body (i.e. n+
for PMOS and p+ for NMOS) that would lead to higher unimplanted threshold
voltages. Adjusting them to the required lower threshold voltage would
necessitate implantation of the impurities of the opposite type near the oxide Si necessitate implantation of the impurities of the opposite type near the oxideSi
interface. This is not desirable. Also, the doping of the poly gate can be carried out
at the same time as the source and drain and therefore does not require an extra
step.
90

=
0

+
=
ox
T GS
e
t
V V
1
91
MOS Capacitance
Capacitance a critical circuit component for speed, power dissipation, and size. Capacitance a critical circuit component for speed, power dissipation, and size.
For digital designs, almost all capacitances are parasitic, and each individual
element is small femtofarads or attofarads. Interconnect capacitances tend to be
voltage-independent. MOS capacitances are voltage-dependent (and non-linear).
Thin-oxide capacitances C
g
(C
gs
, C
gd
, C
gb
)
Gate overlap capacitances C
ol
Junction capacitances C
j
(C
sb
, C
db
)
Depletion layer
capacitance C
jc
92
MOS Capacitance
Junction capacitance
Gate-channel capacitance
Gate overlap capacitance
93
MOS C-V Measurement Gate Oxide
r
A
L W C C
0

= =
C
G
C
G
Accumulation Accumulation
ox
ox g
t
L W C C = =
Inversion
Low frequency
High frequency
Deep depletion
V
G
n-Si
V
G
p-Si n Si p Si
C-V instrumentation sweeps a DC bias (V ) at low (< 100 Hz "quasi-static") or high (>100 Hz) C-V instrumentation sweeps a DC bias (V
G
) at low (< 100 Hz, quasi-static ) or high (>100 Hz)
frequencies with a superimposed small AC signal (< 100mV, 0.110 MHz).
94
MOS C-V Measurement Gate Oxide
C
G
Low frequency
C
ox
C
ox
C
s
/ (C
ox
+C
s
)
V
G
High frequency
V
p-Si
V
T
95
DiffusionCapacitance iffusion Capacitance
Channel-stop implant
Nocapacitance
forconducting
id
( ) ( )
j j high j low
eq jo
D high low
Q Q V Q V
Ceq K C
V V V

= = =

A
N
+
Side wall
Source
W
side
A
Bottom
N
D
W
Side wall
Channel
Substrate N
A
x
j
L
D
o R
jo
j
V
C
C
/ 1+
=
Capacitanceis
function of A
( )
( )
1
1
0
0 0
( )
(1 )
m
m
m
eq high low
K V V
V V m

=


functionof
voltage
( )
( )
(1 )
high low
V V m



96
DynamicBehaviorofMOSTransistor
G
;
GS GCS GSO GD GCD GDO
C C C C C C = + = +
G
;
; ;
GS GCS GSO GD GCD GDO
GB GCB SB Sdiff DB Ddiff
C C C C C C = = =
D
S
C
GD
C
GS
C
SB
C
DB
C
GB
B
SB
97
Capacitance Capacitance
98
MOS Gate Capacitance In Operating Regions
Cutoff (accumulation) surface not inverted no conductive Cutoff
L W C C
C C
gd gs
= = 0
Cutoff (accumulation), surface not inverted, no conductive
connection from channel surface to source and drain.
Cutoff
L W C C
ox gb
=
Linear region, conducting inversion layer shields substrate
0
L W C
C
gb
=
from gate charge; source and drain "share" the distributed
oxide capacitance.
Linear
2
L W C
C C
ox
gd gs


0 C C
gb gd
= =
Saturation region, inversion layer does not extend to
drain, which is pinched off. As an approximation...
Saturation
3
2 L W C
C
ox
gs
gb gd

99
MOS Gate Capacitance In Operating Regions
Worst case (from C
gc,sat
= 0.66 C
ox
WL and C
gc,linear
= C
gc,cutoff
= C
ox
WL) will be
gc gb gs gd bott sw
C C C C C C = + + = +
( )
gc gb gs gd bott sw
j jsw ox D
C Area C Perimeter C W L 2L = + = +
100
MOS Capacitor in Accumulation
V
G
<0
M O S
p-Si
Consider p-type Si
under accumulation.
G
Accumulation of holes
V
G
< 0.
Looks similar to parallel
l i
x
plate capacitor.
C
G
= C
ox
x
G ox
where C
ox
= (
ox
A) / x
ox
Thus, for all accumulation conditions, the gate capacitance is equal
theoxidecapacitance the oxide capacitance.
101
MOS Capacitor in Depletion
Depletion condition:
V
G
> 0
V
G
>0
M O S
p-type Si
C
G
is C
ox
in series
with C
s
where C
s
can
V
G
>0
W Q
M
s s
be defined as
semiconductor
capacitance
Depletion of
holes
C
o
C
s
capacitance
C
ox
=
ox
A / x
ox
C = A / W
2
Si
W

=
x
C
s
=
Si
A / W
C
G
= C
ox
C
s
/(C
ox
+ C
S
)
s
A
W
qN

where
s
is surface potential
In this case, the gate capacitance decreases as the gate voltage is
increased. Why?
102
V V dV >V
MOS Capacitor in Inversion
M O S
p-Si
V
G
= V
T
and V
G
> V
T
Inversion condition
s
= 2
F
V
G
>>0 2 1
F
A
Si
T
2
2
/
qN
W W

= =
Depletion of
h l
W Q
M
At high frequency, inversion
electrons are not able to respond
toacvoltage So tobalancethe holes
Inversion electrons
- function
to ac voltage. So, to balance the
charge on the metal, the depletion
layer width will vary with the ac.
C
o
x
C
s
C
ox
=
ox
A/x
ox
C
s
=
Si
A/W
T
C
G
( ) = C
ox
C
s
/ (C
ox
+ C
S
)
So, C
G
will be constant for V
G
V
T
103
Example n
Consider n-type silicon doped with N
A
=10
16
cm
3
The oxide Consider n type silicon doped with N
A
10 cm . The oxide
thickness is 100 nm. Plot the C
G
vs. V
G
characteristics when V
G
is
varied slowly from 5 V to +5 V. Assume MOS has area of 1 cm
2
,

f
= 0.357 V.
f
Find C
ox
.
Find C (min) when x x (Note that C decreases as the
F 10 47 . 3 cm 1
cm 10 1000
F/cm 10 9 . 8 9 . 3
8 2
8
14

=
ox
C
Find C
s
(min) when x
d
= x
d,T
. (Note that C
s
decreases as the
depletion layer width increases. It is minimum when the depletion
layer width is maximum, i.e. when x
d
= x
d,T
).
2 / 1
14

m 298 . 0 357 . 0 2
cm 10 C 10 6 . 1
F/cm 10 85 . 8 9 . 11 2
3 16 19
14
,
=

V x
threshold d
F/cm 10
12
F 10 35 . 3 cm 1
cm 10 298 . 0
F/cm 10
(min)
8 2
4
s

= C
C
G
(min) = (3.47 10
8
3.35) / (3.47+3.35) F = 1.7 10
8
F
C
G
= C
s
in series with C
ox
.
104
2 1
2

/
N
Example n, continued
F s s
Si
A
ox
Si
ox s T G
2 when
2
=

+ = =
qN
x V V
=215V 2.15 V
Plot the C-V characteristics
34.7 nF
C
G
34.7nF
l f low-f
Explain why C
G
does not
vary for V
G
> V
T
.
17nF
high-f
Question: How will you calculate
C when V 1V?
V
G
p type
2.17 V
C
G
when V
G
= 1V?
Answer: Calculate
s
when V
G
=
1 V using the equation above.
From find W then calculate
p-type
From
s
find W, then calculate
C
s
. Then, calculate
C
G
= (C
ox
C
s
) / (C
ox
+ C
s
)
105
MOS Junction Capacitance
MOSFET layout cross section MOSFET layout, cross-section,
and three-dimensional view
mjsw
sw jsw
mj
b jb
J
A C A C
C

+

=
mjsw
Bsw
J
mj
Bb
J
J
C C
V V

1 1
( )
mj
sw b jb
J
jsw jb
V
A A C
C
C C

+
=

B
J
V

1
106
MOS Junction Capacitance
MOSFET layout cross section MOSFET layout, cross-section
( ) ( )
2 1
2 1
j j
eq
Q V Q V
Q
C
V V V

= =

( )
2 2
1 1
1
m
V V
jb
V V
B
V
Q C V dV C dV

= =



( )( )
1 1
2 1
2 1
1 1
1
m m
jb B eq
eq
B B
C A
V V
C
V V m

=





( ) ( )
12
12 12
1
2
2
eq
B
m
C
K V V

( ) ( )
( ) ( )
2 1
2 1
q
B
eq B B
jb
J eq jb jb j eq jb j
K V V
C V V
C K C WY C Wx K C Y x W


= =

= + = +
107
MOS Gate Overlap Capacitance
C C C = +
_ _ _ _ _ _
ol ov f
overlap gate bottom over diffusion gate sidewall to diffusion
C C C
C C C
C C L
= +
= +
Gate overlap capacitances
2
ln 1
ov ox D
poly
ox
f
C C L
T
C
t

=

= +

ox
t

108
Cutoff Linear Saturation
0
0 0
GS
C
1
2
ox
C WL
1
2
3
ox
C WL
0 0
0 0
GD
C
GB
C
ox
C WL
1
2
ox
C WL
GB
ox
109
k
Transconductanceg
m
( )
( )( )
2
2
1
DS GS T
D
GS T DS
k
I V V
I W
C V V V
=

= = + g
( )
( )( )
1
m ox GS T DS
GS
C V V V
V L
+

g
Bodytransconductanceg
mb
( )
0
2 2
2
t t f SB f
Si A
V V V
q N
C

= + +
=
( )( )
1
ox
t D
mb ox GS T DS
BS BS
C
V I W
C V V V
V L V


= = +

g
( )
( )
2 2
t
BS
f SB
V
V
V

+
( )
( )
2 2
ox D
D
mb
BS
f SB
C W L I
I
V
V

= =

+
g
TheSiliconWafer
Waferissinglecrystalline,lightlydopedmaterial. g y , g y p
Diameterofwaferisbetween4and12inches.
Thicknessatmost1mm.
Aptypedopedwaferisapproximately,210
21
imputies/m
3
.
Oftentheoppositetypeisgrownoverthesuffacebeforethe
wafers are handed to the processing company wafersarehandedtotheprocessingcompany.
128
ThewholeSiliconingot:
Siwafersslicedfromingot:
129
Siliconcrystal.Thislargesinglecrystalingotprovides300mm(12in.)diameter
waferswhenslicedusingasaw.Theingotisabout1.5mlong(excludingthe
taperedregions),andweighsabout275kg.(PhotographcourtesyofMEMC
130
ElectronicsIntl.)
PatterningofSiO2
Sisubstrate
SiO
Hardenedresist
Chemicalorplasma
etch
(a)Siliconbasematerial
Photoresist
SiO
2
SiO
2
Sisubstrate
(d)Afterdevelopmentandetchingofresist,
f
(b)Afteroxidationanddeposition
ofnegativephotoresist
Sisubstrate
Si b t t
SiO
2
chemicalorplasmaetchofSiO
2
Hardenedresist
UVlight
Patterned
opticalmask
Exposed resist
Sisubstrate
(e)Afteretching
Sisubstrate
Sisubstrate
( ) St
Exposedresist
SiO
2
(f)Finalresultafterremovalofresist
132
(c)Stepperexposure
( )
IntegratedcircuitLateralPNPTransistor