748 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-11, NO.

6, DECEMBER 1976
An Integrated NMOS Operational Amplifier with
Internal Compensation
YANNIS P. TSIVIDIS, MEMBER, IEEE, AND PAUL R. GRAY, SENIOR MEMBER, IEEE
,4bstr-act An internally compensated operational amplifier is de-
scribed which has been fabricated using n-channel Algate MOS tech-
nology. Only enhancement mode devices are used, and the circuit
has been designed so that its performance is insensitive to process
parameters.
1. INTRODUCTION
LTHOUGH single-channel (NMOS or PMOS) technology
A
has been used extensively in the realization of digital
large-scale integrated (LSI) circuits, its use to perform
analog functions has proved more difficult. Perhaps the most
generally useful analog circuit function is that of an opera-
tional amplifier. For reasons to be discussed later, single-
channel MOS technology is not as well suited as bipolar or
CMOS to the realization of an operational amplifier-like func-
tion. Nevertheless, the ability to realize this function in single-
channel MOS circuits is important for two reasons. First, as
the level of circuit complexity which can be placed on a single
chip increases, the partitioning of subsystems into separate
analog and digital chips becomes cumbersome. Thus arises a
need to fabricate both analog and digital circuit functions on
the same chip. Examples of such subsystems are A/D and D/A
converters, PCM encoders and decoders, analog sampled data
filters, and so forth. In the realization of these functions,
single-channel technology is only one of several alternatives,
others being 12L, mixed bipolar/MOS and CMOS. However,
the single-channel technologies are the most cost-effective in
terms of cost per unit of digital function on the chip because
of their high yield, low fabrication cost, and high logic density.
Thus, provided the design difficulties can be overcome, it is
potentially less costly to realize these functions in single-
channel technology.
The second motivation for the single-channel realization of
the amplifier function is the application of such a circuit in
on-chip peripheral circuitry for various types of charge-transfer
device analog signal processors. Because of yield and other
considerations, these types of circuits are most effectively
realized in single-channel technology, and a strong need exists
for on-chip charge-to-voltage and voltage-to-charge converters
of reasonable performance.
Manuscript received June 11, 1976; revised July 28, 1976. This work
was sponsored by the National Science Foundation under Grant
ENG73-04184-A01.
Y. P. Tsividis was with the Department of Electrical Engineering and
Computer Sciences, University of California, Berkeley, CA 94720. He
is now with the Department of Electrical Engineering and Computer
Science, Columbia University, New York, NY 10027.
P. R. Gray is with the Department of Electrical Engineering and Com-
puter Sciences, University of California, Berkeley, CA 94720.
Previous attempts to design single-channel MOS amplifiers
have resulted in single-ended input configurations [1] , or dif-
ferential amplifiers which require external frequency compen-
sation with two capacitors [2] . This paper will describe an
internally compensated differential amplifier which is appli-
cable in many analog-digital MOS LSI circuits.
II. CIRCUIT OBJECTIVES
The requirements imposed on an amplifier used in the appli-
cations mentioned in Section I are usually different than those
for a general-purpose operational amplifier. Within a single-
channel MOS LSI circuit, the amplifier typically must drive
capacitive loads of 50 pF or more rather than resistive loads.
In addition, low input offset voltage and offset voltage drift
are not of primary importance since the offset voltage can be
stored on a capacitor and then cancelled. In many of the ap-
plications, the amplifier would be used as a buffer in a unity
gain feedback configuration. Only moderate open loop gain is
required in most of these cases. However, such a buffer should
be capable of fast settling when driving a capacitive load. In
addition, it ii desirable to devise a design whose performance
is not sensitive to process parameters, especially the device
threshold voltage. The latter can vary over a range of more
than 1 V from wafer to wafer, and therefore a mechanism
must be provided to render the circuit insensitive to such
variations.
In view of the above considerations, we have concentrated
our efforts in the design of a fast settling, low gain operational
amplifier which is especially suited for use with capacitive
loads.
III. LIMITATIONS IN SINGLE-CHANNEL MOS ANALOG
CIRCUIT DESIGN
Most of the problems encountered in single-channel MOS
analog circuit design result from the small value of the ratio of
transconductance to quiescent current inherent in the MOS
device, and the lack of availabilityy of complementary devices.
The latter problem makes the realizations of large values of
incremental load resistance within an amplifier impractical.
As a result, the voltage gain attainable in a single stage is quite
limited. For high gain in an inverter stage, high values of trans-
conductance for the amplifying devices must be used. The
transconductance gn of an MOS transistor in the saturation
region is given by:
gm=2
m
k ; I (1)
where k is typically 5 pA/V 2 to 10 pA/V 2, Z is the width of
TSIVIDIS AND GRAY: INTEGRATED NMOS
749
the gate, L is its length, and 1 is the quiescent drain current. It
is apparent that in order to obtain high transconductance,
large values for one or both of the parameters Z and 1 must be
used. A large value for Z will result in large area and large
parasitic capacitances. A large value of 1 will require high
power supply voltages and high power consumption. Also
associated with the low value of gm /1 is the high input offset
voltage expected from differential stages using MOS transistors
[3] ,
The quiescent gate-to-source voltages required in MOS
analog circuits are high, due to the low value of parameter k,
the high value of the threshold voltage (in the case of enhance-
ment mode devices), and the body effect. This makes the
design of output stages difficult. The use of source followers
at the output is undesirable in most cases, since the output
swing would then be very limited. On the other hand, using
simple inverters at the output stage results in a high output
resistance unless excessively high quiescent currents are used.
IV. CIRCUIT DESCRIPTION
A block diagram of the operational amplifier is shown in
Fig. 1. The input stage is a source-coupled differential ampli-
fier. The differential output signal of this stage is applied to a
differential-to-single-ended converter, which develops a
single-ended version of that signal. The converter drives a
cascode stage, around which feedback is applied through a
source follower and a capacitor, to implement a Miller com-
pensation scheme. Another source follower, fed from the
cascode stage, drives the output stage. The bias point inter-
dependence of the stages is such that their quiescent voltages
track one another, so that all stages except the last two remain
in their active region independently of process parameter
variations when the input voltage is zero.
The input stage is shown in Fig. 2. Only a limited voltage is
dropped across M6 and M9 so as to ensure that i147 and Ml O
will not be driven out of their saturation region if a large
common-mode input is applied. The differential gain of the
stage is given by:
(2)
The limited voltage drop across M6 and M9, along with power
consumption, size and frequency response considerations,
limit the differential gain to a nominal value of about 5.
The common-mode gain of the stage is given by:
G=
1
(3)
ml 2r08gm6
where r08 is the incremental output resistance of M8. To in-
crease the latter, and thus reduce GCW~, M8 has been designed
with a long channel. The resulting common-mode gain is
nominally 0.017.
The differential output of the input stage is applied to the
gates of M4 and Ml 1 in the circuit shown in Fig. 3. The
signals at the two gates are out of phase, one of them passing
through an inverting path and the other through a noninvert-
ing path, The inverting path consists of source follower M4,
SOURCE
c
FOLLOWER
r%
IN
1 lp
OUT
0
10
DIFFERENTIAL DIFFERENTIAL- CASCODE sOURCE OUTPUT
INPUT STAGE TO-31 NGLE-ENOEO STAGE FOLLOWER STAGE
CONVERTER
Fig. 1. Block diagram of the operational amplifier.
JOo
M6
d
42/24
M9
42124
-1
V07
k
DIO
d
IN+ M7 MIO
f
~ IN
432/12 432/12
I 1
T
I
5
~ M8
DC BIAS 84/24
-Vss
Fig. 2. Input stage. The channel width (Z) and length (L) is indicated
in micrometers for each device (Z/L).
F-ll-
~o 7 V*
M4 Mll
12/99 12/99
D12
h15 ~ M12
v
90/12
-i~s
Fig. 3. Differential-to-single+ nded converter.
its load M5, and the inverter Ml 2. Transistor Ml 1 acts as the
load to Ml 2, and the noninverting path consists of Ml 1 acting
as a source follower. Both signals appear in phase and are
summed at the drain of Ml 2. The differential-to-single-ended
gain of this stage is given by [4] :
[
Z%211rolz ~ + &7m4&3m12
Gdm2=
1
(4)
2(1 +gml~ro~~)
&mll(gm4 gins)
The value of this gain is 0.95.
The common-mode gain of the stage is given by [4]:
G
[
= gmllr012 ~ _ gm4gm 12
cm 2
1
(5)
1 +gm11rot2 gmll(gm4 gins)
and has a value of 0.09.
The differential-to-single -ended converter drives the stage
750 IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER 1976
+VDD
7
9
M21
144/12
VS21
DC BIAsx M19
210/12
D12
M20
DCti
M22
210/12 BIAS 295/12
~ss
Fig. 4. Cascode stage and output stage driver
+VDD
m
M25
31/40
18/26
M23
OUT
o
M26
486/24
VS21
M24
366/12
-Vss
Fig. 5. Output stage.
shown in Fig. 4. A cascode configuration is used in order to
reduce the Miller capacitance at the gate of J420, which would
otherwise load the converter of Fig. 3 and degrade the fre-
quency response. The gain of the stage is given by:
gm 20
G3.
(6)
gm18
and has a nominal value of 11. The output of this stage is fed
to the source follower M21, also shown in Fig. 4, which is
used both for level shifting purposes and to reduce the effect
of the input capacitance of the output stage on the frequency
response.
The output stage is shown in Fig. 5. The inverter Jf25 ,J426
has been designed with sufficiently large bias current so that
capacitive loads up to 70 pF can be charged from OV to *5 V
in 1 ~s. The output resistance of this inverter if no feedback is
applied is 1/gmz5 ~ 6 k~. This, in conjunction with a 70 pF
capacitive load, would create a pole in the open loop fre-
quency response at a frequency of 379 kHz, which would
make internal frequency compensation virtually impossible.
In order to lower the output resistance, shunt-shunt feedback
is applied by the addition of Jf23. The gain of the combined
stage IM23 ,M24, M25, and M26 is given by:
(7)
and is nominally equal to 6.6. The loop gain is approximately
equal to the gain of the inverter M25, M26, and the output
resistance of the stage is reduced to approximately 1.1 kfl.
Additional considerations in selecting the sizes for the four
devices are given in [4] .
Frequency compensation of the circuit is accomplished
through the capacit ante C, shown in Fig. 1, which is Miller-
multiplied by the cascode stage and used to create a dominant
pole in conjunction with the output resistance of the
differential-to-single-ended converter, which is approximately
equal to I/gm II . The compensation capacitor C is not con-
nected directly between the input and output of the cascode
stage because for an inverting gain stage with simple pole-
splitting compensation, the compensation capacitor, in addi-
tion to introducing a dominant pole, also introduces a right-
half plane zero corresponding to co, = gm /C, where gm is the
transconductance of the stage and C the compensation capaci-
tance. The right-half plane zero is clearly undesirable, since it
degrades the phase of the complete amplifier by 90 at high
frequencies, while at the same time eliminating the effect of
the dominant pole on the gain magnitude frequency response
by stopping the 20 dB/decade rolloff created by it. For the
values of C required and for the values of gm that can be
achieved, the frequency of the zero is lower than that of the
crossover frequency and thus frequency compensation be-
comes impossible. Although this zero often is present in
internally compensated operational amplifiers made with
bipolar technology, the transconductances there are large and
the frequency of the zero extremely high.
Physically, the zero is caused by feedforward through the
compensation capacitor [4] . To eliminate this feedforward,
a buffer implemented by a source follower is placed in series
with C, thus preventing the feedforward and therefore elimi-
nating the right-half plane zero, while at the same time allow-
ing feedback which gives rise to the desirable dominant pole.
Complete Amplifier
The complete amplifier schematic is shown in Fig. 6. It con-
sists of the individual stages discussed above, in addition to
two voltage dividers Ml, M2, M3 and Ml 5, Ml 6, Ml 7, which
are used to bias the current sources M8, Ml 4, and M22. Tran-
sistor Ml 3 is the source follower used to prevent feedforward
through the compensation capacitor, the value of which is 40 pF.
The circuit is designed so that its operation is largely inde-
pendent of the threshold voltage VT, which varies consider-
ably from wafer to wafer. This is achieved by selecting the
Z/Ls of the devices so that the various quiescent voltages track
one another in such a way that the devices up to M21 are
maintained in the saturation region independently of the value
of VT. The voltage required at the gate ofM21 to drive the
output voltage to zero does depend on VT. However, the
range of values of that voltage for various values of VT, when
reflected to the input, corresponds to a small variation of the
input offset precisely due to the fact that the devices are in the
saturation region and therefore the gain between the input and
the gate ofM21 is high, independent of VT.
The quiescent voltage tracking mentioned above will now be
described. The symbol S will be used to denote the Z/L ratio
TSIVIDIS AND GRAY: INTEGRATED NMOS 751
+15V
T
Ml J M6 M15 J 4 M25
Vc
M4 Mll M13 I
I
M21
VA
M2 M16 M19 M23
INV.
VB
IN
IN
%
1 M20
VB
M5 I M12Ml4t-
0
M3 I ME M17 1- 1 M22
Fig. 6. Complete amplifier schematic diagram.
after lateral diffusion has been taken into account.
L
-15V
The input
stage and the differential-to -single-ended converter are sym-
metric, so that for zero differential input, V&j = VG~~,
VDG12 = VDG5 = O, and VGS4 = VGsll , independent of VT.
We have chosen S8 = S3 so that 18 =13 = 11. Therefore, a cur-
rent equal to II/2 flows through M6 and M9. Also, Sb = S9 =
SI /2, and therefore VGSI = VGS6 = VGS9. We therefore have
VGS~ + VGS3 = VGS~ + VGS5. By choosing Sz /S3 = S4/S5 =
Sll /Slz , we get VGS2 = VGS4 = VGsll and VGS3 = VGS5 =
VGS12. Therefore, since VDG12 = O, we have VDS12= VGS12=
VGS3, and this has been shown to be the case independent of
VT. As long as VT> O, Ml 2 will remain in the saturation
region, where its transconductance is high.
The bias string Ml 5, Ml 6, Ml 7 is used to bias the cascode
stage and the source followers. There is no symmetry between
this bias string and the string consisting of Ml, M2, M3 due to
the different biasing requirements of the cascode stage [4] .
Specifically, in the string Ml, M2, M3 we have S1 = S3,
whereas in the string Ml 5, Ml 6, Ml 7 we have Slh = SIT.
However, the two strings have been designed so that VGS17 =
VGS3 for a typical value of VT, and this relation is approxi-
mately true even if VT deviates from the typical value. There-
fOre, SlnCe VGSJO = v~s~~ = v&3, we have VGS2(3= VGS17.
We have chosen S~g/S~fj = Szo/S17, and therefore VGs16=
VGs19 and VGS20= VDS20, so that M20 is kept in the satura-
tion region for any VT> O. Finally, we have S15/S16 =
S18/S19, and therefore VGS18= VGS15, so that VDS19= VGS~9,
which guarantees that Ml 9 is also kept in the saturation
region.
V. EXPERIMENTAL RESULTS
The amplifier has been fabricated as an integrated circuit
using n-channel Al-gate MOS technology. No p+ isolation
diffusion was used. The chip photograph is given in Fig. 7.
As seen, numerous pads are used for experimentation. The
active area of the amplifier is 0.77 mm2. A 12 #m minimum
feature size and a minimum alignment tolerance of 3 pm were
used, and the devices M6, M9, M7, M1O, M4, Ml 1, M5, M12
have been laid out so that proper matching is retained in the
presence of misalignment. The mask dimensions for the devices
are given in Table 1.
The device threshold measured was 0.2 V. To simulate
higher threshold voltages typical of industrial processing, a
substrate bias of 5 V was used so that the eff~ctive threshold
of the devices whose source is connected to - VSS WFS1.5 V.
Fig. 7. Photograph of the integrated circuit.
TABLE I
MASK DEVICE DIMENSIONS
Device Z(pm) L(flm)
Ml
M2
lvr-3
M4
M5
M6
M7
M8
M9
Mlo
Ml 1
Ml 2
Ml 3
M14
M15
M16
M17
Ml 8
M19
M20
M21
iW22
M23
M24
M25
M26
84 24
12 276
84 24
12 99
90 12
42 24
432 12
84 24
42 24
432 12
12 99
90 12
138 12
132 12
12 194
54 12
54 12
12 55
210 12
210 12
144 12
295 12
18 26
366 12
31 40
486 24
The range of threshold voltages encountered throughout the
circuit will of course be different from that of a circuit where
the devices have VT = 1.5 V without substrate bias. However,
the fact that the operation of the circuit is based on quiescent
voltage tracking rather than exact threshold voltages justifies
the use of substrate bias. Also, although the substrate bias
used will decrease the junction capacit antes, computer simula-
tion shows that these capacitances are not the ones that
dominate the circuit performance, and that the results ob -
t ained with substrate bias are representative of those expected
with no substrate bias and a higher threshold.
The dc transfer characteristic of the amplifier is shown in
752 IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER 1976
10
v
OUT
(v) 8
6
4
2
0
-2
-4
-6
-8
-lo
Gain
magnitude
(dB)
.
20 -10 0 10 20
V,N -VoS (mV)
Fig. 8. DC transfer characteristic.
60
__ ~-- -.,
50
\
1~
,:t-
40
\
30
20-
k
lo-
0
\
103 I04 I05 I06 I07 102
-30
Gain phase
(deg )_60
-90
-120
P
2
10
E
\
+
-+
Frequency ( Hz)
(a)
P
--
I 04
Frequency (Hz)
(b)
Fig. 9. Frequency response of the complete amplifier. (a) Gain magni-
tude. (b) Gain phase.
Fig. 8 and the frequency response is shown in Fig. 9. The step margin and cause oscillation. The acquisition to an accuracy
response of the amplifier when connected in a unity gain con- of 11 percent time is 2 us, with an input step of 5 V,
figuration is shown in Fig. 10 for a capacitive load of 70 pF The performance of the amplifier is summarized in Table II.
connected to the output through a series device with Z/L = 3. The first two parameters describe the observed distribution
This device is necessary, since direct connection of the load of input offset voltage over a sample of three wafers. While
capacitance to the output stage would degrade the phase these parameters are much worse than those observed for a bi-
TSIVIDIS AND GRAY: INTEGRATED NMOS
F
+16V
Ell ;
Oul
3 Q
+16V
w
OUT
.ar
3 Top
-14V
Fig. 10. Step response. (a) Positive input. (b) Negative input.
TABLE 11
PERFORMANCE PARAMETERS FOR +15 V POWER SUPPLIES
Input offset voltage mean 9 mV
Input offset voltage standard deviation 66 mV
Low frequency gain 51 dB
Common-mode rejection ratio 70 dB
Unity-gain frequency 5 MHz
Slew-rate (positive input) 7 v//.ks
Slew-rate (negative input) 7 V1l.ls
Power supply rejection 4.5 mV/V
Input noise voltage (1 OHz to 10 kHz) 60 NV
Total harmonic distortion
(1 kHz, output 10 V p-p) 1.5 percent
Power supply current 5 mA
polar circuit, the offset can be sampled and canceled in most
applications because of the sample/hold capability inherent in
[1]
MOS technology. The unity-gain frequency and slew rate are
comparable with many bipolar amplifiers. The open loop gain
of 51 dB restricts the circuit to low values of closed loop gain
[2]
and moderate levels of closed loop gain accuracy. [3]
VI. CONCLUSION
The realization of analog functions in single-channel MOS
technology is both useful and possible. An operational ampli-
fier using n-channel Al-gate technology has been realized
which occupies 0.77 mm2 of chip area, and has a power con-
sumption of 150 mW. The performance of the amplifier is
such that it can find use in A/D and D/A converter circuits,
PCM encoders and decoders, and charge transfer device trans-
versal and recursive filters.
ACKNOWLEDGMENT
[4]
[5]
REFERENCES
753
A. Boornad, E. Herrmann and S. T. Hsu, Low-noise integrated
silicon-gate FET amplifier, L!LYE J. Solid-State Circuits (Cor-
resp.), vol. SC-10, pp. 542-544, Dec. 1975.
P. W. Fry, A MOST integrated differential amplifier, IEEE J.
Solid-State Circuits (Corresp.), vol. SC-4, pp. 166-168, June 1969.
H. C. Lin, Comparison of input offset voltage of differential
amplifiers using bipolar transistors and field-effect transistors,?
IEEE J. Solid-State Circuits (Corresp.), vol. SC-5, pp. 126-128,
June 1970.
Y. P. Tsividis, Nonuniform pulse code modulation encoding using
integrated circuit techniques, Ph.D. dissertation, Univ. California,
Berkeley, 1976.
K. P. Burns, Optimization of offset in an NMOS operational
amplifier ~ Univ. California, Berkeley, M .S. Plan H Report, 1976.
Yannis P. Tsividis (M76), for a photograph and biography, see this
issue, p. 747.
The authors wish to thank Prof. D. A. Hodges and F.
L
/1
Hosticka for useful technical discussions and suggestions, K. P.
Burns for trimming the mask and fabricating additional paul R. Gray (s 65 .M6g_sM76), for a photograph and biography, see
samples, and D. McDaniel for valuable lab assistance. this issue, p. 747.