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Boolean Functions
3 lectures
Boolean Functions Minimization. Combinational Logic Design
Principles
4 lectures
Brief Description of Verilog
3 lectures
Basic Combinational Circuits
4 lectures
Finite States Machines (FSM)
3 lectures
Synthesis of Synchronous FSM
5 lectures
Content (1/2)
Basic Sequential Circuits
3 lectures
Problems of Synchronous Design
3 lectures
Asynchronous FSM. Self-Timed Circuits
3 lectures
Arithmetic Units
4 lectures
Programmable Logical Integrated Circuits (PLDs)
3 lectures
Memory Devices
3 lectures
Content (2/2)
2
n
words
2
n
words
m bit per word
n address lines
m data input lines
m data output lines
Memory is a collection of binary cells together with
associative circuits needed to transfer information to or
from any desired location.
Two primary categories of
memory: RAM and ROM
Semiconductor Memory
Read-Write Memory
Two types: SRAM and DRAM
SRAM: memory cell flip-flop
DRAM: memory cell capacity (drain substrate of MOS-
transistor).
The kinds of IC memory organization:
Linear-select (2D), two-dimensional (3D), compromise
(2DM).
RAM
module memory (enable, address, data_in, data_out, we,
read_write);
input enable, read_write;
input [3:0 ] data_in;
input [5:0] address;
output [3:0] data_out;
reg [3:0] mem[0:63]; // 644 memory
always @(data_in or enable)
if (enable)
if (!we) mem[address] = data_in; // write
else data_out = mem[address]; // read
else data_out = 4bz; // high impedance state
endmodule
RAM in Verilog
SRAM generally is used as a cache to hold recently used
instructions and data, to store data in small microprocessor
systems, often in embedded systems.
SRAM cell is RS or D latch.
Select
Input
Write
S
R
Out
S
I
W
O
Static RAM (SRAM)
O
0
S S
I
W
O
S
I
W
O
S
I
W
O I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
Write
Read
O
3
O
2
O
1
D
C
D
3
D
2
D
1 D
0
A
0
A
1
Four-
address
memory
with 4 bits
per word
Linear Select SRAM (Internal Structure)
Select 1
Input
Write
S T
R
Out
Select 2
S2
S1
I O
W
Two-dimensional memory cell
Word Line
Bit Line ~Bit Line
SRAM Cell
Data (bit)
CS
Memory
cells matrix
A
2
(n/2bits)
Row
deco-
der
(DC
X
)
Column decoder (DC
Y
)
1
A
1
(n/2bits)
CS
S1
S1
S1
S1
S1
S1
S1
S1
S1
S2
S2
S2 S2
S2
S2 S2
S2
S2
All O outputs from cells
are connected to this point
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
Input
Two-dimensional IC memory organization
Dout
(m
bits)
A
k
A
n-1
Memory array
2
n-k
m2
k
Data buffers
(column I/O)
Row
deco-
der
m2
k
bits
Din
(m bits)
A
0
. . . A
k-1
Column decoder
WR/RD
CS
Compromise
The structure IC with selectors (2DM)
The linear-select organization is used for IC memory with
small capacity. Address decoder is complicated:
2
n
AND elements (with n inputs).
Address decoder for two-dimensional IC organization is
simpler : 2 2
n/2
AND elements (with n/2 inputs).
Properties of SRAM:
fast
density is not very large six transistors per bit
doesnt need to be refreshed (data stays as long as
power is on).
basically is used for cache memory
SRAM
CS OE W
E
I/O
pins
Mode
1 x x z Not
selected
0 1 1 z Output
disable
0 0 1 Dout Read
0 x 0 Din Write
A
0
A
1
A14
WE
OE
CS
0
1 SRAM 0
. 1
. 2
. 3
14 4
5
W 6
OE 7
CS
.
.
.
SRAM has bidirectional data bus the same data pins are used
for both reading and writing.
Example: SRAM IC Memory
0
1
2
511
CS
WE
OE
Row
Deco-
der
Memory Array
51282
6
bit
Input
data
control
Column I/O
Multiplexers
A
2
A
3
A
4
A
5
A
6
A
8
A
9
A
11
A
13
A
0
A
1
A
7
A
10
A
12
A
14
Din/out 0
Din/out 7
Address
inputs
Data
outputs
D0
D1
D
m-1
Read Only Memory (ROM)
Horizontal lines lines of word selection,
Vertical lines lines of bit selection.
m output lines
Decoder
0
1
2
2
n
-1
n address
lines
Internal ROM Structure
Information is recorded with the help of mask in the final stage of
technological process.
As a connecting link diodes or MOS transistors are used.
11010001
10101011
Word line
bit line
+5V
Active
low
word
line (WL)
Active low bit lines (BL)
Mask Programmable ROM
A PROM chip is manufactured with all of its diodes or transistors
connected. The customer may program the ROM using PROM
programmer.
Fuse
A link is vaporized by selecting it using PROM address and data
lines and then applying a high voltage pulse (10-30V) to the
device through a special input pin (for programming).
DC
0
1
2
0
1
2
3
4
5
6
7
OR Matrix
Programmable ROM
Programmed by removing or creating special links.
1 0
0
1
WL
WL
BL BL
BL BL BL
Programmable ROM
BL
WL
WL
GND
BL
BL
WL
VDD
Word Line
Bit Line
1
0
ROM Cells
DC
V
DD
A
0
A
1
A
n-1
~D
0
~D
1
~D
7
Active high
word line
Active
low
bit lines
Application of MOS Transistors as
Memory Cells
Erasing old information and its replacement with the new one is
possible.
Erasing is carried out by ultraviolet rays in EPROM (erasable PROM)
In EEPROM (electrically PROM) by electrical signals.
Floating gate MOS transistors are used as connection links.
G
S
D Floating gate
Source
Substrate
Gate
Drain
n
+
p
Device cross-section
n
+
Polysilicon
SiO
2
Si
Erasable PROM
Active-high
word lines
Active-low bit lines
Storage Matrix in EEPROM
DC
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
6
A
14
A
0
A
5
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
0
1
511