Professional Documents
Culture Documents
9, SEPTEMBER 2006
Impact of Scaling on Analog Performance and
Associated Modeling Needs
Boris Murmann, Member, IEEE, Parastoo Nikaeen, Student Member, IEEE, D. J. Connelly, and
Robert W. Dutton, Fellow, IEEE
Invited Paper
AbstractThis paper explores modeling and technology-
scaling issues related to analog performance in advanced CMOS
technologies. Performance metrics for analog circuits are de-
ned, to provide insight into the impact of device scaling on
power-constrained analog circuit design. Current and previous
generation technologies (90 nm and older) are evaluated using
standard compact models. Technology nodes below 90 nm are
simulated at the device level to show trends in analog performance
metrics and to evaluate the impact of nonminimum gate length
and alternate doping proles. Results indicate that the modeling
of moderate-to-weak inversion behavior will continue to grow in
importance. Simulations suggest that using nonminimum length
and drain-side engineered devices at the 45-nm technology node
offers an attractive degree of freedom for analog circuit design.
Index TermsCMOS, distortion, future performance, scaling,
semiconductor device modeling.
I. INTRODUCTION
C
OMPACT models for simulation (e.g., Berkeley short-
channel IGFET model (BSIM) [1]) provide a critical
link between CMOS process properties and integrated circuit
performance. New generations of models have become ever
more complicated, reecting trends in technology evolution
and growing demands from the design community in terms
of modeling accuracy. Especially for analog circuit design,
accurate modeling poses fundamental challenges. Depending
on how the devices are used, key performance attributes are
strongly inuenced by device-level effects that are hard to
model and insignicant within the context of a digital ap-
plication. For instance, appropriately accurate modeling of
nonlinearities for analog purposes must cover a broad range
of biasing conditions, and generally requires accuracy in the
rst few derivatives. Hence, using mean-squared-error criteria
in tting currentvoltage (IV ) and chargevoltage (QV )
curves, across a wide range of bias conditions and process
corners, is neither sufcient nor optimal for analog circuit
design.
This paper discusses care about issues and related
compact-modeling needs within the context of scaling analog
Manuscript received February 16, 2006; revised May 12, 2006. The review
of this paper was arranged by Editor S. Saha.
The authors are with the Integrated Circuits Laboratory, Stanford University,
Stanford, CA 94305 USA.
Digital Object Identier 10.1109/TED.2006.880372
circuits into sub-90-nm CMOS technologies. The focus of this
paper is not to provide a comprehensive discussion of compact
models, nor do we attempt to resolve the controversial dis-
cussion on analog-performance scaling in future technologies
(see [2] for a comprehensive discussion). Rather, we aim to
present a set of basic metrics that should be considered in the
calibration and renement of models for current and future
technologies. Here, it is useful to differentiate between compact
models, which are targeted to provide a comprehensive set of
expressions that are used to t IV and QV data in support of
numerical simulation of circuits, and metrics, which provide a
means to evaluate the model adequacy for application-specic
purposesin this case for analog-circuit-design metrics.
This paper is organized as follows. In Section II, we de-
ne a set of analog performance metrics and illustrate ba-
sic scaling trends. Focus is placed on identifying a common
denominator across analog-circuit variants with no emphasis
on a particular application domain (e.g., RF versus mixed
signal, high speed versus precision designs). Section III uses
technology computer-aided design (TCAD) tools to consider
the implications of scaling at the 45- and 65-nm technology
nodes
1
and discusses important aspects and subtleties of ana-
log performance that impact compact modeling. Included in
this discussion are performance data for nonminimum length
(NML) and asymmetric (A) devices with no pocket implant
2
at
the drain end. We believe that such devices and their attributes
will be of growing importance in making analog design feasible
in the sub-90-nm regime. Section IV will summarize the results
and give a brief conclusion.
II. ANALOG PERFORMANCE METRICS AND
SCALING TRENDS
A basic challenge in analog design lies in achieving a good
balance between the bandwidth and the power efciency of a
circuit. While this tradeoff is complex in general and can be
highly dependent upon circuit architecture and target specica-
tions, it can be linked to fundamental attributes of transistors.
1
In this paper, we refer to a particular technology in terms of the DRAM
staggered contact Metal-l 1/2 pitch as specied in [3].
2
Pocket implant (or halo implant) refers to the local substrate doping at
both the source and drain regions used to avoid source-to-drain punchthrough
in minimum channel length devices [4].
0018-9383/$20.00 2006 IEEE
MURMANN et al.: IMPACT OF SCALING ON ANALOG PERFORMANCE AND ASSOCIATED MODELING NEEDS 2161
For an arbitrary device that operates as a linear transconductor,
one can dene the following gures of merit:
T
= g
m
/C
gg
,
which quanties how much total gate capacitance (C
gg
) must
be driven at the controlling node per desired transconductance,
and g
m
/I
D
, which enumerates how much current must be
invested per g
m
. Based on rst-order MOS device models,
3
one can express the latter quantity using the following simple
equations for strong and weak inversion:
g
m
I
D
stronginversion
=
V
GS
V
t
g
m
I
D
weakinversion
=
V
thermal
. (1)
In the above expressions, V
thermal
= kT/q, and the and
terms follow from the power-law and subthreshold slope
coefcients, respectively. As the quiescent-point gate overdrive
(V
GS
V
t
) approaches zero, the strong-inversion approxima-
tion becomes invalid, and g
m
/I
D
gradually approaches an up-
per limit in weak inversion. While the denition of a threshold
voltage (V
t
) is a convenience, which is based on the extrap-
olation of current or transconductance becoming arbitrarily
small on a linear scale, this quantity provides a useful design
reference in terms of voltage constraints and operating regions
for the circuit design. Hence, the normalized quantity V
GS
V
t
is used in our discussion.
Trends for f
T
=
T
/2 (right y-axis) and g
m
/I
D
(left
y-axis) over several past generations of technology are shown
in Fig. 1(a). In contrast to g
m
/I
D
, f
T
of a transistor is largest
in strong inversion and generally increases with V
GS
V
t
.
As a result, there exists a fundamental tradeoff between the
transconductor efciency and the self-loaded bandwidth of
a transistor. Neglecting other existing tradeoffs, a key task in
analog MOS circuit design is to determine V
GS
V
t
(within
applicable design constraints) such that the bandwidth ob-
jectives are met while operating at the corresponding maxi-
mum possible g
m
/I
D
(lowest power). For a scenario where
the bandwidth is exible and part of an overall optimization
process, it is interesting to consider the product of g
m
/I
D
and
f
T
, as shown in Fig. 1(b). For the given technologies, this
quantity exhibits a sweet spot around a gate overdrive of
100 mV, which is a commonly found bias condition in many
of todays moderate-to-high speed designs.
Based on Fig. 1, one might conclude that scaling brings
only benets for analog design: signicantly higher f
T
with
every process generation together with only an insignicant
reduction in g
m
/I
D
. One important factor that often diminishes
the benet of scaling is the associated reduction in supply
voltage (V
DD
) and signal headroom. As shown in early papers
that were concerned about this issue [5], power dissipation
in a circuit that is limited by thermal noise is approximately
3
Above threshold I
D
(V
GS
V
t
)
and in subthreshold I
D
exp(V
gs
/V
thermal
).
Fig. 1. BSIM3/BSIM4 simulation data for minimum length NMOS devices
in recent CMOS technologies. (a) Transconductor efciency g
m
/I
D
(left
y-axis) and transit frequency f
T
(right y-axis) versus gate overdrive (V
GS
V
t
). (b) Product of g
m
/I
D
and f
T
versus V
GS
V
t
. The transistors are biased
at V
DS
= V
DD
.
inversely proportional to V
DD
, assuming that V
GS
V
t
(i.e.,
g
m
/I
D
) is kept constant. This suggests that power would
double, e.g., when porting an analog function from 180- to
90-nm technology.
In reality, we have not seen this explosion in power dissipa-
tion for several reasons, some of which are rather complex and
require architecture and specication-dependent reasoning [6].
However, a rather fundamental factor that often helps mitigate
a power penalty in scaled technologies stems from the exploita-
tion of increasing f
T
. When porting an analog function with
a xed bandwidth requirement to a shorter channel process,
the constituent devices can be biased at a lower V
GS
V
t
(and
hence higher g
m
/I
D
) to provide the required f
T
. For instance,
90-nm technology yields f
T
= 50 GHz with g
m
/I
D
= 15 S/A.
In a 130-nmtechnology, f
T
= 50 GHz limits g
m
/I
D
to approx-
imately 8 S/A (see Fig. 1).
While working with high g
m
/I
D
greatly helps in lower-
ing power for applications that do not demand an extremely
high bandwidth, it comes with a penalty in terms of linearity.
Transistors operated at large g
m
/I
D
(small V
GS
V
t
) exhibit
a more bipolar junction transistor (BJT)-like behavior, and
hence show worse distortion than for a MOSFET in strong
inversion (i.e., V
GS
V
t
> 200 mV). This is illustrated in
Fig. 2(a) and (b), which shows the linearity performance of
various technologies versus g
m
/I
D
. The metrics used here are
VIP
2
and VIP
3
, which represent the extrapolated gate-voltage
amplitudes, at which the second- and third-order harmonics,
respectively, become equal to the fundamental tone in the
2162 IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 53, NO. 9, SEPTEMBER 2006
Fig. 2. Transconductance linearity of minimum length NMOS devices in
recent CMOS technologies (BSIM3/BSIM4 simulation data). (a) VIP
2
versus
g
m
/I
D
, and (b) VIP
3
versus g
m
/I
D
. VIP
2
and VIP
3
are the extrapolated
gate voltage amplitudes, at which the second- and third-order draincurrent
harmonics become equal to the fundamental tone. The transistors are biased
at V
DS
= V
DD
. Curves for an ideal square law device and a (resistively)
degenerated BJT are included for reference.
devices draincurrent (I
D
). Mathematically, these parameters
are dened as
VIP
2
=4
g
m
g
m2
VIP
3
=
24
g
m
g
m3
(2)
where
g
m2
=
2
I
D
V
2
gs
g
m3
=
3
I
D
V
3
gs
. (3)
The VIP
3
peak, which is shown in Fig. 2(b), is due to the so-
called second-order-interaction effect and can be explained as a
cancellation of the third-order nonlinearity coefcient by device
internal feedback around a second-order nonlinearity [7]. In
practice, it is very hard to utilize this innitely linear point.
Nevertheless, accurate modeling of the second-order interaction
is needed to provide reasonable bounds and margins for design.
Going back to the above numerical example, we see from
the graphs in Fig. 2 that both VIP
2
and VIP
3
deteriorate
signicantly when g
m
/I
D
is increased. For example, moving
from g
m
/I
D
= 8 to 15 S/A brings a 5x and 1.4x reduction in
Fig. 3. (a) Draincurrent (I
D
) and (b) intrinsic gain (g
m
/g
ds
) versus drain-
to-source voltage (V
DS
) for minimum length NMOS devices in recent CMOS
technologies (BSIM3/BSIM4 simulation data). All transistors have W/L = 20
and are biased at V
GS
V
t
= 0.1 V.
VIP
2
and VIP
3
, respectively. It is important to note here that
the design trend toward a higher g
m
/I
D
will not only have
implications on linearity performance but will also demand a
higher accuracy in compact modeling. For instance, models that
rely on a mathematical t to describe the transition region from
strong- to weak-inversion will not yield sufcient accuracy for
distortion-sensitive circuits that are biased at high g
m
/I
D
(i.e.,
V
GS
V
t
< 100 mV).
Aside from low headroom and the increasingly important
impact of nonlinearities, analog designers tend to be concerned
about the available voltage gain in short-channel technologies.
Fig. 3(a) and (b) shows typical I
D
V
DS
characteristics and
a plot of intrinsic transistor gain (dened as g
m
/g
ds
). As
one can clearly see, intrinsic gain is getting worse with each
technology node as a result of increased output conductance
in short-channel MOS devices, resulting from various physical
drain-leakage mechanisms (i.e., gate-inducted drain leakage,
band-to-band tunneling) as well as generally worse electrostatic
control of the channel by the gate versus drain electrodes.
Especially in op-amp-based analog circuits, which leverage
intrinsic gain to linearize and desensitize their transfer func-
tions, the low gain of minimum length devices in current and
future technologies is of great concern. Often, designers are
forced to work with NML devices to overcome this problem,
and generally rely on reasonably accurate compact models to
carry out this optimization. In Section III, we will use TCAD
simulations to evaluate trends in attainable gain in minimum
and nonminimum length devices in sub-90-nm technology.
MURMANN et al.: IMPACT OF SCALING ON ANALOG PERFORMANCE AND ASSOCIATED MODELING NEEDS 2163
Fig. 4. I
D
V
DS
curves for devices at the 65-nm node. Extracted measure-
ment data from [12] (data points marked
24g
ds3
/g
ds
) are comparable to those obtained
for standard CMOS devices.
Fig. 12. TCAD-based linearity comparison of a minimum length NMOS
(L
physical
= 24 nm) in 45-nm technology with an NML device (L
physical
=
80 nm) and an A device (L
physical
= 80 nm). (a) VIP
2
versus g
m
/I
D
, and (b)
VIP
3
versus g
m
/I
D
. Curves for an ideal square law device and a (resistively)
degenerated BJT are included for reference.
Fig. 12 illustrates the (g
m
) linearity performance of the
altered devices. Here, we see that a longer channel and/or
omitting the drain-side pocket implant results in even further
improvements in distortion. Our data suggests that the second-
order interaction peak shifts to very large values of g
m
/I
D
,
which makes the devices well suited for design in this biasing
regime.
IV. CONCLUSION
This paper has explored challenges in modeling and tech-
nology scaling related to analog performance in advanced
MOS. Starting with predictions based on BSIM models for
several generations of technology (180, 130, and 90 nm);
key metrics that impact circuit performance have been de-
ned and quantied. Next, these same metrics have been
evaluated based on device-level (TCAD) simulations, using
extensions of well-tempered MOS scaling trends for 65- and
45-nm technology nodes. While several metrics show a contin-
ued improvement with scaling, intrinsic gain falls to very low
values at the 45-nm node.
Finally, two device variationsnonminimum channel-length
and modied drain doping prole devicesare used to demon-
strate possible tradeoffs in performance metrics. Gaps in analog
performance using minimum feature size devices can be over-
come with longer channels and changes in drain-side doping
proles. Such devices in 45-nm technology exhibit f
T
values
MURMANN et al.: IMPACT OF SCALING ON ANALOG PERFORMANCE AND ASSOCIATED MODELING NEEDS 2167
that are comparable to those of minimum length transistors in
a 90-nm process while providing a signicantly higher intrinsic
gain and improved linearity.
For analog design in advanced sub-90-nm technologies,
compact models will need to undergo careful crafting and
calibration to deliver sufcient accuracy in the presence of the
anticipated trends discussed above. Important factors include
the continuing shift toward lower gate overdrive and its impact
on linearity and the prediction of intrinsic gain versus drain-
to-source bias. Furthermore, NML devices and transistors with
modied doping proles must be modeled with care, as they
represent an attractive solution for ongoing progress in analog
design below the 90-nm technology node.
ACKNOWLEDGMENT
The authors would like to acknowledge the Center for Inte-
grated Systems (CIS) for fellowship support as well as research
support from the MARCO program (MSD). We appreciate
assistance from W. Zhao and Prof. Y. Cao (ASU) in providing
help with PTM and related data/calibration issues. We also
gratefully acknowledge O. Nayfeh and Prof. D. Antoniadis
(MIT) for providing the technical assistance and helpful dis-
cussions concerning physical modeling issues associated with
the well-tempered MOS device simulation. Furthermore, we
thank Prof. H.-S. P. Wong (Stanford) for his insightful contri-
butions to this paper.
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Boris Murmann (S99M03) received the
Dipl.Ing. (FH) degree in communications engi-
neering from Fachhochschule Dieburg, Germany,
in 1994, the M.S. degree in electrical engineering
from Santa Clara University, Santa Clara, CA, in
1999, and the Ph.D. degree in electrical engineering
from University of California, Berkeley, CA, in
2003.
From 1994 to 1997, he was with Neutron
Mikrolektronik GmbH, Hanau, Germany, where he
developed low-power and smart-power ASICs in
automotive CMOS technology. During 2001 and 2002, he held internship po-
sitions with the High-Speed Converter Group at Analog Devices, Wilmington,
MA. Since 2004, he has been an Assistant Professor with the Department of
Electrical Engineering, Stanford, CA. His research interests are in the area of
mixed-signal integrated circuit design with special emphasis on data converters
and sensor interfaces.
Parastoo Nikaeen (S02) was born in Tehran, Iran,
in 1979. She received the B.S. degree in electrical
engineering from Sharif University of Technology,
Tehran, Iran, in 2001 and the M.S. degree in electri-
cal engineering from Stanford University, Stanford,
CA, in 2004. She is currently working toward the
Ph.D. degree at the same university.
Her research interests include modeling and de-
sign of analog and mixed-signal VLSI.
D. J. Connelly, photograph and biography not available at the time of
publication.
Robert W. Dutton (S67M70SM80F84) re-
ceived the B.S., M.S., and Ph.D. degrees from Uni-
versity of California, Berkeley, CA, in 1966, 1967,
and 1970, respectively.
He has held summer staff positions with Fairchild,
Bell Telephone Laboratories, Hewlett-Packard, IBM
Research, and Matsushita during 1967, 1973, 1975,
1977, and 1988, respectively. He is a Professor
of electrical engineering with Stanford University,
Stanford, CA, and the Director of Research with the
Center for Integrated systems. His research interests
focus on integrated circuit process, device, and circuit technologiesespecially
the use of computer-aided design (CAD) in device scaling and for RF applica-
tions. He has published more than 200 journal articles and graduated more than
four dozen doctorate students.
Dr. Dutton was an Editor of the IEEE CAD Journal (1984-1986), winner of
the 1987 IEEE J. J. Ebers and 1996 Jack Morton Awards, 1988 Guggenheim
Fellowship to study in Japan, and was elected to the National Academy of
Engineering in 1991, and also been honored with the C&C Prize, Japan, in
2000. Most recently, he received a Career Achievement Award (2005) from
the Semiconductor Industry Association (SIA) for sustained contributions in
support of research that is critical to SIA needs.