28nm Silicon and Design Enablement The Foundry and EDA Vendor Perspective

IC Compiler 32/28nm Webinar Series
28nm Silicon And Design Enablement

The Foundry And EDA Vendor
Perspective
JC Lin
Vice President R&D
IC Compiler
Synopsys 2010
Today
Done
32/28nm Design Challenges
Done
Addressing 32/28nm Design

Challenges
Done
Fastest Time to Tapeout

with IC Validator
Done
Realizing Todays 32nm

and Beyond Large Designs
Done
Manufacturing-Aware
Routing
Done
Extraction For
32/28nm
Todays Topic
Synopsys 2010
28nm Silicon And Design Enablement

A Foundry And EDA Vendor Perspective
Welcome!
JC Lin
Vice President, R&D
IC Compiler
Synopsys
Synopsys 2010
32/28nm Design Enablement

Overview of Synopsys Solutions At 32/28nm
Featured Technologies
In-Design STA: Final-stage Leakage Recovery
In-design physical verification: Automatic Litho-repair
Using Pattern Matching Technology
Synopsys 2010
Synopsys Solutions At 32/28nm

Variability
High accuracy
MCMM throughout the
flow
Enhanced Manufacturing
Compliance
Routing, Physical
Verification & Test
PrimeTime/StarRC
IC Validator
Galaxy
Design
Compiler
Low Power
Comprehensive flow
Major advances in
2010.03 and 2010.12
Design Complexity
IC
Compiler
Runtime speedup
40M+ design handling
Production proven across 32/28nm process nodes

Synopsys 2010
Leading The Way In Tapeouts At 32/28nm

@ 32/28nm
100
90
80
70
60
50
40
30
20
10
First to 45nm, First to 32nm

Synopsys 2010
Q2'10
Q1'10
Q4'09
Q3'09
Q2'09
Q1'09
Q4'08
Q3'08
Q2'08
Q1'08
Q4'07
Q3'07
Q2'07
Q1'07
Q4'06
Q3'06
Q2'06
Q1'06
Q4'05
High Accuracy Flow Reduces Margins

Critical For Convergence At 32/28nm
Device & Delay

Models
RC models & Net

Topology
Composite Current Source Models (CCS)
Driver
Model
Reduced Order
Network Model
Advanced OCV
Receiver
Model
U
2
Output current waveform in library

slew
Current vectors
0.7
0.5
0.2
0.1
U3
U1
U4
output
cap
.023 .047 .065 .078 .091
Synopsys 2010
NLDM
CCS
Elmore
Arnoldi
NLDM
CCS
Depth
Derate
1.2
1.2
1.15
1.15
1.08
1.08
Concurrent Multicorner Multimode

Reduces Uncertainty At 32/28nm
1-core
4-core
Design
Compiler
Design
Planning
Placement
3
2
CTS
FCLK
TCLK
MCMM
Full Flow MCMM with SI

6
New: MCMM
CTS/CTO
RTL to Layout
Multi-Voltage
Multicore Support
Routing
0
2009.06
2010.03
2010.12
Comprehensive MCMM support - faster TAT, best QoR and easy to use
Synopsys 2010
Enhanced Reliability At 32/28nm

Preventative EM & Integrated IR Flow
Electromigration
Aware CTS
In-Design PrimeRail
IC Compiler Integration
User provided
X-Y padding
Manufacturing
Error Browser
identified missing via
Y
Before EM-Aware CTS
After EM-Aware CTS
Based on guidance
IC Compiler adds in the
missing via
Clock cell
Logic cell
Logic cell
Clock cell
Comprehensive flow addresses EM & IR issues

Synopsys 2010
Comprehensive Low Power Flow

Multi-Voltage And UPF Support
MV Support
Auto-insertion of LS/ISO
cells
Disjoint VA and AlwaysOn Synthesis
MV-aware power
network synthesis
MTCMOS power gating
Improved
Productivity - UPF
Multi-voltage
Aware Opt.
Top
RTL
Mid
UPF
Bot
Design Compiler
Gate
Logic View
UPF
AO (VA)
IC Compiler
AO (VA)
Gate
Gate (PG)
UPF
Physical View
Production proven automated flow produces best QoR
Synopsys 2010
10
SD PD
Low Power CTS

Complete Support At 32/28nm
New In 2010.12
Smart selection of buffers vs.
inverters
XOR Clock Gating
Datapath For CTS
data[0:7]
0
Power driven sizing

Intelligent clock net layer
selection
clock
dly[0:7]
I
C
G
Target transition relaxation
10% reduced power OOTB
Extra 10% reduced power
Datapath ICG
placement & routing
~30% less power
Significant clock tree power savings for high-performance designs
Synopsys 2010
11
Best Leakage QoR

MCMM Aware, Handles More VTs
MCMM
Throughout
180
160
Power (mW)
120
In-Design STA
20%
ICC Only MCMM
140
Physical Flow
DCG+ICC
MCMM
%Improvement
18%
16%
Place Opt
14%
12%
100
10%
80
8%
60
Clock Opt
6%
40
4%
20
2%
Route Opt
0%
Final-stage
Leakage Recovery
Customer Designs
On average 7% better leakage
Optimizing leakage and other

costs through the flow
Delivers Maximum
Leakage Savings
Better leakage and timing - faster convergence at 32/28nm
Synopsys 2010
12
Faster Design Exploration

20M Instances In One Day
Exploration
Placement
Faster
Global Route
Virtual IPO
fanout
43
32
VIPO
43
32
plangroup
1
plangroup 2
47
Coarser placement no legalization
25M instances in 1 hour
Global routing results

see top-level congestion early
budgeted
output delay
Provides early look at timing QoR
2X Faster initial floorplan creation
Synopsys 2010
13
Feasibility Flow
Faster & Easy To Debug
Categorized
Reports
Feasibility
Optimization
Check & Report
Timing Histogram
(baseline, feasibility)
Infeasible
paths
Optimization on
feasible paths
masked
User customizable
What Next recommendations
2X faster place_opt &

1.5X clock_opt to assess dirty SDC
HTML links to reports and/or GUI for

debug
Increased designer productivity in the early stages of the design

Synopsys 2010
14
Faster Hierarchical Design Planning

On Demand Loading Technology
On-Demand
Loading
Top-level
Designers View
Original
netlist
1.8M Cells
On-demand
netlist
50K Cells
Removes internal logic within partitions to place

& optimize interface logic
Top level design has the top level and

interface cells to route & time (GUI)
2.8X runtime and 2X memory improvement
Synopsys 2010
15
32/28nm Rule Formulation & Support

Placement Rules
Routing Rules
2x
Soft Rules
Soft rule for

wire spacing
Yield
1x
Example: 3-neighbor, endof-line via-enclosure rule
Standard Cell
Filler Cell
Yield vs.
spacing plot
Supported by leading foundries and major IDMs
Synopsys 2010
16
H S Spacing
Zroute Manufacturing-Aware Router

Tapeout Proven At 32/28nm
Core Technology
Realistic
Connectivity
Manufacturing
Compliant
Multicore Delivers
3X Speed-up
Dynamic Maze
Grid
Multi-threaded
Dynamic
Grid
Virtual
Wire
Redundant Vias
Advanced Design
Rules
0.6S
Polygon Manager
X Y
0.6S
S
Wire widening &

spacing
Z
S
Litho friendly routing
# of Cores
3X Speed-up, higher QoR, better manufacturability
Synopsys 2010
17
In-Design Physical Verification

Improved Productivity For The Physical Designer
In-Design DRC
In-Design Metal Fill
Auto-Repair
Timing-Aware
Signoff Quality
10x Faster
Incremental
Highest Density
Synopsys 2010
18
In-Design LCC
Automatic
litho-repair using
pattern matching

In-design physical verification: Automatic Litho-repair
Using Pattern Matching Technology
Synopsys 2010
19
Leakage Trends At Advanced Nodes

ITRS Leakage Power Projections
MOSFET Leakage Current Components
Sub-threshold leakage current dominates total leakage power

Advanced nodes require new techniques
Leakage QoR with leakage variants (eg. Channel-length variation, multi-Vt)
Managing increasing leakage variability
Need to approach leakage optimization from a device modeling perspective

Synopsys 2010
20
Leakage QoR With Leakage Variants

Channel-Length Variation, Multi-Vt Libraries
Increasing channel length is also referred to as CD biasing
Besides Vt variants, leakage reduction is possible by increasing gate length
Potential foot-print equivalent leakage variants in standard cell libraries
Example: 3 different leakage variants of a NAND3 with CD biasing
OUT
A1
A1
OUT
A1
A2
A2
A2
A3
A3
A3
Significantly reduced impact on

top-pin-to-out timing with
considerable leakage reduction
Synopsys 2010
21
No impact on most timing with

some leakage reduction
For most effective

leakage reduction
OUT
In-Design STA -- Final-Stage Leakage

Recovery
Used on final netlist for leakage

recovery
Reduces leakage while preserving
signoff timing/DRC
Minimal physical perturbation
Driven by PrimeTime STA

Augments leakage savings
delivered by standard leakage
flow in IC Compiler
Final-Stage Leakage Recovery

400
Leakage Power (uW)
Architected for 15+ channellength based leakage variants

and Vt libraries
Before
After
300
62%
Less
200
48%
Less
100
0
40nm
864K cells
4 Vth
BC/WC
32nm
2M cells
7 Vth
4 scenarios
% Leakage recovery depends on how much power

optimization was done earlier in flow
Synopsys 2010
22

In-Design Physical Verification: Lithography Hotspot
Prevention Using Pattern Matching
Synopsys 2010
23
Manufacturing Challenges at 32/28nm

Sub-Wavelength
Gap
Feature Size
More & More

Rules
Wavelength
Size (um)
3.0
0.436
0.1
2000
10
Complex Feature
Dependencies
DRC-clean
1500
2.0
Number of Rules
0.6
0.365
0.35
1000
0.193
0.18
65nm
0.01
500
Litho
Hotspot
32nm
0
350 250 180 150 130 90 65 45 32
Poor process printability
Difficult to write and maintain
Beyond nearest feature
Address Lithography Limiting Patterns During Design

Synopsys 2010
24
In-Design PV Litho Hotspot Prevention

Built on Patented Pattern-Matching Technology
Prevent
Match
IC Compiler (ICC)
IC Validator (ICV)
Manufacturing aware Pattern-matching

routing avoids litho
based detection of
hotspots
lithography limiting
layout patterns
Repair
ICC+ICV
Automatic repair and
revalidation of
matched layout
patterns
Fastest Path to Litho-Clean Design Closure

Synopsys 2010
25
In-Design PV Pattern-Matching
Match
Patented Technology Enables Fast Litho Detection
Database-Driven
Pattern Matching
100K
10K
1K
100
30
25
20
15
10
5
0
10
Intelligent
Layout Filtering
Runtime (min)
Automated
Pattern Capture
Num Patterns
Directly from OPC,

LRC or Simulation
Fast Identification of
Match Candidates
Zero Runtime Penalty

per Pattern
Qualified by GlobalFoundries for 28nm Process

Synopsys 2010
26
In-Design PV Auto Litho Repair
Repair
Smart Integration Eliminates Corner-Case Patterns
Highly Localized
Router-Driven
Incremental Validation
Full Property Visibility

Timing Aware
Proven Algorithms
Negligible Physical Impact
Highest Quality Final Layout
4-5x Faster Analysis
Eliminates Need for Manual Layout Fixes

Synopsys 2010
27
Results: Automatic Litho Repair

Customer Designs, 45/40nm
High Repair Rate
After
1214
1200
800
90%
600
400
200
457
85%
187
54
13
80%
617k
966k
2.4M
Design Instances
1000
25
20
100
15
10
10
5
0
1
617K
966K
28
2.4M
Design Instances
Hotspot Free in Minutes

Synopsys 2010
Patterns in DB
# Patterns
95%
1000
Repair
30
100%
Repair Rate
# Litho Hotspots
1400
Detection
Repair Rate
Runtime (min)
Before
Fast Runtime
Synopsys Solutions At 32/28nm

Summary
Variability
High accuracy
MCMM throughout the
flow
Manufacturing Compliance
Routing, Physical
Verification & Test
In-Design PV: Litho
Hotspot Prevention using
Pattern Matching
PrimeTime/StarRC
IC Validator
Galaxy
Design
Compiler
Low Power
Comprehensive flow
Low Power CTS
In-Design STA : Finalstage Leakage
Recovery
Design Complexity
IC
Compiler
Runtime speedup
40M+ design handling
Production proven across 32/28nm process nodes

Synopsys 2010
29
Thank You!
Synopsys 2010
Done
32/28nm Design Challenges
Done
Addressing 32/28nm Design

Challenges
Done
Fastest Time to Tapeout

with IC Validator
Done
Realizing Todays 32nm

and Beyond Large Designs
Done
Manufacturing-Aware
Routing
Done
Extraction For
32/28nm
Done
28nm Silicon And Design

Enablement
30
Predictable Success
To view other webinars in the 32/28nm webinar series:

http://www.synopsys.com/32-28nm-WebinarSeries
Synopsys 2010
31

28nm Silicon and Design Enablement The Foundry and EDA Vendor Perspective

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