ADCs for High-Speed Applications

David Nairn
Davi d.Nairn@Analog.corn
Analog Devices HSC
Greensboro NC

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ADCs for High-Speed Applications

ADC Concepts:

quantization
sampling

ADC Specifications:
static specifications
dynamic specifications

ADC Architectures:
classical architectures
"new" architectures

Summary

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ADC Concepts
Analog

Channel

time
continuous time
continuous amplitude

Digital

l)AC

Memory

DSP

time
discrete time
discrete values

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Quantization and Resolution

Quantization:
continuous amplitudes
represented with
discrete levels

100
ct 11
:Ek 10-

FS = Full Scale
LSB = Least Significant Bit

01 --

00
0

Resolution (1 LSB):

1/4 1/2

smallest noticeable change

3/4

'
1 = FS

Analog
V

LSB =

FS
2N

Converter Resolution = N

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Quantization
Noise & SNR
Quantization noise:

+1/2LSB

quantization errors
appear as noise with
an RMS level of
V

1 LSB

citw.4
-1/2LSB
114 1/2 314 1
Analog

LSB

= ,j12

Signal-to-Noise Ratio (SNR):

full scale sine wave Vsig =

2N VLs/3/ 2 "ii

SNR = 20log(V sig /Vv n ) = [6.02N + 1.76]dB

SNR 6NdB I

rig
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Notes for quantization noise:
Quantization noise can be calculated by assuming the
signal within any quantization step has a uniform distribution, as shown in the sketch to the right. The error
for a particular sample will simply be the distance
between x and the origin where -VLsB/2 < x < VLSB/2.
The rms error or the quantization noise can then be calculated as:

2 0

L S B /2

x2dx =

Vqn =

/2

SNR and Resolution: the Practical Case

Quantization is not the only noise source:
SNR = 2019g

vsig
liVq2 n+ Vn2

Ideal 12-bit
Ideal 10-bit
7 4dB

Real 12-bit
Real 10-bit

44,4.

A 62dB

1.

Noise (v1,)

=NI

Log
Scale

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SNR & Effective Number of Bits

Measuring SNR:
f i n < f s /2

ideal SNR

noise bandwidth = fs/2

SNR increases with the signal
ideal SNR
SNRmax = (6N + 1.76)dB

SNR

Effective Number of Bits:

Input Level Level (log scale)

ideally ENOB = N
circuit nonlinearities and
noise reduce ENOB to:

ENOB =

SNR

"1"

1.76

6.02

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Notes tor signal-to-noise:

The maximum SNR for an ideal N-bit ADC can be calculated by assuming the input is a
sine wave and the only noise source is quantization noise. The largest peak-to-peak value of the
sine wave is 2NVLSB which has an RMS value of 2NVLsB/2,j2 . Knowing the quantization noise
is VLsB/^r 1,

SNR = 20log

" /LsB/2,rn

(2 1

vLsB/ ,/ ,

which reduces to:

SNR = 6.02N + 1.76 dB

Solving the above equation for N, yields the effective number of bits from the maximum SNR

ENOB = (SNR. 1.76)/6.02

Sampling, Nyquist and Aliasing

A
Signal spectrum:

f B sir

original signal

Sampled
with fs> 2f Bw:

spectrum

baseband signal
.-*

772)Yx_
I

A
fs/2

is

Sampled
spectrum with fs< 2f Bw: baseband
aliased signal
signal

.6,

....h....
I

. .m.4...
...A..,
4,

- .

.4

4'

4):

1 ^

f5/2 fs fs

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Aliasing in the Time Domain

Output < fs/2

--; l/fs ;- signals beyond f s /2 are aliased to below f s/2

useful for down conversion from IF to baseband

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Sampling & Anti-Aliasing Filtering (ADCs)

Nyquist Criterion f,>2f

Bw

Ideal Case: fs = 2/B4V 1

filter = ideal brick wall
attenuation sufficient to suppress
out-of-band noise below 6NdB
f s /2

practical

r filter

0dB

IAI

J audio signal /
777(///////////

20kHz 22 kHz

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1. Strictly, there should be NO signal energy at half the sampling frequency

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Oversampling & Anti-Aliasing Filters

Oversampling eases filtering requirements:
simple analog filter
audio
signal

0dB

lAl

f BW

analog filter
digital filter
/2

high order digital filters can have

sharp transitions & linear phase

al

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Oversampling & Quantization Noise

Quantization noise is uniform between 0 and fs/2

fs

= 2/Bw

quantization
noise

fs = 8(2fBw

) :

lAl

signal
WII
IFIS
ner
4
/40' Al Fe/

quantization
noise
r/

fs/2

In-band SNR::
sAR = 6.02N+ 1.76 + 1010g

dB

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ADC Concepts
Summary
Quantization determines resolution:
smallest discernible step = 1 LSB
more bits = more resolution
SNR 6NdB

Sampling rate determines useful bandwidth:

2
fs > f B W
- Nyquist criterion
fs 2fBw

- eases analog filtering

S NR = [6N + 1.76 + 10log

fs

dB
2fBviji

rim
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Specifying ADCs
DC Specifications:
fs fcik

"optimal" specifications

Dynamic Specifications:
'Is - fak
indicates performance degradation for
high signal frequencies
"realistic" specifications

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DC Specifications
Clk
1

OUT

REF

rbn

Ideal output:

V OUT =

REFL

+ ' + 2N]

bn -1

MSB (most significant bit) =

- LSB (least significant bit) = bo
Full Scale input (or output) = V R E F [ 22N 11V R E F
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Ideal ADCs and DACs

Analog-to-Digital Converter

Digital-to-Analog Converter

100
0 11
71 0
-j 1
la

114 1/2 3/4

Analog In
levels are uniformly spaced:
1LSB =

01 10 11 100
Digital In
V

REF
2N

slope = 45, intercept =

origin
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Gain and Offset Errors

3-bit ADC example:
AV: Gain Error =
'410-11-;
AV + Vos

111

-5 110

101

:Et 011
010
001
000

Offset
Error

Analog In

REF

Offset Error: difference between zero intercept and the origin

- expressed in LSBs
Gain Error: difference between real and ideal slopes
- often expressed in LSBs from ideal full scale
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Linearity Errors
Differential Non-Linearity (DNL):
difference between
real & ideal step size
Integral Non-Linearity (INL):
difference between
step midpoint and
line joining end points

A
DNL > 0
DNL <
Missing
Code

100
011
010

Missing Codes:
excessive DNL leads to
missed codes in ADCs

001
000

Analog In

Non-Monotonicity:
excessive DNL leads to
non-monotonic behavior in ADCs
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Spurious Free Dynamic Range (SFDR)

INL, DNL and finite slew rates cause distortion

SFDR:
is a measure of

0dB

harmonic distortion
ideally SFDR > SNR

To Measure:
noise bandwidth
Al f 1 2

,c4

wide-band
noise
SFDR 6NdB
narrow
band
noise

input sine wave

fi n 1/2
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Signal-to-Noise and Distortion (SINAD)

SINAD:
noise and distortion degrade an ADC's performance

SINAD, SNR, THD (dB)

Sig

SINAD = 20log

,jVn(total) + THD2
THD
.

.
.

SINAD

SN R

Frequency
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ADC Bandwidth Specifications

Nyquist:
bandwidth = f s /2

Full Power BW (f3dB):

fundamental down 3dB
typicallyh db >1/2

Resolution BW (f RB ):
SINAD down 3dB
(1/2 bit = 3dB)
ideally f RBW fs/ 2

RBW

f3dB fin

f3dB & f RBW are usually independent of f s/2

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Sampling Errors (Jitter)

Jitter:
most systems assume the signal is sampled uniformly.
clock noise leads to non-uniform sampling (i.e. jitter).
Output uncertainty
or noise.

Sample time
variation due
to jitter.
leads to SNR degradation for high frequency inputs.

2nf a T i V p <

V LsB

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Notes for jitter:

Jitter introduces uncertainty in the sampling instant that leads to uncertainty in the sampled value resulting in a degradation in the SNR. The effects of jitter depend on the slope of the
signal at the sampling instant. A sine wave of frequency fa with a peak value of Vp can be
expressed as V p sin (2n f at) . The slope of this wave form at any time is given by:
av/at = 27c fa Vpcos (2rc fat)
The worst case slope occurs at t = 0 and is given by 27Ef aVp. If the sampling clock has an rms jitter of T- one can substitute for at to solve for the worst case av :
av = 27cfy p T i
A nominal target for av is to keep it below one LSB or

27tf Vp Ti <VLsB

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ADC Specification Summary

For true N-bit performance:
INL < -1LSB
DNL <
ENOB N
SFDR > 6NdB
f RBW > fs/ 2

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