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ISSI
DESCRIPTION
The ISSI IS62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-
A0-A14
DECODER
32K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CS
OE
CONTROL
CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc.
ISSI
IS62C256
PIN CONFIGURATION
PIN CONFIGURATION
28-Pin SOP
28-Pin TSOP
A14
28
VCC
A12
27
WE
A7
26
A13
A6
25
A8
A5
24
A9
A4
23
A11
A3
22
OE
A2
21
A10
A1
20
CS
A0
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
GND
14
15
I/O3
PIN DESCRIPTIONS
A0-A14
CS
OE
WE
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
TRUTH TABLE
Address Inputs
Output Enable Input
21
20
19
18
17
16
15
14
13
12
11
10
9
8
22
23
24
25
26
27
28
1
2
3
4
5
6
7
WE
CS
OE
I/O Operation
Vcc Current
High-Z
ISB1, ISB2
H
H
L
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
0.5 to +7.0
55 to +125
65 to +150
0.5
20
Unit
V
C
C
W
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
ISSI
IS62C256
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0C to +70C
40C to +85C
VCC
5V 10%
5V 10%
DC ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Test Conditions
VCC = Min., IOH = 1.0 mA
VCC = Min., IOL = 2.1 mA
Output Leakage
Com.
Ind.
Com.
Ind.
Min.
2.4
2.2
0.3
2
10
2
10
Max.
0.4
VCC + 0.5
0.8
2
10
2
10
Unit
V
V
V
V
A
A
Note:
1. VIL = 3.0V for pulse width less than 10 ns.
ISB2
Parameter
Vcc Operating
Supply Current
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
VCC = Max., CS = VIL
IOUT = 0 mA, f = 0
VCC = Max., CS = VIL
IOUT = 0 mA, f = fMAX
VCC = Max.,
VIN = VIH or VIL
CS VIH, f = 0
VCC = Max.,
CS VCC 0.2V,
VIN VCC 0.2V, or
VIN 0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
-45 ns
Min. Max.
60
70
70
80
5
10
0.5
1.0
-70 ns
Min. Max.
60
70
65
75
10
0.5
1.0
Unit
mA
mA
mA
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max.
8
10
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
ISSI
IS62C256
Parameter
VCC for retention of data
Data retention current
Data retention current
Test Conditions
Min.
2.0
Max.
200
200
Units
V
A
A
-45 ns
Min. Max.
Parameter
-70 ns
Min.
Max.
Unit
tRC
45
70
ns
tAA
45
70
ns
tOHA
ns
45
70
ns
25
35
ns
ns
20
25
ns
ns
20
25
ns
ns
30
50
ns
tACS
tDOE
tLZOE
(2)
tHZOE
(2)
tLZCS(2)
tHZCS(2)
tPU
(3)
tPD
(3)
CS Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CS to Low-Z Output
CS to High-Z Output
CS to Power-Up
CS to Power-Down
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480
5V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
Figure 1.
4
480
5V
255
5 pF
Including
jig and
scope
255
Figure 2.
ISSI
IS62C256
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
READ1.eps
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CS
t ACS
t HZCS
t LZCS
DOUT
HIGH-Z
DATA VALID
CS_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS = VIL.
3. Address is valid prior to or coincident with CS LOW transitions.
ISSI
IS62C256
-45 ns
Min. Max.
Parameter
-70ns
Min.
Max.
Unit
tWC
45
70
ns
tSCS
CS to Write End
35
60
ns
tAW
25
60
ns
tHA
ns
ns
tPWE
WE Pulse Width
25
55
ns
tSD
20
30
ns
tHD
ns
tSA
(4)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS Controlled, OE is HIGH or LOW) (1 )
t WC
VALID ADDRESS
ADDRESS
t SA
t SCS
t HA
CS
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CS_WR1.eps
ISSI
IS62C256
AC WAVEFORMS
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CS
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CS_WR2.eps
VALID ADDRESS
OE
LOW
CS
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
t HZWE
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CS_WR3.eps
Notes:
1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
ISSI
IS62C256
ORDERING INFORMATION
Commerical Range: 0C to +70C
ORDERING INFORMATION
Industrial Range: 40C to +85C
Speed
(ns)
Speed
(ns)
Package
45
IS62C256-45T
IS62C256-45U
TSOP
Plastic SOP
70
IS62C256-70T
IS62C256-70U
TSOP
Plastic SOP
Package
45
IS62C256-45TI
IS62C256-45UI
TSOP
Plastic SOP
70
IS62C256-70TI
IS62C256-70UI
TSOP
Plastic SOP
ISSI