2 3

Takeshi Miyajima, Aldec Japan K.K.
Agenda
Aldec Overview
Co-verification with algorithm and system
development environment
(simulator and actual hardware)
Documentation and graphical design entry
Functional verification with simulator and hardware
assisted environment
Utilization of RTAX/RTSX prototyping board
www.aldec.com/jp
2012 Aldec, Inc. Company Confidential.
Aldec Overview
Founded 1984
Privately Held, Profitable
Employees 190+
Over 34,000 Licenses Worldwide
Several Key Technology Patents
Markets Segments:
www.aldec.com/jp
Military/Defense
Aerospace
Telecommunications
Safety Critical (Avionics/Nuclear/Automotive/Rail)
Industrial
www.aldec.com/jp
www.aldec.com/jp
Customers
Market/Product Roadmap
VHDL and Verilog
Design Entry,
Requirements
Traceability and
Simulation
Active-HDL
Riviera-PRO
ALINT
Functional
Verification
SystemVerilog,
HDLs, PSL
ABV, UVM, FC,

Constrained
Randomization,
HW Acceleration
Riviera-PRO
HES-DVM
Platform
Validation
System Hardware
and Software covalidation
Emulation, HW
Prototyping and
Virtual Platforms
HES-DVM
HES-7
RTAX/RTSX
www.aldec.com/jp
Design/
Simulation
Design/
Simulation
VHDL and Verilog
Design Entry,
Requirements
Traceability and
Simulation
Active-HDL
Riviera-PRO
ALINT
Target Customer
FPGA graphical design entry and HDL simulation
Tests are FPGA and Unit level to validate the RTL code
Mapping Design Requirements to the HDL code and System Level
HDL Code quality checking (linting)
Typical Designs
VHDL, Verilog or Mixed (Text or Graphical)
www.aldec.com/jp
IP Cores or FPGA system
Software
(C/C++)Programmer
Hardware
(HDL)Designer
Functional
Verification
SystemVerilog,
HDLs, PSL
ABV, UVM, FC,

Constrained
Randomization,
HW Acceleration,
Riviera-PRO
HES-DVM
Target Customer
System Level Testing batch and GUI modes
Functional Verification Assertions
Functional Coverage (FC) with Constrained Randomization (CR)
Hardware-assisted Verification (RTL Acceleration - HW in the Loop)
Typical Designs
VHDL, Verilog testbench

SystemVerilog testbench with CR and FC
www.aldec.com/jp
UVM, OVM and VMM

OS-VVM for VHDL
Assertions based triggers
FPGA and ASIC
Software
(C/C++)Programmer
Hardware
(HDL)Designer
Platform
Validation
Hardware and
Software covalidation
Emulation,
Prototyping and
Virtual Platforms
HES-DVM
HES-7
RTAX/RTSX
Target Customer
System Integrators and Firmware engineers
Require At-Speed Prototyping (real time inputs, MHz requirements,
Virtual platforms and processors)

C/C++ designers seeking early access to the HW Design
Typical Design
SoC (processor based)

ASIC
www.aldec.com/jp
Space
Software
(C/C++)Programmer
Hardware
(HDL)Designer
10
Vertical Markets
Compliance/
www.aldec.com/jp
Standards
Avionics
(DO254/ED80)
Nuclear
(IEC61508)
Automotive
Rail Roads
Prototyping
ASIC
(Virtex7/2000Ts
Boards)
Space
(RTAX/RTSX
Adaptors)
Services
SCEMI
Transactors
Customer
Design
UVM/HDL
Training
11
Design and Verification Flow

System
Specification
MATLAB
Production
System
Partitioning
VHDL/Verilog HDL
System
Validation
C/C++
System
Integration
www.aldec.com/jp
Simulation
FPGA Compile
ASM
FPGA
Prototyping
12
Co-verification with algorithm and system

development environment
System
Specification
MATLAB
Production
System
Partitioning
VHDL/Verilog HDL
System
Validation
C/C++
System
Integration
www.aldec.com/jp
Simulation
FPGA Compile
ASM
FPGA
Prototyping
13
Aldec provide 3 types MATLAB interface

MATLAB direct interface
Run MATLAB from AHDL/RPRO
MATLAB
www.aldec.com/jp
Simulink
MATLAB to
Hardware in loop test
PCI-Driver
HES-API
MATLAB-API
Run AHDL/RPRO from Simulink
Simulink interface
14
Simulink interface
Compare simulation result of HDL

design accuracy in Simulink
environment
Ability to analysis and visualization
of simulation result in Simulink
Direct connection to Synplify DSP
and Xilinx System Generator blocks
Test of HDL source generated from
both tools
www.aldec.com/jp
Generate testbench for standalone

HDL simulation
15
Simulink interface use case
Rich Simulink libraries to generate input stimulus and

testbench for HDL block
Compare, Analysis and visualization of each simulation results
Reuse HDL source to Simulink block
Compare Simulink floating point operation
vs. FPGA hardware fixed point operation
Control HDL simulation run/stop at Simulink environment
Reuse test vectors generated by Simulink for standalone HDL
simulation
www.aldec.com/jp
Automatic rerun by batch file, when HDL source code changed
16
MATLAB direct Interface
Exchange of scalar and array data between RivieraPRO/Active-HDL MATLAB

Visualization of HDL Simulation
www.aldec.com/jp
(statistics/Spectrum analysis)
Generate complex stimulus
for HDL testbench
Described high level abstraction
for a part of design unit
Post-processing by MATLAB
after HDL simulation
Provide VHDL procedure and Verilog function for

MATLAB direct Interface
17
MATLAB direct Interface use case
Call MATLAB m file from HDL testbench

Create complex input data/stimulus
Display and analysis in MATLAB for output

Analog/Image/Video data
Use MALTLAB model instead of HDL model
Run System Level Simulation before HDL creation
Available rich HDL debug features
www.aldec.com/jp
Assertion, code coverage, Waveform
18
MATLAB Hardware in Loop Test

MATLAB as testbench for FPGA Prototyping
Hardware Board
MATLAB files
wrappers
C/C++
low level API
SW/HW
Algorithm
Wrapper
in FPGA
DUT and TB
Computing intensive algorithm implemented in the FPGA (running at MHz)
MATLAB works as a testbench
INTERFACE
www.aldec.com/jp
MATLAB files wrappers for HES-Proto API
BENEFITS
RTL IP (VHDL/Verilog) acceleration in FPGA while the rest of the system is
simulated in MATLAB
Early prototype validation in FPGA with power of MATLAB
19
MATLAB Hardware in Loop Test use case
www.aldec.com/jp
Fastest HDL Simulation

Direct test vector input from MATLAB to FPGA
Accessible FPGA board(PCIe) on PC via network
Quickly change FPGA design by bit data download
Hardware in Loot Test for high reliability apprications
20

System
Specification
MATLAB
Production
System
Partitioning
VHDL/Verilog HDL
System
Validation
C/C++
System
Integration
www.aldec.com/jp
Simulation
FPGA Compile
ASM
FPGA
Prototyping
21

VISUALIZE
Abstract design intelligence and convert it to schematic.
Create a textual and graphical representation of your
workspace or design.
LEARN
Design status report collect detailed information about a user
workstation, design, libraries, statistics of line count, flow
manager settings, synthesis and/or implementation results
www.aldec.com/jp
SHARE
Auto-generate HTML & PDF documentation with all the design
details. Export waveform to graphics for easy sharing between
peers
22
Design Documentation
www.aldec.com/jp
Entire workspace, individual

designs or files can be printed
or exported to vector PDF
The HTML document closely
Resembles Active-HDL
environment layout
Vector graphics and other
advanced PDF options
available
Graphical Design Entry
documents can be
accompanied by generated
code
Ideal solution for design
documentation
23
Code2Graphics
Converts HDL code into graphical representation:

Block Diagrams
Finite Sate Machine
Editor files
www.aldec.com/jp
Creates perfect documentation for HDL

designs
Helps with debugging of large designs
24
Block Diagram Editor
www.aldec.com/jp
Multi-page hierarchical
block diagrams
Multidimensional arrays and
record signals supported
Bottom-up and top-down
design methodologies
supported
Allows mixed structural and
behavioral elements
Cross probing with
generated code
Handles mixed HDL designs
Customizable design rules
checking
Imports schematics
Customizable symbols
25
Finite State Machine Editor
www.aldec.com/jp
Multiple State Machines on

a single diagram
Full-Moore machines
support
Hierarchical states and
junctions provided for
legibility
Delay states simplify control
of machine timing
Advanced code generation
settings
Automatic testbench
generation
www.aldec.com/jp
26
Active-HDL FPGA Vendor-Independent IDE
27
Functional verification with simulator and

hardware assisted environment
System
Specification
MATLAB
Production
System
Partitioning
VHDL/Verilog HDL
System
Validation
C/C++
System
Integration
www.aldec.com/jp
Simulation
FPGA Compile
ASM
FPGA
Prototyping
28
Traditional Hardware Verification
Traditional Hardware Verification

Real-time data is streaming through the design inputs
Design outputs (FPGA) are connected to other components
on the board
No test headers on the FPGA I/Os
FPGA
www.aldec.com/jp
Test
Vectors
DSP
uP
RAM
Board Under Test
29
Traditional Hardware
Verification Challenges
www.aldec.com/jp
Ensuring RTL and Hardware

simulation results match
Development of input data to
cover all the design requirements
(time!)
Limited visibility and
controllability on the FPGA I/Os
Preserving documentation of
results
How to automate the testing
environment for many test cases?
30
FPGA Level Verification with

DO-254 CTS
www.aldec.com/jp
At-speed verification in the target device

Reusing testbench as test vectors for
in-target testing
No changes in the design and testbench
FPGA design and verification can be
performed immediately without the final
board
Robustness testing is simplified. The DUT
can be exercised with stimuli that might
not be possible to re-create in the target
board
Easy results capturing, analysis and
documentation
31
DO-254 CTS Components

DO-254 CTS CVT (Software)
COTS Mother Board
Converts final testbench into test vectors

Controls In-Hardware Verification
Writes hardware results to a waveform file
Provides test vectors into daughter board

at speed
1-environment to test all FPGA requirements
Samples FPGA outputs at speed
PCI/e interface to PC
www.aldec.com/jp
Customized Daughter Board

FPGA level verification
Customized to target FPGA and DUT
Contains target FPGA and DUT
32
Traditional Hardware Testing Methods

vs. DO-254 CTS
Traditional Hardware
Verification
Input Type
Real Data
RTL Test Vectors
Verification Type
At Speed
At Speed
Target Device
Yes
Yes
Test Data Generation
Manual engineering time required
Automatic, no additional development

required
PCIe based Hardware Boards
Test Environment Setup Manual connections of wires and

cables
FPGA I/O Access
Limited controllability
www.aldec.com/jp
Aldecs DO-254 CTS

Approach
Complete controllability and visibility
Output Format
From Logic Analyzer, Oscilloscope
RTL Simulator Waveform Format
RTL and Hardware

Results Comparison
Result Documentation
Limited
Easy and automated
Manual documentation
Automatically generated waveform

and PDF export
Manual Process and takes months to

complete, thus development cost is
very high
Automated process and only takes

weeks to complete, thus development
cost is reduced substantially
FPGA Device
Verification Time
33
Aldecs Additional DO-254 Solutions

Active-HDL
RTL Design and Simulation
ALINT
www.aldec.com/jp
Design Rule Checking
Code Coverage
Tool Qualification
Package
Common-Kernel Mixed Language Simulator

VHDL 2008
Graphical Entry - Block Diagram and State Machine
Coverage and Assertions
DO-254 Best Practice HDL Design Rules

Custom Rules creation
Tracking, Results Analysis, Reporting
Design and library management
Tool Qualification Package for Active-HDL Code

Coverage
Including Test Cases and Documentation (Tool
Operational Requirements, Tool Test Plan, etc)
34

System
Specification
MATLAB
Production
System
Partitioning
VHDL/Verilog HDL
System
Validation
C/C++
System
Integration
www.aldec.com/jp
Simulation
FPGA Compile
ASM
FPGA
Prototyping
35
HES-7 ASIC Prototyping
HES-7 with Virtex-7

Utilizes industrys largest FPGAs V7 2000ts
Dual HES-7 can accommodate up to 24m ASIC gates!
Using a conservative 6x logic cell to ASIC gate conversion
Competition has over-inflated capacity we use the same FPGAs
Offers scalable configuration and flexible expansion
With four single-board capacity product configurations
4m to 24m ASIC gates
Using non-proprietary backplane connector for expansion to:

Daughter boards
Multi-HES-7 boards (expands capacity to 96m ASIC gates)
www.aldec.com/jp
Aggressive product prices

Reduces design partitioning
2 FPGAs can be used instead of 6 FPGAs
Which produces higher performing designs
Enables lower cost of bring-up effort
www.aldec.com/jp
36
HES-7 Top View
37
HES-7 Bottom View
www.aldec.com/jp
JTAG
Connector
Micro SD
Socket
SO-DIMM DDR3
Memory Socket
38
www.aldec.com/jp
Ability to prototype RTAX-S/SL and RTSX-SU designs using reprogrammable Microsemi Flash ProASIC3E FPGA family chips
Adaptor board is footprint-compatible with the final RTAX-S/SL
and RTSX-SU device
Programming connector (JTAG) allows on-the-fly
reprogramming of the device without detaching the adaptor
from the target PCB
EDIF netlist converter allows to migrate from RTAX-S/SL and
RTSX-SU to ProASIC 3E FPGA easily
Design efficiency is achieved, saving Development Time and
Costs
39
Aldec Complementary Design Flow

Create and Verify
Design Code
Synthesize and Implement for
ProASIC3 FPGA
Test in Hardware:
Results OK?
No throwaways!
Modify and Verify

Design Code
www.aldec.com/jp
Synthesize and Implement for

flight FPGA
Final Hardware Tests
Preferred flow for

PURE HDL Designs
40
Sample RTAX-S/SL Adaptor Board

A3PE3000-FGG896
Microsemi ProASIC3E FPGA
JTAG Connector
www.aldec.com/jp
Capacitors
Ball grid array that mimics

CG624 package
ACT-H3K-CG624 Adaptor
Adaptor size: 32.5mm x 34mm
The following elements reside on
the top part of the adaptor
device,
A3PE3000-FGG896
(or A3PE3000-2FGG896I)
JTAG connector
Capacitors, resistors
The following elements reside on

the bottom part of the adaptor
Leads that mimic CG624 package
41
Sample RTSX-SU Adaptor

Mother Board of ACT-RTSX-CQ256 adaptor:
www.aldec.com/jp
Top side with visible Microsemi ProASIC3E device

(A3PE600-FGG484 or A3PE600-2FGG484I)
Bottom side with leads mimicking CQ256 package
Mother board and daughter board
of ACT-RTSX-CQ256 adaptor in stacked configuration
42
Available Adaptors
www.aldec.com/jp
ALDEC is constantly extending the assortment of adaptors

RTAX-S/SL adaptor boards are available in the following
footprint layouts:
Commercial grade:
Industrial grade:
CQ208, CQ256, CQ352, CG624, CG1272

CQ208, CQ256, CQ352, CG624
Commercial grade:
Industrial grade:
CQ208, CQ256, CG624

CQ208, CQ256, CG624
RTSX-SU adaptors are available in the following footprints:

Save Development Time Re-Programmability
Footprint compatible adaptors
Customer proven with over 300 units shipped worldwide
43
Summary
System
Specification
Aldec fill in the gap for

Radiation Tolerant FPGA design
MATLAB
Production
System
Partitioning
VHDL/Verilog HDL
System
Validation
C/C++
System
Integration
www.aldec.com/jp
Simulation
FPGA Compile
ASM
FPGA
Prototyping
44
Q&A
Aldec Japan K.K.
Stella Shinjuku 7F
2-1-9 Shinjuku, Shinjuku-ku, Tokyo, Japan
+81-3-5312-1791
sales-jp@aldec.com
N. America
Europe
Israel
Japan
China
India
Taiwan
sales@aldec.com
sales-eu@aldec.com
sales-il@aldec.com
sales-jp@aldec.com
Riviera-PRO
Advanced Verification Platform
Active-HDL
FPGA Design and Simulation
ALINT
Design Rule Checking
HES
Hardware Emulation Solutions
info@aldec.com.cn
sales-in@aldec.com
sales-tw@aldec.com
DO-254/CTS
www.aldec.com/jp
HES-7
FPGA Level In-Target Testing
www.aldec.com/jp
ASIC Prototyping
www.youtube.com/AldecInc
www.twitter.com/Aldec_Japan
Microsemi Prototyping
RTAX/RTSX

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Takeshi Miyajima, Aldec Japan K.K.

2012 Aldec, Inc. Company Confidential.

Privately Held, Profitable

Over 34,000 Licenses Worldwide

Several Key Technology Patents

2012 Aldec, Inc. Company Confidential.

2012 Aldec, Inc. Company Confidential.

VHDL and Verilog

ABV, UVM, FC,

2012 Aldec, Inc. Company Confidential.

VHDL and Verilog

VHDL, Verilog or Mixed (Text or Graphical)

IP Cores or FPGA system

2012 Aldec, Inc. Company Confidential.

ABV, UVM, FC,

VHDL, Verilog testbench

UVM, OVM and VMM

Virtual platforms and processors)

SoC (processor based)

2012 Aldec, Inc. Company Confidential.

2012 Aldec, Inc. Company Confidential.

Design and Verification Flow

Co-verification with algorithm and system

Aldec provide 3 types MATLAB interface

Run AHDL/RPRO from Simulink

Compare simulation result of HDL

2012 Aldec, Inc. Company Confidential.

Generate testbench for standalone

Simulink interface use case

Rich Simulink libraries to generate input stimulus and

Automatic rerun by batch file, when HDL source code changed

2012 Aldec, Inc. Company Confidential.

MATLAB direct Interface

Exchange of scalar and array data between RivieraPRO/Active-HDL MATLAB

Provide VHDL procedure and Verilog function for

2012 Aldec, Inc. Company Confidential.

MATLAB direct Interface use case

Call MATLAB m file from HDL testbench

Display and analysis in MATLAB for output

Run System Level Simulation before HDL creation

Available rich HDL debug features

Assertion, code coverage, Waveform

2012 Aldec, Inc. Company Confidential.

MATLAB Hardware in Loop Test

MATLAB files wrappers for HES-Proto API

RTL IP (VHDL/Verilog) acceleration in FPGA while the rest of the system is

MATLAB Hardware in Loop Test use case

Fastest HDL Simulation

2012 Aldec, Inc. Company Confidential.

Documentation and graphical design entry

Documentation and graphical design entry

2012 Aldec, Inc. Company Confidential.

Entire workspace, individual

2012 Aldec, Inc. Company Confidential.

Converts HDL code into graphical representation:

Creates perfect documentation for HDL

2012 Aldec, Inc. Company Confidential.

Block Diagram Editor

2012 Aldec, Inc. Company Confidential.

Finite State Machine Editor

Multiple State Machines on

2012 Aldec, Inc. Company Confidential.

Active-HDL FPGA Vendor-Independent IDE