Ganged CMOS Logic

Figure illustrates pairs of CMOS inverters ganged together. The truth table is given in table 6.1, shows
that the pair computes the NOR function. Such a circuit is referred to as Ganged CMOS. When one input
is 0 and the other 1, the gate can be viewed as a pseudo-nMOS circuit with appropriate ratio
constraints. When both inputs are 0, both pMOS transistors turn on; pulling the output high faster
than they would in an ordinary pseudo-nMOS gate. Moreover, when both inputs are 1, both pMOS
transistors are OFF, saving static power dissipation.. As in pseudo-nMOS, the transistors are sized so the
pMOS are about the strength of the nMOS and the pull-down current matches that of a unit inverter.
Hence, the symmetric NOR achieves both better performance and lower power dissipation than a 2input pseudo-nMOS NOR.
Table 6.1 operation of symmetric NOR
A
0
0
1
1

B
0
1
0
1

N1
OFF
OFF
ON
ON

P1
ON
ON
OFF
OFF

N2
OFF
ON
OFF
ON

P2
ON
OFF
ON
OFF

Y
1
~0
~0
0

5.6.3 Differential Pass Transistor Logic

For high performance design, a differential pass transistor logic family, called CPL or DPL, is
commonly used. The basic idea (similar to DCVSL) is to accept true and complementary inputs
and produce true and complementary outputs. A number of CPL gates (AND/NAND, OR/NOR,
and XOR/NXOR) are shown in Figure 5.13. These gates possess a number of interesting
properties:

Since the circuits are differential, complementary data inputs and outputs are always
available. Although generating the differential signals requires extra circuitry, the
differential style has the advantage that some complex gates such as XORs and adders
can be realized efficiently with a small number of transistors. Furthermore, the
availability of both polarities of every signal eliminates the need for extra inverters, as is
often the case in static CMOS or pseudo-NMOS.

CPL belongs to the class of static gates, because the output-defining nodes are always
connected to either VDD or GND through a low resistance path. This is advantageous for
the noise resilience.
The design is very modular. In effect, all gates use exactly the same topology. Only the
inputs are permutated. This makes the design of a library of gates very simple.

More complex gates can be built by cascading the standard pass-transistor modules.

5.9.1 Calculation of output voltage through a single nFET :

Suppose that VDD = 5V and VTn = 0.7V. Find the output voltage Vout of the single nFET pass
transistor in the figure 5.26 for the following input voltage values (a) V in = 2V (b) Vin = 4.5V (c)
Vin = 3.5V (d) Vin = 0.7V
.
Figure 5.26. A single nFET pass transistor.
The nFET can pass any voltage in the range [0,Vmax], where
Vmax = (VG VTn ),where VG is the gate voltage. For the given
values Vmax = 5 0.7 = 4.3V. If Vin > Vmax then Vout is
restricted to Vmax. However, the nFET passes any voltage Vin
< Vmax. Hence we can find the output voltages for given data
a) Vin = 2V we have Vout = 2V
b) Vin = 4.5V we have Vout = 4.3V is limited
c) Vin = 3.5V we have Vout = 3.5V

d) Vin = 0.7V we have Vout = 0.7V

The main idea is to show the effect of threshold loss through an nFET.
5.9.2 Calculation of output voltage through cascaded nFETs :
Consider the two nFET chain in figure 5.27. The power supply is set to a value of V DD = 3.3V and
the nFET threshold voltage is VTn = 0.55V. Find the output voltage Vout at the right side of the
chain for the following values (a) Vin = 2.9V (b) Vin = 3.0V (c) Vin = 1.4V (d) Vin = 3.1V.

Figure 5.27. nFET pass transistor chain.

If Vin < Vmax , then the input voltage is
transmitted through the chain, then a
threshold drop occurs in the first
transistor(only) and Vmax makes it to the
output. With the given values Vmax = 3.3
0.55 = 2.75V Hence we get the following
a)
b)
c)
d)

Vin = 2.9V we have Vout = 2.75V is limited

Vin = 3.0V we have Vout = 2.75V is limited
Vin = 1.4V we have Vout = 1.4V
Vin = 3.1V we have Vout = 2.75V is limited

5.9.2 Calculation of output voltage through nFETs

The output of an nFET is used to drive the gate of another nFET shown in figure 5.28. Assume
that VDD = 3.3Vand VTn = 0.60V.Find the output voltage Vout.When the input voltages are at the
following values. (a) Va =3.3V and Vb =3.3V
(b) Va = 0.5V and Vb = 3.0 V (c) Va = 2.0V and
Vb = 2.5 V (d) Va = 3.30V and Vb = 1.8 V
Figure 5.28. nFET pass transistor.
The output of the upper FET M1 (with Va
applied)is used to control the gate voltage
VG of the lower transistor M2 (with Vb
applied). Both are susceptible to threshold

voltage drops so that VG = (VDD - VTn) and max Vout = (VG - VTn). Using maxVG = 3.3- 0.6 = 2.7V
gives trhe following results.
a) Va =3.3V and Vb =3.3V, VG = 3.3- 0.6 = 2.7V, Vout = 2.7 0.6 = 2.1V
b) Va = 0.5V and Vb = 3.0 V VG = 0.5 so M2 is in cut off. This makes Vout = HiZ an unknopwn
value since the transistor is an open circuit.
c) Va = 2.0V and Vb = 2.5 V VG = 2.0V, Vout = 2.0 0.6 = 1.4V
d) Va = 3.30V and Vb = 1.8 V VG = 2.7V, Vout = 1.8V