Chapter 1

Introduction

Recently, the number of individuals and organizations using wide computer

networks for personal and professional activities has increased a lot. Among them,
there are several applications highly sensitive to data security such as commercial
exchange on the Internet and smart cards. A cryptographic algorithm is an essential
part in network security. A well-known cryptographic algorithm is the Data
Encryption Standard (DES), Cryptography is the art of keeping data secure from
unauthorized access so as to guarantee that only the intended users can access it.
As computer technologies are getting advanced, more and more cryptographic
applications are used. They are mainly used to support other applications which are
very much sensitive to data security such as smart cards and commercial data
exchange over a network. Not only for personal use but cryptographic algorithms
are also very important in every aspect of professional activities. Symmetric-key
cryptography refers to encryption methods in which both the sender and receiver
share the same key (or, less commonly, in which their keys are different, but
related in an easily computable way).

Chapter 2
Literature Review

Sourav Mukherjee and Bibhudatta Sahoo, A Hardware implementation of

IDEA cryptosystem using a recursive multiplication approach., International
Conference on Electronic Systems (ICES-2011), pp 383 - 389, 2011,
This paper covers the implementation of the International Data Encryption Algorithm (IDEA)
using Very Large Scale Integrated Circuits Hardware Description Language (VHDL) with the
help of Xilinx ISE 10.1. In terms of security, This algorithm is very much superior and is
already patented by Ascom. The whole algorithm is divided into modules and among all of
them the most time consuming one is the modulo multiplication module.

Modugu.R,

Yong-Bin

Kim,

Minsu

Choi,Design

and

performance

measurement of efficient IDEA crypto-hardware using novel modular

arithmetic components, Instrumentation and Measurement Technology
Conference (I2MTC), 2010 IEEE, 3-6 May2010,pp1222-1227.
Cryptographic algorithms such as International Data Encryption Algorithm (IDEA) have
found various applications in secure transmission of the data in networked instrumentation
and distributed measurement systems. Modulo 2n +1 multiplier and squarer play a pivotal role
in the implementation of such crypto-algorithms. In this work, an efficient hardware design of
the IDEA (International Data Encryption Algorithm) using novel modulo 2n + 1 multiplier
and squarer as the basic modules is proposed for faster, smaller and low-power IDEA
hardware circuits.

 Antti Hamalainen, Matti Tommiska, and Jorma Skytt, 6.78 Gigabits per
Second Implementation of the IDEA Cryptographic Algorithm, 2002
Springer-Verlag, pages 760-769.
IDEA (International Data Encryption Algorithm) is one of the strongest secret-key block
ciphers. The algorithm processes data in 16-bit sub blocks and can be fully pipelined. The
implementation of a fully pipelined IDEA algorithm achieves a clock rate of 105.9 MHz on
Xilinx XCV1000E-6BG560 FPGA of the Virtex-E device family. The implementation uses
18105 logic cells and achieves a throughput of 6.78 Gbps with a latency of 132clock cycles.

Somayeh Timarchi, Keivan Navi, Improved Modulo 2n +1 Adder Design,

International Journal of Computer and Information Engineering 2:7 2008.
Efficient modulo 2n+1 adders are important for several applications including residue number
system, digital signal processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented number system. The
proposed approach is introduced for the reduction of the power dissipated. In a conventional
modulo 2n+1 adder, all operands have (n+1)-bit length.

Rahul Ranjan and I. Poonguzhali, VLSI Implementation of IDEA

Encryption Algorithm, Mobile and Pervasive Computing (CoMPC2008).
This paper describes VLSI implementation of IDEA encryption algorithm. In this
implementation, modulus multiplier is optimized and the temporal parallelism available in
IDEA algorithm is exploited. The implementation of inverse modulo (2^n+1) multiplier
design using a novel realization of the power algorithm for Eulers theorem results in the fast
inverse modulo multiplier. A multiplier including Wallace tree compressors and carry look
ahead adder is used which allow very high throughputs in pipelined Implementations. In it,
the sub-keys are generated internally.

Chapter 3
Proposed Methodology

In the presented research, Improved Modulo (2n + 1) Multiplier with radix-8 Booth recoding
is applied to International Data Encryption Algorithm

The modulo multiplier saves more time and area.

The proposed design enables IDEA to be implemented on hardware with high

performance and low cost.

The number of partial products generated in less than n/2 for n bit multiplication, thereby
reducing the number of intermediate addition operations.

Chapter 4
Platform Used

Altera Quartus
Altera Quartus is a programmable logic device design software from Altera. Its features
include:

An implementation of VHDL & Verilog for hardware description.

Visual edition of logic circuits.

Vector waveform simulation.

Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs,
which enables the developer to compile their designs, perform timing analysis, examine RTL
diagrams, simulate a design's reaction to different stimuli, and configure the target device
with the programmer. The latest version (January 2011) is 10.1.

Chapter 5
Expected Output

The proposed structure is

saves more time and area.

high performance and low cost.

less than n/2 for n bit multiplication, thereby reducing the number of intermediate
addition operations.

Chapter 6
References

1. Sourav Mukherjee and Bibhudatta Sahoo, A Hardware implementation of IDEA

cryptosystem using a recursive multiplication approach., International Conference on
Electronic Systems (ICES-2011), pp 383 - 389, 2011,

2. Modugu.R, Yong-Bin Kim, Minsu Choi,Design and performance measurement of

efficient IDEA crypto-hardware using novel modular arithmetic components,
Instrumentation and Measurement Technology Conference (I2MTC), 2010 IEEE, 3-6
May2010,pp1222-1227.
3. Rahul Ranjan and I. Poonguzhali, VLSI Implementation of IDEA Encryption
Algorithm, Mobile and Pervasive Computing (CoMPC2008).
4. Somayeh Timarchi, Keivan Navi, Improved Modulo 2n +1 Adder Design, International
Journal of Computer and Information Engineering 2:7 2008.
5. Antti Hamalainen, Matti Tommiska, and Jorma Skytt, 6.78 Gigabits per Second
Implementation of the IDEA Cryptographic Algorithm, 2002 Springer-Verlag, pages
760-769.