KALASALINGAM UNIVERSITY

(Kalasalingam Academy of Research and Education)

CURRICULUM AND SYLLABUS

REGULATIONS 2011
M. Tech. VLSI DESIGN
(4 Semesters)

KALASALINGAM UNIVERSITY
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT
KRISHNANKOIL 626 126

M. Tech. VLSI DESIGN

REGULATIONS 2011

KALASALINGAM UNIVERSITY
(Kalasalingam Academy of Research and Education)
ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT
M. Tech. (VLSI DESIGN)
CURRICULUM
I SEMESTER
Code
ECE5121
ECE5122
ECE5123
ECE5124
ECE5125
ECE51XX
ECE5183

Course Name
VLSI Design Techniques
VLSI Technology
Analog Design
Digital Design
Modelling and Synthesis with Verilog HDL
Elective I
HDL Programming and EDA Tools Laboratory
Total

L
4
3
3
3
3
3
0
19

T
0
0
0
0
0
0
0
0

P
0
0
0
0
0
0
3
3

C
4
3
3
3
3
3
2
21

II SEMESTER
Code
ECE5126
ECE5127
ECE5128
ECE5129
ECE51XX
ECE51XX

Course Name
Low power VLSI Design
Advanced Digital Design
Analog and Mixed Signal Design
ASIC Design
Elective II
Elective III

L
3
3
3
4
3
3

T
0
0
0
0
0
0

P
0
0
0
0
0
0
3*
(6)
3

C
3
3
3
4
3
3

ECE5184

VLSI Physical Design Laboratory

Total

19

Total

L
3
3
3
0
9

T
0
0
0
0
0

P
0
0
0
18
18

C
3
3
3
6
15

Total

L
0
9

T
0
0

P
30
30

C
10
10

2
21

III SEMESTER
Code
ECE6111
ECE611X
ECE611X
ECE6196

Course Name

Testing of VLSI Circuits

Elective IV
Elective V
Project Phase I
IV Semester

Code
ECE6197

Course Name
Project Phase II

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 2 of 37

M. Tech. VLSI DESIGN

REGULATIONS 2011
TOTAL CREDITS: 67

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 3 of 37

M. Tech. VLSI DESIGN

REGULATIONS 2011

LIST OF ELECTIVES
ELECTIVE I
Code
ECE5130
ECE5131
ECE5132
ECE5133

Course Name
VHDL Analysis and Design of Digital Systems
Electronic Design Automation Tools
Scripting Languages for VLSI Design Automation
Physical Design of VLSI Circuits
ELECTIVE II

L
3
3
3
3

T
0
0
0
0

P
0
0
0
0

C
3
3
3
3

Code
ECE5134
ECE5135
ECE5136
ECE5137

Course Name
CAD for VLSI Circuits
FPGA Based System Design
Genetic Algorithms and its Applications
Optimization Methods for Engineering Design
ELECTIVE III

L
3
3
3
3

T
0
0
0
0

P
0
0
0
0

C
3
3
3
3

Code
ECE5138
ECE5139
ECE5140
ECE5141

Course Name
Advanced Microprocessors and Microcontrollers
DSP Architecture
Advanced Computer Architecture
Video and Audio Processing
ELECTIVE IV

L
3
3
3
3

T
0
0
0
0

P
0
0
0
0

C
3
3
3
3

Course Name
RF Microelectronics Chip design
System-on-chip Design
RF MEMES
Embedded Systems
ELECTIVE V

L
3
3
3
3

T
0
0
0
0

P
0
0
0
0

C
3
3
3
3

L
3
3
3
3

T
0
0
0
0

P
0
0
0
0

C
3
3
3
3

Code
ECE6112
ECE6113
DCN CODE
ECE6115

Code
ECE6116
ECE6117
ECE6118
ECE6119

Course Name

Nano Electronics
EMI and Compatibility in System Design
VLSI Signal Processing
VLSI Circuit Design Methodology

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 4 of 37

M. Tech. VLSI DESIGN

REGULATIONS 2011

KALASALINGAM UNIVERSITY
(Kalasalingam Academy of Research and Education)
Electronics and Communication Engineering Department

M. Tech. (VLSI DESIGN)

SYLLABUS

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 5 of 37

M. Tech. VLSI DESIGN

ECE5121

REGULATIONS 2011

VLSI DESIGN TECHNIQUES

CMOS CIRCUITS FUNDAMENTALS

MOS transistors, CMOS Logic, VLSI design flow, Circuit and System Representations, MOS transistor
theory-Introduction, MOS Device design equations Ideal I-V Characteristics, C-V Characteristics, Non-Ideal
I-V effects; Complementary CMOS inverter DC characteristics, Static load MOS inverters, Differential
inverter, Transmission gate, Tristate inverter, Bipolar devices
CMOS PROCESSING TECHNOLOGY
CMOS Fabrication overview, Basic CMOS technology, Stick Diagrams, Design rules and Layout, SOI rules,
design rules: MOSIS scalable CMOS design rules, micron design rules; CMOS process enhancements,
Latchup, technology-related CAD issues, manufacturing issues
CIRCUIT CHARACTERSATION AND PERFORMANCE ESTIMATION
Resistance estimation, Capacitance estimation, Inductance estimation, Switching characteristics: Delay
estimation, CMOS gate transistor sizing, Logical effort and transistor sizing, Timing analysis delay models,
Power Dissipation, Energy-delay optimization, Low power architectures
INTERCONNECT AND ROBUSTNESS
Interconnect modelling, Interconnect impact, Interconnect engineering, Sizing routing conductors, Charge
sharing, Design Margin, Robustness introduction, Variability, Yield, Reliability, Scaling, Statistical analysis
of variability, Variation-tolerant design
CMOS CIRCUIT DESIGN AND DESIGN METHOD
CMOS Logic Gate Design- Basic Physical Design of Simple Gate, CMOS Logic Structures, Clocking
Strategies, I/O Structures, Low Power Design, Super Buffers, BICMOS and Steering Logic, Driving Large
Capacitive load, Design Strategies, Chip Design Options, Design Methods, Design Capture and Verification
Tools, Data sheets, Basics of testing
REFERENCES
1. Neil H. E. Weste, Eshraghian Kamran, Principles of CMOS VLSI Design: A System Perspective,
2nd Edition, Pearson, 2010 (Reprint)
2. Neil H. E. Weste, David Harris, Banerjee, CMOS VLSI Design: A Circuits and System Perspective,
3rd Edition, Pearson, 2010 (Reprint)
3. Neil H. E. Weste, David Harris, CMOS VLSI Design, 4th Edition, Pearson, 2010
4. Douglas A Pucknell and Eshraghian Kamran, Basic VLSI Design- system and circuits, Prentice
Hall, 2003
5. Wayne Wolf, Modern VLSI Design, Pearson, 2007
6. John .P. Uyemura, Introduction to VLSI Circuits and Systems , Wiley, 2003

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 6 of 37

ECE5123

ANALOG DESIGN

L
3

T
0

P
0

C
3

FIELD EFFECT TRANSISTORS

J-FETs, MESFETs, MODFET, MOS diode, MOSFETs: Fundamentals, Essentials, Non Ideal MOS, Basic
device characteristics, Non uniform doping and buried-channel device, Device scaling and Short-channel
Effects, MOSFET Structures, CMOS and BICMOS, MOSFET on Insulator, MOS Memory Structures, Power
MOSFET, Single Electron Transistor
MODELLING OF FIELD EFFECT TRANSISTORS
PSPICE Modelling: MOSFETs- DC, small signal, high frequency and noise models of MOSFETs. MOS
Capacitors, Device Scaling- short and narrow channel MOSFETs. MOSFET channel mobility model, DIBL,
charge sharing and other non-linear effects, MOS Models: Level-1 and level-2 large signal MOSFET models,
BSIM models, Extraction of MOSFET model parameters
BJT AND MOS TRANSISTOR AMPLIFIERS, CURRENT MIRRORS
Single transistor Amplifiers stages, Multiple Transistor Amplifier stages, Differential Amplifiers, Current
Mirrors of Bipolar, MOS transistors, Voltage and current references, Output Stages
OPERATIONAL AMPLIFIER
Applications of operational Amplifier, theory and Design; Definition of Performance Characteristics
-Deviation from Ideality in Real Operational Amplifiers, Design of two stage MOS Operational Amplifier,
Operational Amplifier with cascodes, Bipolar operational amplifiers. Frequency response of Integrated
Circuits Single Stage Amplifiers, Multistage Amplifiers, NE5234 OP-AMP, Feedback, Frequency response
and stability of feedback amplifiers
NONLINEAR ANALOG CIRCUITS
Analysis of four quadrant and variable Tran conductance multiplier, Voltage controlled oscillator,
Comparators, Analog Buffers, Phase Locked Techniques; Phase Locked Loops (PLL), closed loop analysis of
PLL. Digital-to-Analog (D/A) and Analog-to-Digital (A/D) Converters
REFERENCES
1. Paul. B Gray, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th Edition, Wiley,
2009
2. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw Hill, 2002
3. David A Johns, Kenneth W Martin, Analog Integrated Circuit Design, Wiley, 2011
4. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010
5. Arora. N. D., MOSFET Models for VLSI Circuit Simulation, Springer-Verlag, 2003
6. Simon M. Sze, Semiconductor Devices Physics and Technology, 2 nd Edition, Wiley, 2003
7. M. H. Rashid, Introduction to PSpice using OrCAD for circuits and electronics, Prentice Hall, 2004

M. Tech. VLSI DESIGN

REGULATIONS 2011

ECE5124

DIGITAL DESIGN

DIGITAL SYSTEMS OVERVIEW

Number Systems, Basic Logic Gates, Combinational Logic Circuits, Sequential Logic Circuits, Logic
Families, Classification of memories, RAM organization, PROM, EPROM, EEPROM, EAPROM, and
Advanced Flash Memory Architecture
ADVANCED TOPICS IN BOOLEAN ALGEBRA
Shannon expansion theorem, consensus theorem octal designation, fun measure, INHIBIT/ INCLUSION/
AOI/ Driver/ Buffer gates, gate expander, Reed Muller expansion, synthesis of multiple output combinational
logic circuits by product map method
THRESHOLD LOGIC, SYMMETRIC FUNCTIONS
Linear seperability, unateness, physical implementation, dual comparability, reduced functions, various
theorems in threshold logic, synthesis of single gate and multigate threshold network, Symmetric Functions:
Elementary symmetric functions, partially symmetric and totally symmetric functions, Mc Cluskey
decomposition method, unity ratio symmetric ratio functions, synthesis of symmetric function by contact
networks, Clock skew, jitter
SEQUENTIAL CIRCUITS DESIGN
Mealy machine, Moore machine, trivial/reversible/ isomorphic sequential machines, state diagram, state table
minimization, incompletely specified sequential machines, state assignments, design of synchronous and
asynchronous sequential logic circuits working in the fundamental mode and pulse mode, ASM Chart, ASM
Realization, Races in ASC, Hazards, Unger s theorem
PROGRAMMABLE LOGIC DEVICES
Programming logic device families Designing synchronous sequential circuit using PLA/PAL Realization
of FSM using PLD Introduction to field programmable gate arrays Types of FPGA, Logic Cell array (LCA),
CLB, IOB, programmable interconnect point (PIP), Introduction to Actel ACT2 family and Xilinx XC3000,
XC4000 families, Design examples
REFERENCES
1.
2.
3.
4.

William I Fletcher, An Engineering Approach to Digital Design, Prentice Hall, 2006

James E. Palmer, David E. Perlman, Introduction to Digital Systems, Tata McGraw Hill, 2006
N.N. Biswas, Logic Design Theory, Prentice Hall, 2003
S.Devadas. A Ghosh and K Keutzer, Logic synthesis, Tata McGraw Hill, 2004

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 8 of 37

ECE5125

MODELLING AND SYNTHESIS WITH VERILOG HDL

HARDWARE MODELLING WITH VERILOG HDL

HDLs in EDA, System C, VHDL and Verilog, System Verilog overview, Hardware Encapsulation, Hardware
Modeling with Verilog HDL, Hierarchical descriptions of hardware, Structured design methodology, Arrays,
Using Verilog for synthesis, Language conventions, Representation of numbers, Event driven simulation and
testbenches, Logic system, data types and operators, User-defined primitives: Combinational behaviour,
Sequential behaviour, Sequential primitives initialization
DELAY MODELS, BEHAVIOURAL DESCRIPTION
Verilog models of propagation delay, Built-in constructs, Signal transition, Inertial delay, Time scales and
precision, Delays, Delay effects and Pulse rejection, Race condition in Verilog, Types of race condition, Task
and function, Events, Process control, Fork/join, Disable a block, Watchdog, debugging, Code coverage,
Testing strategies, File handling, Behavioral descriptions in Verilog HDL,
SYNTHESIS OF COMBINATIONAL LOGIC, SEQUENTIAL LOGIC
Synthesis of Combinational Logic, HDL-Based Synthesis, Technology-Independent Design, Synthesis
Methodology, Styles for Synthesis of Combinational Logic, Technology Mapping and Shared Resources,
Three-State Buffers, Outputs and Don't Cares, Synthesis of Sequential Logic, Synthesis of Sequential UDPs,
Latches, Edge-Triggered Flip-Flops, Registered Combinational Logic, Shift Registers and Counters Finite
State Machines, Resets, Gated Clocks, Design Partitions and Hierarchical Structures
SYNTHESIS OF LANGUAGE CONSTRUCTS, SWITCH LEVEL MODELS
Synthesis of Language constructs, MOS Transistor Technology, Switch-Level Models, PULL gates, CMOS
Transmission gates, Bi-Directional gates (Switches), Signal Strengths, Ambiguous Signals, Strength
Reduction by Primitives, Combination and Resolution of Signal Strengths, Signal Strengths and Wired Logic,
FIFOBuffers for Data Acquisition, FIFO Application, UART, Bit-Slice Microcontroller, Rapid Prototyping
with Verilog and FPGAs
ELECTRONIC DESIGN AUTOMATION
Electronic Design Automation, Design, Simulation, Analysis, Verification, Testing, Synthesis, Design flow:
High level synthesis, Logic synthesis, Schematic capture, Layout; Simulation: Transistor (low) level, Logic
(RTL, Gate-netlist boolean) level, Behavioural simulation, Hardware emulation, Analysis: Functional
verification, CDC check, Formal verification, Equivalence checking, Timing analysis, Physical verification;
Formats: netlist, GDSII, Gerber, OASIS, EDIF, DEF, LEF, SDF, Tools for Analog and Digital VLSI Design
Design, Simulation and Synthesis, VLSI Back-end, Layout tools, Testing tools, Shell scripts for VLSI, List
and overview of EDA tools
REFERENCES
1. M,D,Ciletti, Modeling, Synthesis and Rapid Prototyping with the Verilog HDL, Prentice Hall, 2006
2. Steven M. Rubin, Computer Aids for VLSI Design, http://www.rulabinsky.com/cavd (free online
book), 1997
3. M,G, Arnold, Verilog Digital Computer Design, Prentice Hall, 2006
4. S. Palnitkar, Verilog HDL A Guide to Digital Design and Synthesis, Pearson , 2003

M. Tech. VLSI DESIGN

ECE5183

REGULATIONS 2011

HDL PROGRAMMING AND EDA TOOLS LABORATORY

HDL PROGRAMMING
1. Study of simulation tools, Study of synthesis tools, Study of FPGA board
2. RTL description of combinational and sequential circuits using Verilog HDL/VHDL
a. All gates with all modelling, half adder and full adder, Multiplexer, Address decoder
b. Clock generator with variable duty cycle and frequency, clock generator with jitter, clock
multiplier, clock divider and a pulse counter
c. 2 bit counter as a FSM (with Clock, Reset, Enable, Load, and Count up or down)
d. 4 bit multiplier, 8 bit adder, Accumulator, Calculator (Addition, Subtraction and
Multiplication of 2s complement numbers)
e. 4/8 bit Barrel shifter, 8 bit Parallel to serial converter (with a go bit for start of transmission)
f. PRBS generator, Memory unit
3. Verification of the Functionality using a Simulator, for above RTL designs with test benches: Linear
or File I/O Based or Task based Test bench
4. Synthesis of the above RTL designs and power and timing analysis of the synthesised designs
PSPICE MODELLING
5. Introduction to Spice language
6. Study of Netlist (R, C, diodes, MOS transistors, BJTs), Models (diodes, MOS transistors, BJTs), and
Analysis types (dc, ac and transient)
7. Verify truth tables of NOT, AND, OR gates implemented by NAND gates using PSPICE
8. Diode Circuits
a. Diode characteristics and basic diode circuits: - Experimental identification of basic diode
Spice model parameters
b. Design of rectifiers and power supplies: - Ripple, line and load regulation specs
9. MOS Transistor Circuits
a. MOS characteristics: - Experimental identification of basic MOSFET Spice model parameters
b. NMOS Inverter: - Depletion and Enhancement Mode Circuit Simulation
c. CMOS Inverter: - Circuit Simulation, adjustment of W/L ratio of P & N channel MOS
transistor for symmetrical drive output and loading consideration, Scaling of CMOS Inverter
for different technologies, study of secondary effects
10. Current source/Mirrors
a. Circuit simulation of current Mirror using BJT and MOS (Simple, Wilson and Widler
configurations) study and modifications to improve power and load regulation
11. Differential Amplifier
a. Study of specifications of Differential amplifier and Design considerations, Study of input
loading and biasing techniques, Determination of gain, bandwidth, output impedance and
CMRR
12. Frequency response of an op-Amp integrator circuit, RC-coupled CE Amplifier
MINI PROJECT
(INCLUDING THE FOLLOWING)
13. Design and characterization of an 8-bit ADC circuit using HDL
14. Design of FFT using HDL
15. Design and simulation of pipelined serial and parallel adder to add/ subtract 8 numbers of size, 12 bits
each in 2's complement

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 10 of 37

M. Tech. VLSI DESIGN

REGULATIONS 2011

16.

ECE5126

VLSI TECHNOLOGY

SEMICONDUCTOR PHYSICS, PN JUNCTION

Semiconductor devices, Energy bands and Carrier concentration, Carrier modelling, Quantization concept,
Equilibrium carrier concentration, Carrier action, State equations, p-n Junction, Thermal equilibrium
condition, Depletion Region, Depletion Capacitance, I-V Characteristics, Ideal diode equation, Hetero
junctions, Metal-semiconductor contacts, Ideal MIS Capacitors, Silicon MOS Capacitors:
PSPICE Modelling: AC, DC, Transient, noise, temperature extra analysis, Junction Diodes- DC, small signal,
large signal, high frequency and noise models of diodes. Measurement of diode model-parameters
BIPOLAR TRANSISTORS
Bipolar Transistor Fundamentals, Transistor action, Static, BJT Dynamic Response Modelling, Frequency
response and switching of Bipolar Transistors, Microwave characteristics, Hetero-junction Bipolar transistor
PSPICE Modelling: BJT- DC, small signal, high frequency and noise models of bipolar junction transistors.
Extraction of BJT model parameters
WAFER PREPARATION, EPITAXY AND OXIDATION
Electronic Grade Silicon, Wafer preparation, Czochralski crystal growing, Silicon Shaping, processing
consideration, Epitaxy, Growth Mechanism and kinetics, Oxidation Techniques and Systems, Models of
Diffusion in Solids, Atomic Diffusion, Ion implantation
LITHOGRAPHY, ETCHING AND DEPOSITION
Types of Lithography, Plasma Etching techniques and Equipments, Deposition process, Polysilicon, plasma
assisted Deposition
METALLISATION AND PROCESS INTEGRATION
Metallisation: Physical vapour deposition, Patterning, Process integrated: NMOS IC Technology, CMOS IC
Technology, MOS Memory IC technology - Bipolar IC Technology, IC Fabrication
REFERENCES
1.
2.
3.
4.
5.

S.M.Sze, VLSI Technology, McGraw Hill, 2003

Douglas A. Pucknell, Kamran Eshraghian, Basic VLSI Design, Pearson, 2003
R.S. Muller and T.I. Kamins, Device Electronics for Integrated Circuits, 3 rd Edition, Wiley, 2003
Simon M. Sze, Semiconductor Devices Physics and Technology, 2 nd Edition, Wiley, 2003
M. H. Rashid, Introduction to PSpice using OrCAD for circuits and electronics, Prentice Hall, 2004

6. Giuseppe Massobrio, Paolo Antognetti, Semiconductor Device Modeling with Spice, Tata McGraw
Hill, 2010

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 11 of 37

M. Tech. VLSI DESIGN

ECE5127

REGULATIONS 2011

ADVANCED DIGITAL DESIGN

COMBINATIONAL, SEQUENTIAL CIRCUITS DESIGN

Wire models, Circuit families, Circuit pitfalls, Comparison of circuit families, SoI circuit design, subthreshold circuit design, Design methodology Simulation of complex logic gates, Sequencing static circuits,
Circuit design of latches and flip-flops, Sequencing dynamic circuits, Timing issues in digital circuits,
Synchronous design, self-timed design, Synchronizers and arbiters, Clocks, PLLs and DLLs, Clock synthesis
and synchronization using PLL, Wave pipelining,
DATA PATH, ARRAY, SPECIAL-PURPOSE SUBSYSTEMS
Data paths, Addition/Subtraction, One/Zero detectors, Comparators, Counters, Boolean logical operations,
Coding, Shifters, Multiplication, Parallel-prefix computation, Power and Speed tradeoff, Memory architecture
and building blocks, Memory Core, SRAM, DRAM, ROM, SAM, CAM, Memory peripheral circuits, Robust
Memory Design, Power distribution, I/O, 4 Mbit SRAM design, 1GBIT NAND FLASH RAM design, MIPS
processor design
CIRCUITS AND MODELS, ARCHITECTURE LEVEL SYNTHESIS
Graphs, Combinatorial optimization, Graph optimization problems and algorithms, Boolean algebra and
functions, Hardware Modelling Languages, Abstract models, Compilation and behavioural optimization,
Circuit specifications for architectural synthesis, Synthesis problems, Area and performance estimation,
Strategies for architectural optimization, Data path synthesis, control-unit synthesis, synthesis of pipelined
circuits
SCHEDULING ALGORITHMS AND RESOURCE SHARING
Model for the scheduling problems, Scheduling without and with constraints, Scheduling algorithms for
extended sequencing models, Scheduling pipelined circuits, Sharing and binding for resource dominated
circuits, Concurrent binding and scheduling, Resource sharing and binding for non-scheduled sequencing
graphs, the module selection problem, Resource sharing and binding for pipelined circuits
LOGIC-LEVEL SYNTHESIS AND OPTIMIZATION
Two-level combinational logic simulation, Multiple-level combinational logic simulation, Sequential logic
optimization, Cell-library binding
REFERENCES
1. Neil H. E. Weste, David Harris, Banerjee, CMOS VLSI Design: A Circuits and System Perspective,
3rd Edition, Pearson, 2010
2. Jan M. Rabaey, et.al., Digital Integrated Circuits, 2nd Edition, Prentice Hall, 2004
3. G.De Micheli, Synthesis and optimization of Digital circuits, McGraw Hill, 1994
4. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010
5. James O. Hamblen, et.al., Rapid prototyping of digital systems, Springer- SOPC Edition, 2008

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 12 of 37

M. Tech. VLSI DESIGN

ECE5128

REGULATIONS 2011

ANALOG AND MIXED SIGNAL DESIGN

ANALOG AND MIXED SIGNAL DESIGN FUNDAMENTALS

Challenges in Analog design, Mixed signal processing blocks, Mixed signal issues, Mixed signal design
example, Review of Basic MOS Transistors, Review of Basic Analog Circuits Large signal, Small signal
models, Amplifiers, Signals, Filters, Submicron CMOS circuit design
ANALOG AND DIGITAL FILTERS
Sampling, Sample and Hold Circuits, Data converters, Differential non-linearity and Integral non-linearity for
DACs and ADCs, Data converter architectures, Analog filters, Integrator building blocks, Analog Filtering
topologies, Digital filters, SPICE models for DACs and ADCs, Sinc-shaped Digital filters, Digital filtering
topologies
DATA CONVERTER SNR, DESIGN BASICS
Quantization noise, SNR, Clock jitter, Improving SNR using averaging, using feedback, Decimating filters for
ADC, Interpolating filters for DAC, Data converter design, One bit ADC and DAC, Passive noise-shaping,
Improving SNR and linearity using an Active circuit
NOISE SHAPING, BANDPASS DATA CONVERTERS
First order noise shaping, second order noise shaping, Noise shaping topologies, Continuous time Bandpass
noise-shaping, Passive component modulators, Active component modulators, Modulators at RF Frequencies,
Switched-capacitor, Bandpass noise-shaping
HIGH SPEED DATA CONVERTERS
Topology, Clock signals, Path settling time, Implementation, filtering, understanding the signals, Practical
implementation, Generating clock signals, Components Switched capacitors, Amplifiers, Clocked
comparators; High speed ADC, Switched capacitor circuits
REFERENCES
1. R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, 2nd Edition, Wiley-IEEE press, 2008
2. Vineeta P. Gijji, Analog and Mixed Mode VLSI Design, Prentice Hall, 2011
3. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010

E.C.E. DEPARTMENT

KALASALINGAM UNIVERSITY

Page 13 of 37

ECE5129

ASIC DESIGN

ASICs INTRODUCTION*
Introduction to ASICs, ASICs types, Design flow, Comparison, Cell libraries, CMOS transistors, CMOS
process, CMOS rules, Combinational logic cells, Sequential logic cells, Data path logic cells, I/O Cells, Cell
compilers, ASIC Library design
PROGRAMMABLE ASICs, LOGIC CELLS, I/O CELLS
Antifuse, Static RAM, EPROM and EEPROM technology, Issues, Specifications, PREP benchmarks, Actel
ACT, Xilinx LCA, Altera FLEX, Altera MAX, DC and AC I/Os, Clock input, Power input, Xilinx I/O blocks,
Other I/O cells
PROGRAMMABLE ASIC INTERCONNECT, DESIGN SOFTWARE, LOW LEVEL DESIGN
ENTRY
Interconnect Actel ACT, Xilinx LCA, Xilinx EPLD, Altera MAX, FLEX; Design systems, Logic synthesis,
Halfgate ASIC, Schematic entry, Low level design languages, PLA tools, EDIF, CFI design representation,
HDL languages overview and design examples
LOGIC SYNTHESIS, SIMULATION, TESTING
Logic synthesizer, Verilog and Logic synthesis, FSM synthesis, Memory synthesis, Performance driven
synthesis, Case studies, Simulation types, Design example, Logic systems and Logic simulation, Cell models,
Delay models, Static timing analysis, Formal Verification, Switch-level simulation, Transistor-level
simulation, Testing importance, Design example, Case study, SOC Introduction, Design issues in SOC, High
performance algorithms for ASICs/ SOCs
PARTITIONING, FLOORPLANNING, PLACEMENT, ROUTING
ASIC construction, Physical design, System partitioning, Size estimation, Power dissipation, FPGA
partitioning, partitioning methods, Floorplanning, Placement, Information formats, Routing, Circuit extraction
and DRC, ASIC/SOC Case studies- Design of: Digital camera, Bluetooth radio/modem, SDRAM and USB
controllers
REFERENCES
1. M.J. Sebastian Smith, Application Specific Integrated Circuits, Pearson, 2009
2. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010

ECE5184

VLSI DESIGN LABORATORY

1. Place and route ,Back annotation for FPGAs (Synthesis, P&R and Post P&R simulation, Concepts of
FPGA floor plan, critical path, design gate count, I/O configuration and pin assignment, Generation of
configuration/fuse files, I/O data demonstration using Logic Analyzer)
2. Design and simulation of back annotated Verilog HDL files for multiplying two signed, 8 bit numbers
in 2's complement. Design must be pipelined and completely RTL compliant
3. Design of static random access memories (SRAMs)
4. Implementation of 8 Bit ALU in FPGA, 4 bit sliced processor in FPGA
5. Implementation of FFT, Digital Filters
6. HDL implementation of I2C bus protocol
7. Design a Synchronous FIFO of 4 x 16 bit words with test bench using System Verilog
8. Design the Models of R, L, C, Diode, Op Amp, basic gates, using Verilog-A or Verilog AMS
9. Study of Synthesis, simulation and physical design of a digital circuit, standard CAD tools to design,
layout and simulate VLSI circuits, graphical schematic entry and post-processing tools, a complete
VLSI design example: from RTL to GDSII
10. Layout of a simple CMOS inverter, parasitic extraction and simulation
11. Design and optimize the delay, power, and area of an inverter chain
12. Design, analyze, simulate and layout of static CMOS gates, dynamic CMOS gates
13. Design and optimize a full adder circuit
14. Design latches and flip-flops and analyze timing and clocking issues
MINI PROJECT
(INCLUDING THE FOLLOWING)
15. Implementation of a USART on FPGA
16. Implementation of a 4-bit X 4-bit array multiplier with carry-save circuit techniques using Sequential
Circuit Components
17. Implement an arbitrary sequence generator. Observe waveform on a logic analyzer. Exchange data
with PC and manipulate data in Matlab
18. Implementation of a MAC on FPGA
19. Design capture and mixed-mode simulation and analysis of a successive approximation ADC
20. Design of a 10 bit number controlled oscillator using standard cell approach, simulation followed by
study of synthesis reports; Automatic layout generation followed by post layout extraction and
simulation of the designed circuit
Tools needed: Dolphin SMASH, Cadence/MAGMA/Tanner/Synopsys/Silvaco/Alliance, Electric with plug-ins
IRSIM, Bean Shell, and Jython, Xilinx ISE/Altera Quartus, Magic, SPICE software, Xilinx/Altera FPGA kits
Design is to be carried at-least in 0.5u CMOS technology

M. Tech. VLSI DESIGN

ECE6111

REGULATIONS 2011

TESTING OF VLSI CIRCUITS

FAULT MODELLING AND FAULT SIMULATION

Introduction to testing - Faults in Digital Circuits - Modelling of faults: - Functional modelling at logical,
register and structural levels Logic simulation Types of simulation Event Driven simulation - Delay
models Fault Modelling - Logical Fault Models Fault detection Fault Equivalence and Fault Location
Fault dominance Fault simulation Technique - Fault simulation for combinational circuits Fault sampling
TEST GENERATION FOR CIRCUITS
Introduction - Composite circuit representation and value systems - Test generation basics -Implication Structural test generation: preliminaries - Specific structural test generation paradigms - Non-structural test
generation techniques -Test generation systems -Test generation for reduced heat and noise during test Classification of sequential ATPG methods and faults - Fault collapsing - Fault simulation - Test generation
for synchronous circuits - Test generation for asynchronous circuits - Test compaction - IDDQ testing
DESIGN FOR TESTABILITY
Testability - Ad Hoc Design for Testability Techniques Controllability and observability by means of scan
registers- Generic scan path designs Board level and system level DFT approaches Advanced Scan
concepts Boundary scan standards - Compression Techniques
SELF-TEST AND MEMORY TESTING
Built-In Self-Test concepts BIST Design Rules - Test pattern generation for BIST- Exhaustive Testing,
Pseudorandom Testing, Pseudo exhaustive Testing, Logic Segmentation and Constant weight patterns
Generic offline BIST architecture Specific BIST architecture CSBL, BEST, RTS, LOCST,
STUMPS,CBIST, CEBS, RTD, SST, CATS, CSTP and BILBO Advanced BIST Concepts - Memory testing
- Traditional tests - March tests - Pseudorandom memory tests
FAULT DIAGNOSIS, SELF-CHECKING DESIGN AND PLA TESTING
Logical Level Diagnosis Diagnosis by UUT reduction Fault Diagnosis for Combinational Circuits Selfchecking design System Level Diagnosis PLA testing - PLA testing problems Test generation algorithms
for PLAs Testable PLA design
REFERENCES
1. M.Abramovici, et.al., Digital systems and TestableDesign, Jaico IEEE Publishers, 2002
2. Niraj jha, S. Gupta, Testing of Digital systems, Cambridge Press, 2003
3. Laung-T Wang, et.al (Editors), VLSI Test principles and architectures: Design for Testability,
Kaufmann Publishers, 2006
4. Parag. K.Lala, An Introduction to Logic Circuit Testing, Morgan Publishers, 2005
5. Parag. K. Lala, Digital Circuit Testing and Testability, Kluwer Academic, 2002
6. M.L.Bushnell, V.D.Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal
VLSI Circuits, Kluwer Academic, 2002

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ECE5130

REGULATIONS 2011

VHDL ANALYSIS AND DESIGN OF DIGITAL SYSTEMS

COMBINATIONAL DESIGN
Combinational logic design-Boolean algebra, logic gates, timing, combinational logic using VHDL gate
models-Entities and architectures, identifiers, spaces and comments, netlists, signal assignments, generics, test
benches, configurations, Combinational building blocks-three-state buffers, decoders, multiplexers, priority
encoder, adders, parity checker, test benches for combinational blocks.
SYNCHRONOUS SEQUENTIAL DESIGN
Synchronous Sequential systems, Algorithmic State machine, synthesis from ASM charts, state machine in
VHDL,VHDL testbenches for state machines, VHDL models of sequential logic blocks-latches, flip flops, JK
and T flip flops, registers and shift registers, counters, memory, sequential multiplier, testbenches for
sequential building blocks.
VHDL SYNTHESIS AND SIMULATION
Event driven simulation, simulation of VHDL models, simulation modelling issues, fire operations, RTL
synthesis, constraints, synthesis for FPGAs, behavioural synthesis, verifying synthesis results
TESTING AND DESIGN FOR TESTABILITY
Need for testing, fault models, fault oriented test pattern generation, fault simulation in VHDL, Ad-Hoc
testability improvements, structured design for test ,built in self test ,boundary scan
ASYNCHRONOUS SEQUENTIAL DESIGN
Analysis of asynchronous circuits, design of asynchronous sequential circuits, asynchronous state machines,
setup and hold times and metastability, interfacing with the analog world, VHDL-AMS, Phase locked loop,
VHDL AMS simulators
REFERENCES
1.
2.
3.
4.
5.

Zwolinski, Digital System Design with VHDL, Pearson, 2007

Volnei A. Pedron, Digital electronics and design with VHDL, Kaufmann, 2008
Frank Vahid, Digital Design with RTL Design, Verilog and VHDL, Wiley, 2010
Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010
James O. Hamblen, et.al., Rapid prototyping of digital systems, Springer- SOPC Edition, 2008

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REGULATIONS 2011

ELECTRONIC DESIGN AUTOMATION TOOLS

ELECTRONIC DESIGN AUTOMATION

EDA, Design, Simulation, Analysis, Verification, Testing, and Synthesis, Manufacturing preparation, Field
solvers, Functional verification, CDC check, Physical verification; Manufacturing preparation: Mask Data
Preparation, Resolution Enhancement Techniques, Optical Proximity Correction, Mask generation, Test
pattern generation, BIST, Signoff, Formats: netlist, GDSII, Gerber, OASIS, EDIF, DEF, LEF and SDF
OVERVIEW OF EDA TOOLS
Tools for Analog and Digital VLSI Design, VLSI Backend, Layout tools, PCB design and Layout tools,
Testing tools, Shell scripts, Mixed Signal Design- Modelling, Integration to CAE tools, Features of EDA
tools: LTSPICE, PSPICE, HSPICE, NI Multisim, Modelsim, Lenoardo Spectrum, Xilinx ISE, Quartus, Active
HDL, Riviera, ALINT, Cadence, Synopsys, Magic, IRSIM, gEDA, netlist and GDSII viewers, AutoTrax, IP
Products, ADS
SYNTHESIS AND SIMULATION
Synthesis and simulation using HDLs-Logic synthesis using Verilog and VHDL, Memory and FSM synthesis,
Performance driven synthesis, Simulation- Types of simulation, Static timing analysis. Formal verification,
Switch level and transistor level simulation
CIRCUIT SIMULATION AND DESIGN
Circuit simulation using Spice - circuit description, AC, DC and transient analysis, Advanced spice commands
and analysis, Models for diodes, transistors and OPAMP, Digital building blocks, A/D, D/A and sample and
hold circuits, Design and analysis of mixed signal circuits,
ANALYSIS AND MODELLING OF MIXED SIGNAL, SYSTEM DESIGN AND TESTING
Mixed signal circuit modelling and analysis using VHDL AMS, System design using SystemC- SystemC
models of computation, Classical hardware modelling in system C. Functional modelling. Parameterized
modules and channels, Test benches, Tracing and debugging
REFERENCES
1.
2.
3.
4.
5.
6.

M.J. Sebastian Smith, Application Specific Integrated Circuits, Pearson, 2009

M. H. Rashid, Spice for Circuits and Electronics using Pspice, Prentice Hall, 2004
T. Grdtker, et al, System Design with SystemC, Kluwer, 2004
P.J. Ashenden, et al, The System Designers Guide to VHDL-AMS, Elsevier, 2005
Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010
James O. Hamblen, et.al., Rapid prototyping of digital systems, Springer- SOPC Edition, 2008

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ECE5132

REGULATIONS 2011

SCRIPTING LANGUAGES FOR VLSI DESIGN AUTOMATION

SCRIPTING LANGUAGES
Definition of script, Scripting Context, Shell scripts Overview of Scripting Languages PERL, CGI, VB
Script, Java Script, Python, Ruby, and TCL
PERL, INTERFACING
Operators, Statements Pattern Matching etc. Data Structures, Modules, Objects, Tied Variables, Inter process
Communication Threads, Compilation and Line Interfacing
PROGRAMMING IN PERL, TCL BASICS
Debugger Internal & Externals Portable Functions, Extensive Exercises for Programming in PERL, TcL
language basics
PROGRAMMING IN TCL
Basic commands, Control constructs, Advanced constructs, File I/O, TcL application in EDA tools, tk and
wish, Example: Back-Annotating a Verilog module
OTHER LANGUAGES
Broad Details of CGI, VB Script, Java Script, Python, Ruby with Programming Examples
REFERENCES
1. Randal L, Schwartz Tom Phoenix, Learning PERL, Oreilly Publications, 2000
2. Larry Wall, et.al., Programming PERL, Oreilly Publications, 2000
3. Tom Christiansen, Nathan Torkington, PERL Cookbook, Oreilly Publications, 2000

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ECE5133

REGULATIONS 2011

PHYSICAL DESIGN OF VLSI CIRCUITS

INTRODUCTION TO VLSI TECHNOLOGY

Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining, WeinBerger arrays and gate matrices-layout of standard cells gate arrays and sea of gates, field programmable gate
array(FPGA)-layout methodologies-Packaging-Computational Complexity-Algorithmic Paradigms
PLACEMENT USING TOP-DOWN APPROACH
Partitioning: Approximation of Hyper Graphs with Graphs, Kernighan-Lin Heuristic- Ratio-cut- partition with
capacity and i/o constraints; Floor planning: Rectangular dual floor planning- hierarchical approachsimulated annealing- Floor plan sizing; Placement: Cost function- force directed method- placement by
simulated annealing- partitioning placement- module placement on a resistive network regular placementlinear placement
ROUTING USING TOP DOWN APPROACH
Fundamentals: Maze running- line searching- Steiner trees; Global Routing: Sequential Approacheshierarchical approaches- multi-commodity flow based techniques- Randomised Routing- One Step approachInteger Linear Programming; Detailed Routing: Channel Routing- Switch box routing; Routing in FPGA:
Array based FPGA- Row based FPGAs
PERFORMANCE ISSUES IN CIRCUIT LAYOUT
Delay Models: Gate Delay Models- Models for interconnected Delay- Delay in RC trees. Timing Driven
Placement: Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving
Routing: Delay Minimization- Click Skew Problem- Buffered Clock Trees. Minimization: constrained via
Minimization- unconstrained via Minimization- Other issues in minimization
SINGLE LAYER ROUTING, CELL GENERATION AND COMPACTION
Planar subset problem (PSP) - Single layer global routing- Single Layer Global Routing- Single Layer
detailed Routing- Wire length and bend minimization technique Over the Cell (OTC) Routing- Multiple chip
modules (MCM) - Programmable Logic Arrays- Transistor chaining- Wein-Burger Arrays- Gate matrix
layout- 1D compaction- 2D compaction
REFERENCES
1. Sarafzadeh, C.K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1995
2. Preas M. Lorenzatti, Physical Design and Automation of VLSI systems, Benjamin Cummins
Publishers, 1998
3. Ban Wong, et.al. , Nano CMOS Circuit and Physical Design Wiley 2004
4. N.A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic, 2002
5. Sadiq M. Sait, Habib Youssef, VLSI Physical Design Automation, Theory and Practice World
Scientific Publishing Company, 2003
6. Bryan T. Preas, Physical Design Automation of VLSI system, Benjamin Cummins Publishers, 1998
7. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010

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ECE5134

REGULATIONS 2011

CAD FOR VLSI CIRCUITS

VLSI DESIGN METHODOLOGIES

Introduction to VLSI Design methodologies, Review of Data structures and algorithms, Review of VLSI
Design automation tools, Algorithmic Graph theory and Computational complexity, Tractable and Intractable
problems, General purpose methods for combinatorial optimization
DESIGN RULES
Layout Compaction, Design rules, Problem formulation, Algorithms for constraint graph compaction,
Placement and partitioning: Circuit representation, Placement algorithms, Partitioning
FLOOR PLANNING, ROUTING
Floor planning concepts, shape functions and floor plan sizing, Types of local routing problems, Area routing,
Channel routing, Global routing, Algorithms for global routing
SIMULATION
Simulation, Gate-level modelling and simulation, Switch-level modelling and simulation, Combinational
Logic Synthesis, Binary Decision Diagrams, Two Level Logic synthesis
MODELLING AND SYNTHESIS
High level synthesis, Hardware models, Internal Representation, Allocation, Assignment and scheduling,
Simple scheduling algorithm, Assignment problem, High level transformations, Physical Design Automation
of FPGAs, MCMs
REFERENCES
1. S.H. Gerez, Algorithms for VLSI Design Automation, Wiley, 2002
2. N.A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic, 2002
3. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010

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M. Tech. VLSI DESIGN

ECE5135

REGULATIONS 2011

FPGA BASED SYSTEM DESIGN

FPGA FUNDAMENTALS
Introduction to ASICs and FPGAs, Fundamentals in Digital IC design, FPGA and CPLD architectures, FPGA
development board hardware and I/O features, FPGA programming technologies, FPGA logic cell structures,
FPGA programmable interconnect and I/O ports, Downloading design to FPGA board, NiosII Processor
software development, Nios II Hardware design
FPGA IMPLEMENTATION
FPGA implementation of Combinational circuits, Sequential design and hierarchy, FPGA implementation of
sequential circuits, Timing issues in FPGA synchronous circuits, FPGA core library functions, Verilog HDL,
Design flow using Verilog HDL, Using Verilog HDL for synthesis of hardware
ARCHITECTING SPEED, AREA, POWER
Architecting speed, Architecting area, architecting power, high level design, Clock domains, Design
examples: AES, I2S vs. SPDIF, State machine design: The electric train controller,
FPGA CIRCUITS
Arithmetic circuits, Implementing Math functions, Example design: FPU, DSP applications, Reset circuits,
Coding for synthesis, direct digital frequency synthesiser implementation, Example design: Secure Hash
algorithm, synthesis optimization, VGA display using FPGA, Interfacing PS/2 Keyboard and mouse, Digital
I/O interfacing standards
FPGA DESIGN
FPGA Microprocessor design, Design of SDRAM controller, Design of half tone pixel converter, Design of
ADSL modem, Design of Software Radio, RISC design: Synthesis of MIPS core, Programming FPGA in
electronics systems, dynamically reconfigurable systems, Operating system support for SoPC design
REFERENCES
1. Wayne Wolf, FPGA-Based System Design, Prentice Hall, 2004
2. Steve Kilts, Advanced FPGA Design, Wiley, 2004
3. James O. Hamblen, et.al., Rapid prototyping of digital systems, Springer- SOPC Edition, 2008

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M. Tech. VLSI DESIGN

ECE5136

REGULATIONS 2011

GENETIC ALGORITHMS AND ITS APPLICATIONS

GA TERMINOLOGY
Introduction, Finding the best solution, Minimum seeking algorithms, Natural optimization methods,
Biological Optimization, GA Terminology, Simple (Binary coded) GA, Steady State Algorithm, Genetic
Operators, Selection, Crossover, Mutation, Fitness scaling, Inversion, GA Example
GA FOR VLSI DESIGN
GA for VLSI Design, Layout and Test automation - partitioning, automatic placement, routing technology
mapping for FPGA, Automatic test generation, Power estimation
PARTITIONING, PLACEMENT, ROUTING
Partitioning algorithm, Taxonomy, Circuit partitioning by GA, Hybrid genetic algorithm for Ratio-cut
partitioning, GA for Standard cell placement and MACRO Cell Placement
ROUTING, FPGA TECHNOLOGY MAPPING, TESTING
Global routing, FPGA technology mapping, automatic test generation
POWER ESTIMATION, PARALLEL IMPLEMENTATIONS, TYPES OF GA
GA for peak power estimation, Parallel implementation of GA, Problem encoding, fitness function, Types of
GA, GA Parameters, Genetic Algorithms vs. Conventional algorithms
REFERENCES
1. Pinaki Mazumder, E.MRudnick, Genetic Algorithm for VLSI Design, Layout and test
Automation, Prentice Hall, 2008
2. Randy L. Haupt, Sue Ellen Haupt, Practical Genetic Algorithms, Wiley, 2004
3. Ricardo Sal Zebulum, et.al., Evolution Electronics: Automatic Design of electronic Circuits and
Systems Genetic Algorithms, CRC press, 2006
4. John R.Koza, et.al., Genetic Programming Automatic programming and Automatic Circuit
Synthesis, MIT Press, 1999

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ECE5137

REGULATIONS 2011

OPTIMIZATION METHODS FOR ENGINEERING DESIGN

LINEAR PROGRAMMING
Linear programming formulation Graphical and simplex methods Big-M method Two phase method
Dual simplex method Primal Dual problems.
UNCONSTRAINED ONE DIMENSIONAL OPTIMIZATION TECHNIQUES
Unconstrained one dimensional optimization techniques - Necessary and sufficient conditions Unrestricted
search method - Fibonacci and Golden section method Quadratic interpolation, cubic interpolation and
direct root methods.
UNCONSTRAINED n DIMENSIONAL OPTIMIZATION TECHNIQUES
Unconstrained n dimensional optimization techniques direct search methods Random search methods
Pattern search methods - Rosenbrocks method - Descent methods -Steepest descent, conjugate gradient,
Quasi - Newton methods.
CONSTRAINED OPTIMIZATION TECHNIQUES
Constrained optimization Techniques - Necessary and sufficient conditions Equality and inequality
constraints - Kuhn-Tucker conditions - Gradient projection method-cutting plane method- penalty function
method
DYNAMIC PROGRAMMING
Dynamic programming Principle of optimality recursive equation approach application to shortest route,
cargo-loading, allocation and production schedule problems
REFERENCES
1. Fox, R. L., Optimization methods for Engineering Design ", Wesley, 1979
2. Rao S. S., Optimization :Theory and Application, Wiley, 2009
3. Taha, H.A., Operations Research: An Introduction, Prentice Hal, 2008

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REGULATIONS 2011

ECE5138 ADVANCED MICROPROCESSORS AND MICROCONTROLLERS

MICROPROCESSOR ARCHITECTURE
Organization and Architectural Features of Microprocessor and Micro Controllers, Instruction Set, Data
formats, Addressing modes, Memory hierarchy register file, Cache, Virtual memory and paging,
Segmentation- pipelining the instruction pipeline pipeline hazards RISC principles RISC versus CISC,
Overview of 8086/8088, IBM PC Architecture, MASM- assembler directive, real mode, protected mode,
DPMI services
HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM
CPU Architecture, Salient features, Bus operations, Pipelining, Instruction Translation, Instruction Translation
Look aside Buffer and Branch Prediction, Floating Point Unit, Operating Modes, Rapid Execution Module,
Memory Subsystem, Paging, Multitasking, Hyper threading Technology, Extended Instruction set in
Advanced Pentium Processors, Programming the Pentium processor
HIGH PERFORMANCE RISC ARCHITECTURE ARM
Organization of CPU, Bus architecture, Memory management unit, Registers, Current Program Status
Register, Pipeline, ARM instruction set, Thumb instruction set, Addressing modes, Programming the ARM
processor
Exception Handling, Interrupts, Interrupt Handling schemes, Firmware, Embedded Operating Systems,
Caches-Cache Architecture, Cache Policy, DSP on the ARM7TDMI, ARM9TDMI, Strong ARM, ARM9E,
ARM10E, Embedded ARM Applications
PICMICROCONTROLLERS
PIC Microcontroller: Architectural Overview, Memory Organization, Data Memory and Flash Memory,
Instruction set, Interrupts and Reset, I/O Ports, Timer, I 2C Interfacing, PWM, UART and Analog to Digital
Converters
INTERFACING, BUS STANDARDS
Interfacing of memory devices, Data transfer techniques and I/O ports; Interfacing of keyboard and display
devices, Programmable Interrupt and DMA controllers, Standards for Bus architectures and ports: ISA Bus,
EISA Bus, MCA Bus, PCI Bus, VESA Bus, AGP, USB, IEEE1394, RS232-C, RS423-A, RS-449, RS-366,
IDE,EIDE,ATA, ATAPI and SCSI, SCSI Adapter, PCMCIA Cards and Slots, IEEE1284, IEEE488
REFERENCES
1.
2.
3.
4.
5.
6.
7.

Daniel Tabak , Advanced Microprocessors, Tata McGraw Hill, 2000

James L. Antonakos, The Pentium Microprocessor, Pearson Education, 1997
Steve Furber, ARM System On Chip architecture, Addison Wesley, 2000
Barnett, Cox and OCull, Embedded C Programming and the Microchip PIC Thomson, 2007
John .B.Peatman, Design with PIC Microcontroller, Prentice Hall, 1997
Valvano, Embedded Microcomputer Systems", Thomson, 2001.
Badri Ram, Advanced Microprocessor and Interfacing, Tata McGraw Hill, 2007

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ECE5139

REGULATIONS 2011

DSP ARCHITECTURE

DSP FUNDAMENTALS
Digital signal-processing system, Sampling process, discrete time sequences, Linear time-invariant systems,
DFT, FFT, Digital filters, Decimation and interpolation, Analysis Computational accuracy, Number formats
for signals and coefficients in DSP systems, Dynamic Range and Precision, Sources of error in DSP, DSP
Computational errors, A/D, D/A Conversion Errors, Compensating filter
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES
Basic Architecture, DSP Computational Blocks, Multiplier and Multiplier accumulator, Modified Bus
Structures and Memory access in P-DSPs, Multiple access, Multi-ported memory, VLIW architecture,
Pipelining , Special Addressing modes, Address Generation Unit, On chip Peripherals
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS
TMS320C5X, TMS320C3X PROCESSORS: Architecture, syntax, Addressing modes, Instructions, Pipeline
structure, Operation, Block Diagram of DSP starter kit, Application Programs for processing real time signals
IMPLEMENTATION OF BASIC DSP ALGORITHMS
Design tool for DSP Systems MATLAB, DSP Assembler and the Assembly Source File, Linker and Memory
Allocation, C Compiler, Code Composer Studio, The IEEE754 Q notation, Bit-Reversed index generation,
Overflow and scaling, FIR Filters, IIR Filters, interpolation Filters, Decimation filters, PID Controller,
Adaptive Filters, 2-D Signal Processing, Computation of signal spectrum
ADVANCED PROCESSORS, ADSP PROCESSORS
Architecture of TMS320C6X, Architecture of Motorola DSP563XX, Comparison of the features of DSP
family processors, FPGA Based DSP system design, Architecture of ADSP-21XX and ADSP-210XX series of
DSP processors, Addressing modes and assembly language instructions
REFERENCES
1. B.Venkataramani, M.Bhaskar, Digital Signal Processors: Architecture, Programming and
Applications, Tata McGraw Hill, 2010
2. Avtar Singh, S. Srinivasan, Digital signal processing implementations: using DSP microprocessors
(with examples from TMS320C54xx), 2004
3. Walt Kester (Editor), Mixed-signal and DSP Design Techniques, Elsevier, 2002
4. Phil Lapsley, et.al., DSP Processor Fundamentals: Architectures and Features, Wiley, 2000
5. Jonathan (Y) Stein, Digital Signal Processing: A Computer Science Perspective, Wiley, 2000
6. S. K. Mitra, Digital Signal Processing: A Computer Based Approach, Tata McGraw Hill, 2010

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ECE5140

REGULATIONS 2011

ADVANCED COMPUTER ARCHITECTURE

OVERVIEW OF COMPUTER ARCHITECTURE

Digital logic, HW/SW/FW allocation, Organization and architecture, Computer evolution and Performance,
Computer components, Computer function, Interconnect structures, Bus interconnection, PCI
COMPUTER SYSTEM
Memory management and hierarchy, Caches: associativity, allocation and replacement policies, sub-block
placement. Multilevel caches, Cache performance issues, Uniprocessor cache coherency issues: selfmodifying code, peripherals, address translation, Six basic cache optimizations, Eleven Advanced
optimizations of Cache performance, Virtual memory, Virtual memory protection and examples, Virtual
memory and virtual machines, Cross cutting issues, AMD Opteron memory hierarchy
CENTRAL PROCESSING UNIT
Computer arithmetic, ISA: functions, addressing modes and formats, comparisons, Role of compiler, MIPS,
Processor structure and function, RISC, CISC architectures, RISC vs. CISC architectures comparison, RISC,
CISC Processor s and overview
INSTRUCTION LEVEL PARALLELISM
Instruction Level Parallelism - over coming data hazards- reducing branch costs high performance
instruction delivery, Superscalar processors, VLIW,EPIC, Itanium- architectures, Instruction pipelining, Outof-order execution, Register naming, Speculative execution, Branch prediction, ILP: Hardware vs. Software
approach, Limits on ILP, Memory Level Parallelism,
MULTIPROCESSORS, THREAD LEVEL PARALLELISM
Multiprocessors and Thread Level Parallelism, Control unit and operation, Interleaved memory architecture,
Symmetric shared memory architectures, Distributed shared memory - synchronization, Symmetric
multiprocessors, Bus-based 'snooping' protocol design space, Cache coherence, Scalable shared memory,
Open MP and MPI, MESI protocol, Clusters, NUMA, Vector computing, Simultaneous multithreading ('hyper
threading'), and vector instruction sets (such as SSE and AVX), Graphics processors and Multicore computers:
SIMT, the CUDA and OpenCL programming models
REFERENCES LIMIT BOOKS
1. William Stallings, Digital Computer Organization and Architecture: Designing for Performance,
8th Edition, Pearson, 2010
2. John. L. Hennessy, David. A. Patterson, Computer Architecture: A Quantitative Approach,
4th Edition, Elsevier (Morgan Kufmann Series), 2010
3. Kai Hwang, Naresh Jotwani, Advanced Computer Architecture: Parallelism, Scalability and
Programmability, Tata McGraw Hill, 2010
4. John Hayes, Computer Architecture and Organization, Tata McGraw Hill, 2010
5. David Culler, J.P. Singh, Anoop Gupta, Parallel Computer Architecture: A Hardware/Software
Approach, Elsevier (Morgan Kufmann Series), 2005
6. Nicholas Carter, Raj Kamal, Computer Architecture and Organization, Tata McGraw Hill
(Schaum's Outline Series), 2009
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ECE5141

REGULATIONS 2011

VIDEO AND AUDIO PROCESSING

DSP FUNDAMENTALS
Digital signal-processing system, Signal representation, Sampling process, ADC architectures, Discrete time
sequences, Quantization of Discrete time sequences, DFT, FFT, Fast convolution and filtering, Fast matrix
computations, Digital filters, Decimation and interpolation, Statistical signal processing, Time-frequency and
Multirate signal processing
SPEECH PROCESSING
Physiology of speech generation: characteristic of speech sounds; speech production models, linear prediction
analysis, spectral envelopes; applications of LP analysis, Speech coding: Coder's attributes; waveform coding;
vocoders; analysis-by-synthesis coding; code-excited linear predictive vocoder; regular pulse-excited LPC
IMAGE PROCESSING
Digital image representation and visual perception, Image enhancement, Image coding and compression
techniques, Codec examples, Image analysis and segmentation, Threshold, Image representation and
description: Boundary descriptor; Chaincode; Fourier descriptor; Skeletonizing; Texture descriptor; Moments,
Stereoscopic image processing, Still image compression, Image processing software and databases
AUDIO PROCESSING
Basic digital audio processing techniques, Dithering; Noise shaping, DAC, Equalization, Digital Audio
compression, Amplitude masking; Temporal masking; Waveform coding; Perceptual coding; Coding
techniques: Sub band coding and Transform coding; Codec examples
VIDEO PROCESSING
Digital video formats, Basic digital video processing techniques: Motion estimation; Interframe filtering;
Motion-compensated filtering; Error concealment, Video coding techniques, Block-based motion estimation
and compensation; Coding techniques, Codec examples
REFERENCES
1.
2.
3.
4.
5.
6.
7.

Vijay Madisetti (Ed.), The Digital Signal Processing Handbook, 2nd Edition, CRC Press, 2009
A. K. Jain, Fundamentals of digital image processing, Prentice Hall, 2009
Ben Gold, Nelson Morgan, Speech and Audio Signal Processing, Wiley, 2004
Lawrence R.Rabiner, R.W.Schaffer, Digital Processing of Speech signals, Prentice Hall, 2009
James L. Flanagan et.al., Speech Analysis Synthesis and Perception, Springer-Verlag, 2008
A.M. Tekalp, Digital Video Processing, Prentice Hall, 2005
A L Bovik(Editor), Handbook of Image and Video Processing, Elsevier, 2005

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M. Tech. VLSI DESIGN

ECE6112

REGULATIONS 2011

RF MICROELECTRONICS CHIP DESIGN

INTRODUCTION TO RF DESIGN AND WIRELESS TECHNOLOGY

Design and Applications, Complexity and Choice of Technology, Basic concepts in RF design: Nonlinearly
and Time Variance, Intersymbol interference, random processes and noise, Sensitivity and dynamic range,
conversion of gains and distortion
RF MODULATION, RF TESTING
Analog and digital modulation of RF circuits, Comparison of various techniques for power efficiency,
Coherent and non-coherent detection, Mobile RF communication and basics of Multiple Access techniques,
Receiver and Transmitter architectures, Direct conversion and two-step transmitters, RF testing for
heterodyne, Homodyne, Image rejection, Direct IF and sub sampled receivers.
BJT AND MOSFET BEHAVIOR AT RF FREQUENCIES
BJT and MOSFET behavior at RF frequencies, modelling of the transistors and SPICE model, Noise
performance and limitations of devices, integrated parasitic elements at high frequencies and their monolithic
implementation
RF LOW NOISE AMPLIFIER, MIXERS DESIGN
Overview of RF Filter design, Active RF components & modeling, Matching and Biasing Networks, Basic
blocks in RF systems and their VLSI implementation, Low noise Amplifier design in various technologies,
Design of Mixers at GHz frequency range, Various mixers- working and implementation,
RF OSCILLATORS, FREQUENCY SYNTHESIZER, POWER AMPLIFIER DESIGN
Oscillators- Basic topologies VCO and definition of phase noise, Noise power and trade off, Resonator VCO
designs, Quadrature and single sideband generators, Radio frequency Synthesizers- PLLS, Various RF
synthesizer architectures and frequency dividers, Power Amplifier design, Liberalization techniques, Design
issues in integrated RF filters, Nonlinearly and Time Variance, intersymbol Interference, random processes
and Noise, Definitions of sensitivity and dynamic range, conversion Gains and Distortion
REFERENCES
1. B.Razavi, RF Microelectronics, Prentice-Hall, 1998
2. T.H. Lee, Design of CMOS Radio-Frequency Integrated Circuits, Cambridge Press, 2004
3. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010

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REGULATIONS 2011

SYSTEM-ON-CHIP DESIGN

INTRODUCTION TO SOC, SYSTEM LEVEL DESIGN

SOC Technology Challenges, Microsystems technology and applications, SOC components, BJT Modelling
with VBIC, MOS Transistor Model for Mixed Analog-digital Circuit Design and Simulation, Retargetable
Application-driven Analog-digital Block Design, System level design, System level space and modelling
languages, SOC block based design and IP assembly
SOC ISSUES AND POWER MANAGEMENT
SOC Issues, SOC Design Methodology, Power Considerations, SOC Case study, Design Consideration
Challenges, Memories, Parameterized SOC , SOC Peripheral Cores, SOC and interconnect centric
Architectures, System level power management, Embedded software modelling and design using performance
metrics to select microprocessor for IC design, Design Reuse
MICRO-ARCHITECTURE DESIGN AND POWER OPTIMIZATION
Micro-architecture design, Cycle accurate system level modeling, Performance evaluation, Micro
architectural power estimation optimization, Design planning. SOC protocols, OC, VSI, Target architecture
models, Intra-chip communication, Task time measurement, Interconnect latency modeling, Back annotation
of lower level timing to high-level models, Synthesis of SOC components
SOFTWARE DESIGN VERIFICATION
Logical verification, Design and Verification languages, Digital simulation, using transactional, level models
in an SOC design, Assertion based verification, Hardware/Software Co-Design, System Level, Block Level
and Hardware/Software Co-verification
HARDWARE DESIGN VERIFICATION
SOC components: emulation, co-simulation, Physical Verification, Hardware acceleration & emulation,
Formal property verification, TEST, DFT, ATPG, Analog and mixed signal test , IP Core Design issues, IP
Core Design Methodology, Reusability and intellectual property, IP Core Applications
REFERENCES
1. Louis Scheffer, Grant Martin,et.al., EDA for IC System verification and Testing, CRC, 2006
2. Prakash Rashnikar, et.al., System-On-A-Chip Verification methodology and techniques, Kluwer
Academic, 2005
3. Badawy, Wael; Julien, et.al., (Eds.), System-on-Chip for Real-Time Applications, Springer, 2003
4. Reis, Ricardo, et.al. (Eds.), Design of Systems on a Chip: Design and Test, Springer, 2007
5. Ricardo Reis, J A. G. Jess, Design of System on a Chip Devices and Components, Springer, 2007
6. Alberto Sangiovanni Vincentelli, Surviving the SOC Revolution: A Guide to Platform based
Design, Kluwer Academic, 2003

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DCN CODE

RF MEMS

SWITCHING
RF MEMS relays and switches: Switch parameters, Actuation mechanisms, Bistable relays and micro
actuators, Dynamics of switching operation.
MEMS INDUCTORS AND CAPACITORS
MEMS inductors and capacitors: Micro machined inductor, Effect of inductor layout, Modeling and design
issues of planar inductor, Gap tuning and area tuning capacitors, Dielectric tunable capacitors.
MEMS COMPONENTS
MEMS phase-shifters: Types. Limitations, Switched delay lines, Micro machined transmission lines, coplanar
lines, Micro machined directional coupler and mixer
FILTERS
Micro machined RF filters: Modeling of mechanical filters, Electrostatic comb drive, Micromechanical filters
using comb drives, Electrostatic coupled beam structures
ANTENNAS
Micro machined antennas: Micro strip antennas design parameters, Micromachining to improve
performance, Reconfigurable antennas
REFERENCES
1. V.K.Varadan, et.al., RF MEMS and their Applications, Wiley, 2003
2. H.J.Delos Santos, RF MEMS circuit Design for Wireless Communications, Artech house, 2002
3. G.M.Rebeiz, RF MEMS Theory, Design and Technology, Wiley, 2003

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REGULATIONS 2011

EMBEDDED SYSTEMS

FUNDAMENTALS TO EMBEDDED SYSTEMS

Definition and Classification Overview of Processors and Hardware Units in an Embedded System
Software Embedded into the System Exemplary Embedded Systems Embedded Systems on a Chip (SOC)
and the Use of VLSI Designed Circuits.
EMBEDDED PROCESSOR AND COMPUTING PLATFORM
Embedded hardware building blocks, Embedded board, Embedded processors, ARM processor- processor and
memory organization, Data operations, Flow of Control, SHARC processor- Memory organization, Data
operations, Flow of Control, parallelism with instructions, Board buses, CPU Bus configuration, ARM Bus,
SHARC Bus, Board Memory, Board I/O, Device drivers
DEVICES AND BUSES FOR DEVICES NETWORK
I/O Devices Device I/O Types and Examples Synchronous ISOsynchronous and Asynchronous
Communications from Serial Devices Examples of Internal SerialCommunication Devices UART and
HDLC Parallel Port Devices Sophisticated interfacing features in Devices/Ports Timer and Counting
Devices I2C USB CAN and Advanced I/O Serial, High Speed Buses ISA PCI PCI X CPCI
and Advanced buses
EMBEDDED PROGRAMMING
Programming in Assembly Language (ALP) vs. High Level Language C Program Elements Macros and
Functions Use of Pointers NULL Pointers Use of Function Calls Multiple Function Calls in a Cyclic
Order in the Main Function Pointers Function Queues and Interrupt Service Routines Queues Pointers
Concepts of EMBEDDED PROGRAMMING in C++ Objected Oriented Programming Embedded
Programming in C++ C Program compilers Cross compiler Optimization of Memory Codes
REAL TIME OPERATING SYSTEMS
Embedded operating systems (RTOS), Middleware and application software , OS Services Interrupt
Routines Handling Task Scheduling Models Handling of Task Scheduling and Latency and Deadlines as
Performance Metrics Inter Process Communication and Synchronization Shared Data Problem Use of
Semaphore(s) Priority Inversion Problem and Deadlock Situations Inter Process Communications using
Signals Semaphore Flag or Mutex as Resource key Message Queues Mailboxes Pipes Virtual
(Logical) Sockets RPCs
REFERENCES
1. Rajkamal, Embedded Systems Architecture, Programming and Design, Tata McGraw Hill, 2003
2. David E. Simon, An Embedded Software Primer, Pearson, 2000
3. Wayne Wolf, Computers as Components: Principles of Embedded Computing System Design,
Morgan Kaufman Publishers, 2008
4. Jane.W.S. Liu, Real-Time systems, Pearson, 2000

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REGULATIONS 2011

LOW POWER VLSI DESIGN

POWER DISSIPATION
Need for Low power design, Sources of power dissipation, Physics of power dissipation in MOSFETs, Power
dissipation in CMOS, CMOS leakage current, Design for Low power dissipation, Basic principles of low
power design, Circuit techniques for leakage power reduction, Low power design limits
POWER ESTIMATION
Simulation power analysis, Probabilistic power analysis, Power estimation: Circuit, Logic
DESIGN OF LOW POWER CIRCUITS
Design and test of low voltage CMOS circuits, Special techniques, Low power SRAM architectures,
Architecture and systems, Advanced Techniques
SYNTHESIS, SOFTWARE DESIGN FOR LOW POWER
Synthesis for low power, Low energy computing using energy recovery techniques, Software design for low
power
LOW POWER SYSTEM DESIGN
Low voltage low power adders, Low voltage low power multipliers, Low-Voltage Low-Power Read-Only
Memories, Large Low-Power VLSI System Design and Applications
REFERENCES
1. Gary K. Yeap, Practical low power digital VLSI design", Springer, 2002
2. K. Seng Yeo, Kaushik Roy, Low Voltage, Low Power VLSI Subsystems, Tata McGraw Hill, 2009
3. Kaushik Roy, Sharat Prasad, Low-Power CMOS VLSI Circuit Design, Wiley, 2000

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REGULATIONS 2011

NANOELECTRONICS

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BASIC SOLID STATE PHYSICS, SHRINK-DOWN APPROACHES

Energy bands, Localized particles, Organic compounds, Semiconductor materials and building
blocks, CMOS scaling, Nanoscale MOSFET, Limits of scaling - Constant electric field scaling, Drain
currents at present limits of scaling, Small Size Limits for the MOSFET, Nano-FET drive currents, nand p- MOSFET devices with 5 nm Channel length, Alternative to Bulk Silicon: Buried Oxide BOX,
Strain Engineering, Benzene Molecule as a Field Effect Transistor
NANO PHYSICS
Properties of individual nanoparticles, Nanoscale Materials and Quantum Mechanics, ThreeDimensional (Bulk materials), Two-Dimensional Systems, One-Dimensional, Zero-Dimensional
(Quantum Wires, Dots), Energy Levels of a (Semiconductor) Quantum Dot and varieties,
Lithographically Defined Quantum Dots, Epitaxially Self-Assembled Quantum Dots, Colloidal
Quantum Dots, Optical Properties of Quantum Dots, Metal Nanoparticles, Quantum bits, Quantum
computation, Metal nanoclusters, Semiconducting nanoparticles, Carbon molecules, Carbon
clusters, Carbon nanotubes
LOGIC DESIGN IN NANOSPACE
Logic design in spatial dimensions, Methodology, Example: hypercube structure of hierarchal
FPGAs, Nanoelectronic devices, Digital nanoscale circuits, Molecular electronics, Operational limits
of nanoelectronic devices, Basics of logic design in nanospace
EMERGING DEVICE TECHNOLOGIES
Quantum Transport Devices Based on Resonant Tunneling, Single-Electron devices for logic
applications, Superconductor digital electronics, Quantum Computing using Superconductors ,
Quantum Cellular Automata's (QCAs), Carbon nanotubes for data processing
NANO MACHINES AND NANO DEVICES
Memories implemented based on Emerging Devices, Photonic Networks, Liquid Crystal Displays,
Organic Light Emitting Devices, Nano-Electro Mechanical Systems (NEMSs)
REFERENCES
1. Rainer Waser (Editor), Nanoelectronics and Information Technology: Advanced Electronic
Materials and Novel Devices, Wiley, 2005
2. Edward L. Wolf, Quantum Nanoelectronics: An Introduction to Electronic Nanotechnology
and Quantum Computing, Wiley, 2009
3. Michael A. Nielsen, Isaac L. Chuang, Quantum Computation and Quantum Information,
Cambridge University Press, 2010
4. Michael C. Petty, Molecular Electronics: From Principles to Practice, Wiley, 2008
5. John H. Davies, The Physics of Low-dimensional Semiconductors: An Introduction,
Cambridge University Press, 1998
6. Sergey Edward Lyshevski et.al., Logic Design of NanoICs, CRC Press, 2006
7. Sergey Edward Lyshevski et.al., Molecular Electronics, Circuits, and Processing Platforms,
CRC Press, 2007
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ECE6117

REGULATIONS 2011

EMI AND COMPATIBILITY IN SYSTEM DESIGN

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EMI ENVIRONMENT
Definition of EMI and EMC with examples, Classification of EMI/EMC - CE, RE, CS, RS, Units of
Parameters, Sources of EMI, EMI coupling modes - CM and DM, ESD Phenomena and effects, conducted
and radiated EMI, Transient EMI phenomena and suppression, Time domain vs Frequency domain EMI,
Emission and immunity concepts
EMI COUPLING PRINCIPLES
Conducted, Radiated and Transient Coupling, Common impedance ground Coupling, Radiated common mode
and ground Loop coupling, Radiated differential mode coupling, Near field cable to cable coupling, Power
mains and Power supply coupling
EMI/EMC STANDARDS AND MEASUREMENTS
Civilian standards - FCC,CISPR,IEC,EN, CS, CE and RE Standards, Military standards - MIL STD
461D/462, EMI Test Instruments /Systems, EMI Shielded Chamber, Open Area Test Site, TEM Cell,
Sensors/Injectors/Couplers, Test beds for ESD and EFT, Military Test Method and Procedures (462), Basic
principles of RE, CE, RS and CS measurements, EMI measuring instruments- Antennas, LISN, Feed through
capacitor, current probe, EMC analyzer and detection technique open area site, shielded anechoic chamber,
TEM cell, Frequency assignment - spectrum conversation
EMI CONTROL TECHNIQUES
Shielding, Filtering, Grounding, Bonding, EMI gasket, Isolation transformer, opto-isolator, Transient
suppressors, Cable routing and connection, Signal Control, Component selection and mounting
EMC DESIGN OF PCBs
PCB Trace routing, Cross talk, Impedance control, Power distribution decoupling, Zoning, Motherboard
designs and Propagation delay performance models
REFERENCES
1. Clayton. R.Paul, Introduction to Electromagnetic Compatibility , Wiley, 2006
2. W. Prasad Kodali, Engineering Electromagnetic Compatibility: Principles, Measurements,
Technologies, and Computer Models, Wiley - IEEE Press, 2001
3. Bernhard Keiser, Principles of Electromagnetic Compatibility, Artech House, 1987
4. Henry W.Ott, Electromagnetic Compatibility Engineering, Wiley, 2009

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REGULATIONS 2011

VLSI SIGNAL PROCESSING

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DSP SYSTEMS, FIR FILTERS

DSP systems, Programs, Applications, Representation, Data flow graphs, Loop Bound and Iteration Bound,
Algorithms, Iteration Bound of Multirate Date-flow graphs, Pipelining of FIR filters, Parallel Processing of
FIR filters, Pipelining and Parallel Processing for Low Power
RETIMING, SYSTOLIC ARCHITECTURE DESIGN
Retiming properties, applications, Solving inequality systems, Retiming techniques, Unfolding-algorithm,
application, properties, Critical path, Folding transformation, Techniques, Folded architectures, Folding of
Multirate systems, Systolic architecture design methodology, FIR systolic arrays, Scheduling vector, MatrixMatrix multiplication, Systolic design for space representations with delays
FAST CONVOLUTION, IIR FILTERS
Fast convolution algorithms, Iterated, Cyclic Convolutions, Design by Inspection, Parallel FIR Filters, DCT
and Inverse DCT, Parallel architectures for rank -order filters, Pipeline interleaving in digital filters, Pipelining
in 1st-order and higher-order IIR Digital Filters, Parallel processing for IIR Filters, Combined pipelining and
parallel processing for IIR Filters, Low power IIR filter design using pipelining and parallel processing,
Pipelined adaptive digital filters
SCALING AND ROUND OFF NOISE, BIT-LEVEL ARITHMETIC ARCHITECTURE
Scaling and Round off noise, State variable description, Scaling and Round-off noise computation, Round off
noise in pipelined IIR filters, Round off noise computation using state variable, Slow-Down, Retiming, and
Pipelining, Fast binary adders and multipliers, Parallel multipliers, Interleaved floor plan and bit plane
designed filters, Bit-serial multipliers, Bit-serial filter design and implementation, Canonic Signed Digit
arithmetic, Distributed arithmetic, Redundant arithmetic
NUMERICAL STRENGTH REDUCTION, LOW POWER DESIGN
Sub expression elimination, Multiple Constant Multiplication, Sub expression sharing, Additive and
multiplicative number splitting, Synchronous pipelining and clocking styles, Clock skew, and clock
distribution, Wave pipelining, Constraint space diagram, Implementation, Asynchronous pipelining, Signal
Transition Graphs and its application, Implementation of computational units, Low power design, Power
analysis, Power estimation, Power reduction
REFERENCES
1. K K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, Wiley, 2009
2. M. Ismail and T. Fiez, Analog VLSI: Signal and Information Processing, McGraw-Hill, 2004

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REGULATIONS 2011

VLSI CIRCUIT DESIGN METHODOLOGY

INTRODUCTION
IC definition, Requirements, technologies, goals, approaches, tasks, costs in IC design, Basics of the CMOS
process and devices, Challenges in VLSI circuit design, Cell-based ASIC design methodology, Introduction to
usual design flows in IC design
BASIC ANALOG DESIGN FLOW
Design entry and parameterization, Simulation set-up and post-processing, analog behavioural modelling and
simulation, assisted full-custom layout, Physical verification, Post-layout simulation, Statistical analysis, Tape
out
MIXED SIGNAL DESIGN FLOW
Design entry and floor planning, Partitioning, Mixed-simulation, set-up, Net list generation, Mixed-mode
back annotation, Co-simulation
BASIC DIGITAL DESIGN FLOW
Design entry and functional simulation, automated synthesis and optimization, Semi custom layout:
automated place and route, Back annotation and post layout simulation, Integration into full custom design
flow
ADVANCED DIGITAL DESIGN FLOW
Timing driven synthesis, Timing drive place and route, Low power synthesis flow, Clock tree generation,
Introduction to Linear Time Variant (LTV) analysis, LTV analysis, LTV AC and transfer function analysis,
LTV s-parameters and noise analysis, Passives, Packaging
REFERENCES
1. Liming Xiu, VLSI Circuit Design Methodology Demystified: A Conceptual Taxonomy, WileyIEEE press, 2007
2. Erik Brunvand, Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Pearson, 2010
3. James O. Hamblen, et.al., Rapid prototyping of digital systems, Springer- SOPC Edition, 2008
4. Kenneth S. Kunder, The Designer's Guide to SPICE and Spectre, Kluwer Academic,2005

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