Definition:

Network on chip or network on a chip (NoC or NOC) is a communication subsystem on

an integrated circuit (commonly called a "chip"), typically between IP cores in a system on a chip
(SoC).
# In other words, NoC is a key architect component that determine overall performance, power
and area (PPA) of contemporary SoC device.

Such scalable bandwidth requirement can be satisfied by using on-chip packet-switched

micro-network of interconnects, generally known as Network-on-Chip (NoC) architecture.

The basic idea came from traditional large-scale multi-processors and distributed computing
networks. The scalable and modular nature of NoCs and their support for efficient on-chip
communication lead to NoC-based system implementations.

Even though the current network technologies are well developed and their supporting
features are excellent, their complicated configurations and implementation complexity
make it hard to be adopted as an on-chip interconnection methodology.

In order to meet typical SoCs or multi-core processing environment, basic module of

network interconnection like switching logic, routing algorithm and its packet definition
should be light-weighted to result in easily implemental solutions.

The PPA characteristics of NoC are influenced by a wide range of issues, including:

semi-conductor technology (process node and corner, 2D/3D integration)

circuit technology (synchronous, asynchronous),
SoC architecture and use-case (number of IP blocks, general purpose or domain specific
workload, frequency requirements, voltage, and clock domains)
network topology (homogeneous, heterogeneous)
routing strategy (deterministic, adaptive)
router architecture and features (arity, virtual channels, Quality-of-Service)
test architecture.

Why NoC is built?

To meet the growing computation-intensive applications and the needs of low-power,

high-performance systems, the number of computing resources in singlechip has enormously increased, because current VLSI technology can support such an
extensive integration of transistors.

By adding many computing resources such as CPU, DSP, specific IPs, etc to build a system in
System-on-Chip, its interconnection between each other becomes another challenging
issue.

In most System-on-Chip applications, a shared bus interconnection which needs an

arbitration logic to serialize several bus access requests, is adopted to communicate with
each integrated processing unit because of its low-cost and simple control characteristics.

However, such shared bus interconnection has some limitation in its scalability because
only one master at a time can utilize the bus which means all the bus accesses should be
serialized by the arbitrator.

Therefore, in such an environment where the number of bus requesters is large and their required
bandwidth for interconnection is more than the current bus, some other interconnection methods
should be considered.
Function:

NoCs can span synchronous and asynchronous clock domains or use

unclocked asynchronous logic.
NoC technology applies networking theory and methods to on-chip communication and
brings notable improvements over conventional bus and crossbar interconnections.
NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared
to other designs.

From http://www.arteris.com/technology

Here are four reasons why today's SoC's need a NoC IP interconnect fabric:
1. Reduce Wire Routing Congestion
2. Ease Timing Closure
3. Higher Operating Frequencies
4. Change IP Easily
Reduce Wire Routing Congestion
Arteris network on chip interconnect fabric technology significantly reduces the number of wires
required to route data in a SoC, reducing routing congestion at the backend of the design process.
Backend routing congestion has become one of the most significant factors causing late designs as
the number of IP blocks on a SoC has increased.
Ease Timing Closure

The distributed architecture of Arteris network on chip interconnect fabrics allows for precise
placement of pipelines (aka register slices) to easily resolve timing closure issues without affecting
other areas of the chip.
Higher Operating Frequencies
NoC technology simplifies the hardware required for switching and routing functions, allowing SoCs
with NoC interconnect fabrics to reach higher operating frequencies.
Furthermore, for long or speed-sensitive paths, the architect can easily place pipeline registers along
any connection, allowing for higher frequencies. Precise placement of pipeline registers (also called

register slices) allows the interconnect to exactly accommodate the SoCs timing budget and meet
its target frequency, with less pipeline register latency and no effect on neighboring IP block timing.
In addition to pipelining, distributed globally asynchronous locally synchronous (GALS) technology
allows synchronous modules with locally generated clocks, with asynchronous connections between
them.
In short, NoC technologys simpler switching and routing hardware, fine granularity pipelining
capability, and GALS allow NoC interconnects to achieve higher operating frequencies than inferior
multi-layered bus or crossbar interconnects.
Change IP Easily
Arteris NoC technology makes it easy to swap IP blocks to create derivative chips or to respond
quickly to engineering change orders (ECOs) during development because Arteris NoC interconnects
are protocol agnostic. In an Arteris NoC interconnect fabric, the transaction (protocol) layers are
separate from the transport and physical layers. Small network interface units (NIUs) that convert IP
protocol transaction into transport packets are synthesized close to initiator and target IP blocks,
allowing the rest of the interconnect topology to be made of simpler IP blocks that perform
switching and routing.