LOW POWER DATA BUS ENCODING

& DECODING SCHEMES

BY

Candy Goyal
engg_candy@yahoo.co.in

Isha sood
ishasood123@gmail.com

LOW POWER DATA BUS ENCODING &

DECODING SCHEMES
Candy Goyal engg_candy@yahoo.co.in , Isha Sood ishasood123@gmail.com .

ABSTRACT
With shrinking feature size and increasing frequency, power dissipation on data
bus has become the most predominant factor than the power dissipation in other
parts of the circuitry. The large intrinsic capacitance associated with buses is
responsible for a substantial fraction (approx 40%) of total power dissipated,
because the bus power dissipation is proportional to switching activity. The main
disadvantage of the existing power aware encoding schemes such as Bus Invert
and Bus Invert Transition Signaling is the extra bus line used to indicate the
receiver that the data is encoded or uncoded. A methodology has been proposed
in this project to get rid of this extra bus line. To support this claim, detailed
implementation of such additional logic is presented.
A logical model of data buses is presented and a family of techniques is proposed that can
reduce average power consumption of the bus by 34%
With new implemented technique defined, we present technique for the synthesis
of encoding and decoding interface logic that minimizes the average number of
transitions on heavily-loaded global bus lines at no cost in communication throughput .
The distinguishing feature of our approach is that it does not rely on designers intuition,
but it automatically constructs low-transition activity codes and hardware implementation
of encoders and decoders, given information onward-level statistics. We propose an
accurate method that is applicable to low-width buses, as well as approximate methods
that scale well with bus width.

INTRODUCTION
The advent of portable digital devices such as laptop personal computers has made low
power CMOS circuit design an increasingly important research area. It has been shown
that in CMOS technology a large portion of power dissipation on chip is due to dynamic
power consumption. In whole system buses are major culprit for dynamic power
dissipation. OFF-CHIP and ON-CHIP global bus lines in very large scale Integrated
(VLSI) circuits are generally loaded with large Capacitances, approximately three orders
of magnitude larger than the average on-chip interconnects capacitance. As Dynamic
power dissipation is directly proportional to the capacitance power consumed by off-chip
driving becomes dominant as devices are scaled down, because off-chip capacitance does
not depend on process technology, but depends on the package and printed circuit board

(PCB) technologies. OFF chip buses accounts 60% of total power dissipation. Further
because of shrinkage of technology we are entering a system on chip era and in these
applications it is very much important to save the power dissipation of buses.
Since the power consumption is proportional to the switching activity, thus reducing the
bus switching in an efficient way to reduce the bus power consumption. Based on this
some basic techniques are available in literature like BI (bus invert), BITS (bus invert
transition signaling) are the most commonly used. But there use is limited because of
extra line needed to indicate the receiver that data is encoded or uncoded. The
extra bus line used in these coding makes the coding difficult to use in real circuit design
because it implies changes to the interface specification of the chip. Also this extra bus
line takes extra area also.
To get rid from this problem a methodology has been proposed here which reduce the
switching activity on the buses without the need of extra bus line and also encoder and
decoder has very small hardware which itself consume very less power. In this paper we
compared the result of BI and BITS with our new technique and the hardware of new
technique is also presented

Existing solution of low power data bus encoding and decoding

schemes
Basic system of data bus encoding lines for data transfer in digital system

Figure 1 Basic system of data bus encoding

Figure 1 shows the data bus encoding and decoding, here because data lines are always
bi-directional [1] so we need encoder and decoder on both the sides, when source wants
to transmit a data then it will pass into the encoder, encoder will encode the data so that
number switching activity will reduce. And at the other end it will pass through the
decoders, which decode data in original form. And we are getting original data at the
receiver side with much reduction in switching power.

Proposed Architecture

Figure 2 Encoder & Decoder (gray encoding scheme with MSB reference)

As shown in Figure 2 the input binary data is converted into gray code. The first graycoded data is sent as it is, through the data bus. Then the MSB of the next gray-coded
data is checked. If it is '0', then XOR operation is performed between the lower N-1 bits
of the present gray-coded data and the N-1 bits of the previous encoded data. The MSB
of the present gray-coded data is sent as it is, along with the output of the XOR. If it is
'1', then XNOR operation is performed between the lower N-1 bits of the present graycoded data and the N-1 bits of the previous encoded data. The MSB of the present graycoded data is sent as it is, along with the output of the XNOR.
At the decoder side, depending on the status of the MSB of the data received
through the data bus, XOR operation is performed between the lower N-1 bits of the
previous data received and the lower N-1 bits of the present data through the data bus, if
the MSB is '0', else XNOR operation is performed. Finally this gray-coded data is
converted in to binary form. As shown in the results this technique saves 24% of the total
power dissipation.

Figure 3 FFA (Fourth & Fifth bit ANDing) encoder &decoder

As shown in Figure 3 the input binary data is converted into gray code and then the data
is sent as it is, through the data bus. From the next gray-coded data, AND operation is
performed between 4th and 5th bits for an 8-bit data. If this operation results in '0', then
XOR operation is performed between the remaining six bits of gray-coded data (i.e.
Lower three bits and upper three bits) and the six bits (lower three bits and upper three
bits) of the previous encoded data. The output of the XOR combined with the 4th and 5th
bits is sent through the data bus. If the AND operation results '1', then XNOR operation
is performed in the same way.
At the decoder side, again AND operation is done between 4th and 5th bits of the
data received through the data bus. If it results in '0', then XOR operation is done
between the six bits of the received data and the six bits of the previous received data.
The output so received is then converted into binary. As shown in the results this
technique saves 40% of the total power dissipation.

MODIFIED BITS
4th
B
I
N
A
R
Y
8

6th

OR

B
I
N
A
R
Y

OR

5
AND

AND
5

D
A
T
A

5
NOT
XOR

M
U
X

XOR

M
U
X

NOT

D
A
T
A

5
5

REG

REG

Figure 4 Encoder & Decoder (MBITS encoding scheme)

This is the most useful technique where we get desired results with great reduction in
power. In this technique we take three bits for the reference line and we performed
various operation on these three bits and finally we came to the technique with oring two
bits and then anding it with the third one.
Through this technique we get least switching in the data bus. We took the binary data
which is to be sent. First is the encoder part. Take three bits (4rth and 5th) and perform
oring of two bits , then anding with the third bit (6th). If we get 0 through anding
technique then do XOR previous output with present input except the reference bits
which are to be sent as it is without doing any operation.
If the reference line is 1 i.e anding operation of the two bit is zero then XNOR previous
input with present input except the reference bits. Data which we get after this operation
is encoded data ready to be sent through data buses. Through this the encoded output is
moved to the decoder through data bus line.
In decoder , we check the reference line. If the reference line that is anding & oring
operation of the three bits is zero then XOR previous input with present input except the
reference bits . If the reference bits output is one then XNOR pevious input with present
input except the reference bits.
Now we get decoded output . Final step here is to transform gray to the binary output
which is the data that we passed in the encoder.

Electrical Design Methodology

Fully-hierarchical verilog coding in RTL-to-netlist generation by synthesis has been done
in this project. To design this project we followed the top-down methodology. Firstly the
idea of whole system was made on paper [5] and then the system was further divided into
hierarchical components which are encoder and decoder. Further these components were
divided into the basic components.
These encoder and decoder has been designed which can be used where data is being
transmitted from source to destination. this encoder will encode the data before placed
onto data bus in such a way so that number of transition will reduce hence it will save
switching power dissipation depending on the number of switching reduction. And other
side decoder will decode the data into original form. These encoder and decoder can be
used for off chip data transfer also.
It is not a separate chip; it can be a part of the system. The complete power saving result
is shown in this paper

Power Estimation

Figure 4: basic system of data transfer

Figure 4 shows the basic system of data transfer on the data lines. Let us assume when
switching takes place in any of the bus line it will dissipate P watt power so if in a system
switching takes place on the n bus lines then power dissipation is n * P watt and the
number of bus lines on which switching takes place can be calculated from the switching
activity from the data. So to calculate the switching activity[2] we have taken reference
data, which is shown in the table we have applied these data to all the techniques and then
power dissipation is calculated and based on that we have shown the result.
As we know that the power dissipation is given by:
P = Vdd2 f c -------------------------------------(a)
where P is the power dissipation without using any technique
= Switching activity
Vdd =Supply voltage
f = Frequency
c = Load Capacitance

Let P be the power dissipation after using encoding technique

P = Vdd2 f c -------------------------------------(b)
Now power saving is

(P-P) / P

By putting equation a and b in above equation we have

Power saving = (-) /
Based on this equation we have calculated the power dissipation on the bus lines by using
the following reference data.

Reference Data
Based on this equation we have calculated the power dissipation on the data bus lines by
using the following reference data
0000_0000
0000_0010
0000_1111
0000_0001
0001_0101
1001_0100
1001_0010
1010_0000
1110_1011
0011_0100
0111_0111
1111_0110
0011_0000
0010_1000
1110_0101
1110_1011
0010_0000
1010_0001
0000_1000
0000_0100
This reference data has been taken for estimating the power dissipation of the encoder,
decoder and bus lines of different techniques and the corresponding results has been
shown in the summary given below.

Summary of Design Results

Table 1: Power consumption
S.No

Name of the technique

1.

BI(bus invert)

2.

BITS(bus invert transition

signaling
MSB (MSB reference)

3
4.
5

P encoder
(in nw)

P decoder
(in nw)

555956.55

173342.55

588732.9

411383.57

386547.35

255112.73

390203.12

273067.29

213349.2

366369.37

FFA (fourth & fifth bit ANDing)

MODIFIED BITS

Table 2: Power saving

S.No

Name of the technique

1.

BI(bus invert)

2.

BITS(bus invert transition signaling

MBITS

% saving
10
20
34

Table 3: Area Over heads

S.No

1.
2.
3.
4.
5

Name of the tech

Area of encoder Area of decoder Extra bus

in micrometer in micrometer
line
square
square
BI (Bus Invert)
yes
2006
778
BITS (Bus Invert Transition
yes
Signaling
2109
1556
MSB (MSB Reference)
No
1523
1101
FFA (Fourth & Fifth bit ANDing)
1480
1071
No
MBITS
1204
971
NO

600000
500000
400000

Pow er saving
(encoder)

300000

Pow er saving
(decoder)

200000

3-D Colum n 3

100000
0
BI

BITS

MSB ref.

FFA

MBITS

Figure 5

35
30
25
20
%SAVING

15
10
5
0
BI

BITS

MBITS

Figure 6
2500
2000
1500

AREA (EN)

1000
AREA (DEC)

500
0
BI

BITS

MSB
ref.

Figure 7

FFA

MBITS

Comparision Of Power Saved, Dissipated In The 256 Data With

MBITS
60
50
40
SAVE
NEUTRAL
DISSIPATE

30
20
10
0
7thBIT REF 3 BIT ANDING

4 BIT ref

MBITS

Figure 8

Conclusion:
We have implemented three new techniques as shown in this paper, these techniques are
better than the existing techniques because they do not need the extra bus line from
encoder to decoder to indicate the decoder that data is encoded or decoded. Still we are
saving 34% of power. It has very less area overhead as compared to the previous
techniques. In previous techniques, most of data is unable to save power. And one more
significant advantage of this technique is that out of every data only 18% of total data
combinations dissipate power which is great achievement that we can't achieve with
previous techniques.

References:
[1] Narrow Bus Encoding for Low Power DSP system IEEE transactions on very
Large scale integration (VLSI) systems, VOL9, NO, 5 OCTOBER [2001].
[2] Kushik Roy and Sharat Prasad Low-Power CMOS VLSI Circuit Design
[2000].
[3] Power Optimization of core-Based Systems by Address Bus Encoding IEEE
Transactions on very large scale integration (VLSI) systems, VOL.6, NO,
4December [1998].
[4] Working zone Encoding for reducing the energy in microprocessor address bus
IEEE Transactions on very large scale integration (VLSI) systems, VOL.6, NO,
4December [1998].
[5] Low Power Techniques for Address Encoding and Memory Allocation IEEE
transactions on very large scale integration (VLSI) systems, VOL.6,NO,4June
[2001].
[6] Samir Palnitker Verilog HDL [2004].