HIGH-THROUGHPUT MULTI STANDARD TRANSFORM

CORE SUPPORTING MPEG/H.264/VC-1 USING COMMON

SHARING DISTRIBUTED ARITHMETIC
ABSTRACT:
This paper proposes a low-cost high-throughput multi standard transform (MST) core,
which can support MPEG- 1/2/4 (8 8), H.264 (8 8, 4 4), and VC-1 (8 8, 8 4, 48, 44)
transforms. Common sharing distributed arithmetic (CSDA) combines factor sharing and
distributed arithmetic sharing techniques, efficiently reducing the number of adders for high
hardware-sharing capability. This achieves a reduction in adders in the proposed MST, compared
with the direct implementation method. With eight parallel computation paths, the proposed
MST core has an eightfold operation frequency throughput rate. The CSDA-MST core thus
achieves a high-throughput rate supporting multi standard transformations at low cost.

EXISTING SYSTEM:
Numerous researchers have worked on transform core designs, including discrete cosine
transform (DCT) and integer transform, using distributed arithmetic (DA), factor sharing (FS),
and matrix decomposition methods to reduce hardware cost. The inner product can be
implemented using ROMs and accumulators instead of multipliers to increase the area cost.

EXISTING SYSTEM TECHNIQUE:

Factor sharing (FS) and matrix Decomposition

EXISTING SYSTEM DRAWBACKS:

Low throughput

High cost

PROPOSED SYSTEM:
The proposed CSDA algorithm combines the FS and DA methods. By expanding the
coefficients matrix at the bit level, the FS method first shares the same factor in each coefficient;
the DA method is then applied to share the same combination of the input among each
coefficient position. The main strategy aims to reduce the nonzero elements using CSDA
algorithm.

PROPOSED SYSTEM BLOCK DIAGRAM:

2-D CSDA-MST CORE

PROPOSED SYSTEM ALGORITHM:

Common sharing distributed arithmetic Algorithm

PROPOSED SYSTEM ADVANTAGES:

High-throughput rate

Low cost

SOFTWARE REQUIREMENT:

ModelSim6.4c

Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3/ Spartan 3AN

REAL TIME EXAMPLE:

Video and image applications

Digital cinema or ultrahigh resolution

FUTURE ENHANCEMENT:
We will modify the proposed system by reducing the Area of converting one
dimensional to two dimensional core designs.
High-Throughput Multi Standard Transform Core Supporting MPEG/H.264/VC-1 Using
Common Sharing Distributed Arithmetic

ALTERNATE TITLES:
Title 1: Efficient High-Throughput Multi Standard Transform Core realization on FPGA
Title 2: High-Throughput Multi Standard Transform Core Implementation based on
Common Sharing Distributed Arithmetic
Title 3: Implementation of High-Throughput Multi Standard Transform Core Using
Verilog HDL

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification)