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PrimeTime: Introduction
to Static Timing Analysis
Workshop
34000-000-S16
PrimeTime: Introduction to Static
Timing Analysis
Synopsys 34000-000-S16
i-1
Unit i: Welcome
i-2
Student Guide
Lab Guide
Breaks
Facilities
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-2
Unit i: Welcome
Workshop Goal
i-3
Use
UsePrimeTime
PrimeTimeto
toperform
performStatic
StaticTiming
TimingAnalysis
Analysis(STA)
(STA)
on
onaaFunctional
FunctionalCore
Coreprior
priorto
toPlace
Placeand
andRoute
Route(P&R).
(P&R).
Obtain
Obtainthe
theprerequisite
prerequisiteknowledge
knowledgeto
toattend
attendthe
the
PrimeTime:
PrimeTime:Chip
ChipLevel
LevelSTA
STAworkshop.
workshop.
A/D
DSP
CODEC
Processor_CORE
MPEG
USB
RAM
Functional Core
Core Clock
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
Design Assumptions:
1. STA is performed on the Functional core only; Block level STA has been done in DC. (See Flow
Diagram)
2. No scan chains yet (Flow diagram in PT:Chip level STA workshop)
3. Functional Core routing parasitic RCs (detailed SPEF) and sub block WLMs are available from
early design planning (Chip level floor plan)
4. No clock tree synthesis yet (Flow diagram in PT:Chip level STA workshop)
5. Blocks may be either synthesized netlist or QTMs (will be covered if class time permits)
6. Functional Core has Logical hierarchical partitions (blocks)
7. No I/O pads, no BSD, no clock generation logic yet (Definition of Functional Core)
8. Chip specification is available (in Constraints modules)
9. Multiple Synch/Asynch clocks (in Constraints modules)
10. Multicycle paths (in Constraints modules)
11. Hold Time analysis is performed using Worst case PVT (as opposed to Best case PVT) (in
Constraints modules)
12. No case analysis (absence of scan chains); no functional modes (Flow diagram in PT:Chip level
STA workshop -- although it may apply to Functional CORE but is not discussed in this PT: ISTA)
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Unit i: Welcome
i-4
PrimeTime:
ISTA
PrimeTime:
CHIP Level
CHIP Synthesis
(Design Compiler)
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
Design or Verification engineers who perform STA at the functional core level.
In addition to block level STA, you will handle functional core integration.
Little or no formal experience with Design Compiler.
If you have taken CHIP Synthesis or have experience using Design Compiler, do not attend this
workshop: Take PrimeTime: Chip Level STA
If your expectation is to learn DC as youre expanding your portfolio to include synthesis, you should
take the CHIP Synthesis workshop next and then PrimeTime: Chip Level STA.
PT:Chip Level STA Workshop focuses on final, full chip, post route STA in order to achieve Timing
closure.
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Unit i: Welcome
i-5
TOP
MID
CLOCK-GEN
PLL
JTAG/BSD
Logic
ASYNCH
LOGIC
FUNC_CORE
Synthesized
Block1(wlm)
Synthesized
Block2
Synthesized
Block3
RAM (Timing
model)
Welcome
Synopsys 34000-000-S16
i-5
Unit i: Welcome
i-6
Fully synthesized
Functional Core.
Chip-Level floorplan
and constraints.
Write Top-Level
constraints and
exceptions
Units 4-6
Design Compiler
Resynthesis
Unit 3
Fix data
yes
Errors/
Warnings?
no
Generate STA
Reports
Units 1,8
Timing
violations
Place&Route
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
After synthesis of all sub-blocks, perform Chip level floorplan, global routing and extract the parasitic
RCs between blocks within the Functional core.
QTMs (or Timing models) may be used for the blocks for which synthesized gate level netlist is not
available.
Day-1: Objective: Using the basic 5 step STA flow, constrain all the Register to Register (Internal)
timing paths within the functional core
Day-2: Objectives:Using the 5 step STA flow, constrain all the I/O (interface) timing paths within the
functional core and apply the necessary single clock cycle timing exceptions
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Unit i: Welcome
i-7
Physical Compiler
Mapped netlist
(using WLM)
Placed netlist
PrimeTime
STAMP
CHIP Architect
Parasitics, SDF
PathMill
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-7
Unit i: Welcome
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Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-8
Unit i: Welcome
Workshop Prerequisites
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Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-9
Unit i: Welcome
Unit
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0i
Welcome
Reading Data
Lab
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
Unit 1 Objective:
Is to introduce Static Timing Analysis in PrimeTime by: Defining the 2 steps performed by a Static
Timing Analyzer; Understanding under the hood calculation of cell and net delays based on NLDM
(Non-Linear Delay Model) and WLM (Wire Load Model); Listing 4 types of timing paths; Identifying
the path with the WNS (worst negative slack) or longest delay using the report_timing command;
Interpreting results of the report_delay_calculation command and for cell and net timing arcs and
Finding specific topics in SOLD using key word search.
Unit 2 Objective:
Is to find Tcl syntax errors using the Tcl Syntax checker, to fix these errors and to obtain command and
variable syntax information.
Unit 3 Objective:
Is to create a basic PT setup file, read all the required files for STA and resolve errors and warnings
associated with reading the files.
Unit 4 Objective:
Is to create a Tcl script, which fully constrains internal Register-to-Register paths by Applying clock
constraints and design environmental attributes; Modeling multiple synchronous/asynchronous clocks,
Modeling pre-layout non ideal clocks, Invoking appropriate report commands to verify the correctness
of constraints and Invoking a report to verify the completeness of constraints.
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Unit i: Welcome
Unit
i-11
Lab
Performing STA
Summary
10
Customer Support
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
Unit 5 Objective:
Is to create a Tcl script which fully constrains the Input/Output interface paths by applying port constraints and
environmental attributes, modeling I/O data paths between multiple synchronous and asynchronous clock domains,
modeling pre-layout non ideal clock effects, Invoking appropriate report commands to verify the correctness of constraints,
Invoking a report to ensure the completeness of constraints and Identifying the effect of constraints on the path reported by a
timing report.
Unit 6 Objective:
Is to Efficiently constrain a design for non-single-clock cycle behavior by Defining Timing exceptions, Modeling multi cycle
path, Modeling logically false paths, Writing efficient constraints to model the above and Identifying any ignored exceptions
and remove them.
Unit 7 Objective:
Is to Create a Quick Timing model using a given specification for use in PT by Defining what QTM is, Writing a QTM script
to create a QTM library cell for the given specification and Modifying the link_path to use the QTM just created.
Unit 8 Objective:
Is to Apply three techniques in a systematic approach to analyze timing and design rule violations by Listing the 3 techniques
in the appropriate order, Obtaining summary reports of all constraint violations and determining the next course of action,
Identifying timing bottleneck blocks for re-synthesis. Enabling generation of Divide and conquer Timing reports to
investigate what types of timing paths are causing violations (group_path) and Generating timing reports for setup check,
hold check and showing the fanout, capacitance and transition time along the path.
Unit 9 Objective:
Is to list ways to improve the runtime and memory when using the STA flow in PT and summarize the workshop.
Unit 10 Objective:
Is to introduce you to our Customer Support Services.
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Unit i: Welcome
i-12
In this class, what are the 2 types of blocks which you assume are
contained within the floor-planned Functional Core?
_____________________
_____________________
In this class, how are the net parasitics (RC values) within
Functional Core modeled prior to Place and Route?
__________________________
After attending this class, you will be able to perform Static Timing Analysis on:
(Circle all that apply)
a.
Block (Module) level design that is either a mapped netlist or a timing model
b.
c.
d.
CHIP level design that has been placed and routed (P&R)
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-12
Unit i: Welcome
Acronym
Acronym
Meaning
Meaning
STA
STA
PVT
PVT
DC
DC
WLM
WLM
PT
PT
WNS
WNS
GUI
GUI
SPEF
SPEF
Tcl
Tcl
DRC
DRC
SOLD
SOLD
NLDM
NLDM
QTM
QTM
--
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Meaning
Meaning
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-13
Unit i: Welcome
Appendix
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Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
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Unit i: Welcome
i-15
Group Exercise
Lab Exercise
Acronyms
Recommendation
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
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Unit i: Welcome
i-16
Question
Remember
Checklist
Caution
Note
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-16
Unit i: Welcome
i-17
Description
Courier
Courier italic
Courier bold
[ ]
Control-c
Indicates a path to a menu command, such as opening the Edit menu and
choosing Copy.
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-17
Unit i: Welcome
START
START
RTLand
and
RTL
Chip
Chip
Constraints
Constraints
Design
Planning
Design
Implementation
Design
Refinement and
Chip Finishing
i-18
END
END
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
i-18
Unit i: Welcome
RTL,
chip constraints
RTL,
RTL,
Chip
Chip
constraints
constraints
VCS
CoverMeter
Vera
Design
Planning
MC,
Design
Implementation
Obtain
Obtaintarget
targetRTL
RTL
and
andtoggle
togglecoverage
coverage
compile
compiledatapath
datapath
ACS
synthesis
synthesiswith
withscan
scan
BSDC
JTAG
JTAGinsertion
insertion
Design
Refinement
and Chip
Finishing
RTL
RTLverification
verification
CA
Die
DieInitialization
Initialization
CA
IO
IOPad
Pad
Assignment
Assignment
CA
A
END
END
PP
Power
PowerAnalysis
Analysis
CA
Power
PowerPlanning
Planning
CA
Initial
Initial pin
pin
assignment
assignment
FV
Floor-planning,
Floor-planning,
hierarchy manipulation
hierarchy manipulation
reshaping
reshaping
i-19
CA
CA
FR
ILM
Top-level
ILM
Top-level
global
routing
and
global routing and
congestion
congestionanalysis
analysis
Top-level
Top-level
ILM
repeater
repeaterinsertion
insertion
Top-level
Top-levelroute
route
estimation
estimation
Initial
Initialblock
block
timing
timingbudget
budget
New in 2.2
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
VCS
CA
Chip Architect
PP
PrimePower
FR
Flex Route
BSDC
FV
MC
Module Compiler
ACS
ILM
i-19
Unit i: Welcome
i-20
Block
BlockLevel
Level
physical
synthesis
physical synthesis
START
START
RTL,
RTL,
Chip
Chip
constraints
constraints
Low
LowPower
Power
Optimization
Optimization
One
OnePass
PassScan
Scan
Placement
Placement
PC
Design
Planning
Block
BlockLevel
LevelCTS
CTS
Block
BlockLevel
Level
Detail
DetailRouting
Routing
FV
Block
BlockLevel
Level
RC
RCExtraction
Extraction
ILM
PT
ILM
Generation
Generation
PC
PT
Top
TopLevel
Level ILM
physical
synthesis
physical synthesis
Design
Implementation
Low
FV
LowPower
Power
Optimization
Optimization
One
OnePass
PassScan
Scan
Placement
ATPG
Placement
PC
Chip Finishing
and Design
PT
Refinement
END
END
CA
timing OK
ECO
ECO
Route
Route
FV
RCRCcorrelation
correlation
no
Chip
ChipIntegration
Integration
Top
TopLevel
LevelCTS
CTS
Full
FullChip
ChipSTA
STA ILM
Placement
Placementhandoff
handoff
no
Arcadia
Detail
Router
Block
Block
level
levelIPO
IPO
PC
yes
FV
New in 2.2
Detail
Router
Block
Level
Block
Level
STA
STAand
and
ILM
ILMcreation
creation
timing OK ?
CTC
Top
TopLevel
Level
Detail
DetailRoute
Route
ILM
CTC,
STAMP
Detail
Router
yes
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
CTS
ECO
PC
Physical Compiler
CTC
ClockTree Compiler
ATPG
IPO
In-Place Optimization
i-20
Unit i: Welcome
Arcadia
START
START
RTL,
RTL,
Chip
Chip
constraints
constraints
Full
FullChip
ChipSTA
STA
PT
PT
Design
Implementation
PC
Router
Block
Level
BlockRoute
Level
ECO
ECO Route
ILM
ILMGeneration
Generation
PT
Full
FullChip
ChipSTA
STA
PT-SI
ILM
Top
Toplevel
level
IPO,
hold
fix
IPO, hold fix
PC
Detail
PT
PP
Design
Refinement and
Chip Finishing
Blocks/Top
Blocks/Top
RC
RCExtraction
Extraction
no
Capture
Capture
Block
BlockLevel
Level
Constraints
Constraints
Block
Blocklevel
level
IPO,
IPO,hold
holdfix
fix
Arcadia
yes
timing OK
Design
Planning
ILM
Top
TopLevel
Level
ECO
ECORoute
Route
Detail
Router
END
END
Detail
Router
SLE
ILM
timing OK
yes
Final
FinalPower
Power
Analysis
Analysis
Crosstalk
Crosstalk
Analysis
Analysis
Crosstalk
Crosstalk
Repair
Repair
GDSII
GDSIIMerge
Merge
Calibre
DRC
DRC
Calibre
LVS
LVS
SLE
New in 2.2
i-21
Chip
ChipFinishing
Finishing
Welcome
PrimeTime: Introduction to Static Timing Analysis
Synopsys 34000-000-S16
SLE
LVS
DRC
GDSII
i-21
Unit i: Welcome