Setup and Hold Basics - 1 PDF

Calculation of Setup time and Hold time
User Name
Password
http://www.edaboard.com/thread51611.html
Log in
Register
Lost password?
Resend activation?
Remember Me?
Forum
NewBlogs
Posts
Activity Stream
Unanswered
Posts
What's New?
Search
FAQ
Help
Forum Actions
Rules
Community
Groups
Albums
Quick Links
Advanced Search
Forum
Digital Design and Programming
ASIC Design Methodologies and Tools (Digital)

Welcome to EDABoard.com
+ Post New Thread

Results
1 to
11 of 11
Calculation of Setup
time
and
Hold time
LinkBack
Thread Tools
Search Thread
9th December
2005,10:12
anan_tv
EDA Resources
Junior Member level 1
lvision model generation for clock

gating cells in LV flow
etlibgenerator tool provided by tessent LV does not
support LV scan model generation of clock gating
cells. How to handle clock gating cells in LV flow?
How to provide definition of clock...
Posted By pankaj_sawant. Today 06:14 in ASIC
Design Methodologies and Tools (Digital)
Interfacing rtc(ds1307) pic24f

Hi All, I am trying to interface RTC(DS1307 WITH I2C
) with pic24fj128ga010, somewhere i m doing
1 of 23
Calculation
of
Setup
time
and
Hold
time
Haiii,
Threads Without Replies

[ Unanswered Posts ]
#1
Join Date:
Nov 2005
Location:
Bangalore - INDIA
Posts:
15
Helped:
1/1
Points:
1,365
Level:
How to
calcula
te
Setup
time
and
Hold
time
manual
ly???
How
does
04/11/2014 11:15 AM

mistake but i m not getting where please can any
one find wt i m doing wrong and help me please.. ...
9th December 2005,10:12
Posted By Ranjitharanju. Today 05:56 in

Microcontrollers
HFSS field calculator

I wish to find RMS value of Electric field using Field
calculator. Electric field has three components Ex,
Ey, Ez. Frequency of operation is 100 Khz.. I am not
able to perform integration with...
Posted By monika762. Today 05:49 in
Electromagnetic Design and Simulation
help required -- HFSS to Gerber

hello i have power divider designed in HFSS.Now for
fabrication i need to have the gerber file. Can
anybody help me with this?
12th December 2005,15:46
Posted By shilpa.k. Today 05:44 in Electromagnetic

Design and Simulation
How design the encapsulation M-bus in

RS232
Precision M
Hello, As I am novice in embedded sofware

development,I find some troubles with protocols . i
am working on domotic project.I try to design an
encapsulation for [the industrial protocol...
fotofab.com
Precision Metal Parts
Posted By hajeur. Today 05:34 in Analog Circuit

Design
they
differ
for
FPGA
and
ASIC?
???
Sponsor
Thank
you
Reply With
Quote
9th December
2005,21:40
semiconductorman
Full Member level 3
New Replies
what is different AXI and AXI3? (2)
Garbage data problem from max232
circuit. (5)
Error CST: The calculation seems to be
unstable! A possible source of
instability.... (13)
AltiumDesigner printing error (16)
2 of 23
#2
Re:
Calculation
of
Setup
time
and
Hold
time
setup
and
holdtim
04/11/2014 11:15 AM

Gain of a Digital circuits/Logic circuits.
(13)
How to shift the pulses in labview? (2)
Moving / Copying multiple objects to a
specific location in Eagle (1)
Replacing multiple components in
Eagle. (1)
Need help to draw graph of Peak to
average power (4)
Code failure after schematic
modification (1)
Mercury UPS Power Problem (2)
Need help for doing 3D Image
processing in MATLAB (1)
RF Receiver for 150MHz and 450MHz
FSK Signals (3)
Single Ended To Differential Conversion
(2)
c++ simple computer system (1)
how can i design opamp ideal? (3)
Where do I start learning micro
controllers and using them? (1)
Light sensor intensity (10)
How to design a start up circuit in
bandgap? (2)
SMPS dc ac 150w design problems (1)
dual feeding in a single patch (19)
conversion of LC oscillator to RC
oscillator (3)
Issue with simple buffer design (8)
Hfss project files for fractal antenna
design (4)
Design of Low Drop-out Voltage
Regulator (12)
EE News, Tips and Resources

TI introduces 40-V to 100-V NexFET
MOSFETs 03/25/2014
Power-One Expands Open Frame AC/DC
Portfolio 03/25/2014
AutomationDirect adds WEG miniature
contactors 03/22/2014
Join Date:
Dec
2004
Posts:
156
Helped:
23 / 23
Points:
2,648
Level:
11
e will
be
specifi
ed by
the
library
vendor.
Reply With
Quote
12th December
2005,10:24
anan_tv
#3
Re:
Calculation
of
Setup
time
and
Hold
time
haiii ,
Join Date:
Nov 2005
Location:
Bangalore - INDIA
Posts:
15
Helped:
1/1
Points:
1,365
Level:
I think
the
vendor
will be
giving
it for
ASIC
only.
what
abt
FPGA?
??
also for
any
circuit ,
how to
calucul
ate
them??
?
Sine Wave Generation 03/21/2014

Detect lightning surges with Weidmullers
Logger 30 03/15/2014
Microsemis Highly Integrated IGLOO2 FPGAs
Recognized with DesignVision Award
3 of 23
Reply With
Quote
#4
04/11/2014 11:15 AM

03/15/2014
Altera Introduces OTN Solutions for 400G and

Beyond at OFC 2014 03/11/2014
Linear Technology LT8614 SilentSwitcher
03/11/2014
Flashing Dome Signal Lights Combine the

Best Functionality Features 03/11/2014
Higher Efficiency AC-DC Full-Brick Power
Modules Have 5 Year Warranty 03/06/2014
12th December
2005,15:03
anjali
Full Member level 3
Join Date:
Aug 2005
Posts:
173
Helped:
14 / 14
Points:
2,436
Level:
11
Re:
Calculation
of
Setup
time
and
Hold
time
even
for
FPGA,
there
will be
tech
specific
librarie
s.
setup
& hold
periods
r given
in
those
libs.
Recently Updated Groups

Digital design the real world, C , VERILOG,
VHDL., Switch Mode Power Supply (SMPS),
VLSI PD- discussion, Embedded C/C++
Programming, Electrical and electronics,
SOLAR POWER, Power Electronics,
Renewable/ Alternate Energy & Power
Converter Design Group, SWITCH mode
power supply
Sponsor
Reply With
Quote
Enter Part Number
12th December
2005,15:46
farhada
Advanced Member level 2
Top Helped / Month

FvM (34), erikl (17), betwixt (16), chuckey
(16), cl10greg (15)
4 of 23
Join Date:
Oct 2004
Location:
Nice, France
Posts:
589
Helped:
85 / 85
Points:
10,314
Level:
24
#5
Calculation
of
Setup
time
and
Hold
time
Take a
look at:
http://w
ww.arl.
wustl.e
du
/~jaf/ha
rdwa...l
culatio
04/11/2014 11:15 AM
n.html
Top Posters
It has a
good
explan
ation
about
how to
calcual
te the
S&H.
FvM (25582), keith1200rs (10883), alexan_e

(10804), IanP (7943), bigdogguru (7314)
Top Experience Points

FvM (162471), IanP (160061), bigdogguru
(58899), keith1200rs (54711), tpetar (54409)
Cheers
,
/Farha
d
1
members
found
this post
helpful.
Reply With
Quote
13th December
2005,06:00
anan_tv
#6
Re:
Calculation
of
Setup
time
and
Hold
time
haii ,
Join Date:
Nov 2005
Location:
Bangalore - INDIA
Posts:
15
Helped:
1/1
Points:
1,365
Level:
I
already
seen
more
websit
es for
the
formula
es.
also
there
are lot
of
variant
5 of 23
04/11/2014 11:15 AM
s in the
formula
es
such
as:
Hold
time <=
shorest
contam
ination
path
delays
<=
propag
ation
delay
<=
clk-Q
delay +
combin
ational
path
delay clk
skew
Setup
time <=
clk
period
-(
clk-Q
delay +
combin
ational
path
delay +
clk
skew)
Also
w.r.t
clock
clk-low
>=
Setup
time
clk-hig
h <=
Hold
6 of 23
04/11/2014 11:15 AM
time
which
of the
above
has to
be
used
for
checki
ng
violatio
ns???
& for
require
ments?
??
[/list]
Reply With
Quote
22nd December
2005,14:15
beckchm
Banned
Join Date:
Nov 2005
Posts:
191
Helped:
3/3
Points:
1,902
Level:
10
#7
Re:
Calculation
of
Setup
time
and
Hold
time
in
general
,
differen
t libs
have
differen
t time
constra
ints.
Reply With
Quote
23rd December
2005,02:51
7 of 23
#8
04/11/2014 11:15 AM
Yun Lin
Member level 4
Join Date:
Apr 2005
Location:
China
Posts:
78
Helped:
5/5
Points:
1,691
Level:
Calculation
of
Setup
time
and
Hold
time
if you
want to
calcula
te, the
simulat
ion can
tell you
the
setup
and
hold
time.
The
setup
and
hold
time is
the
point
that the
functio
n is
fail.
Reply With
Quote
23rd December
2005,13:56
bansalr
Full Member level 2
Join Date:
Dec 2005
Posts:
146
Helped:
17 / 17
Points:
1,871
Level:
10
#9
Re:
Calculation
of
Setup
time
and
Hold
time
The
setUp
and
Hold
time
8 of 23
04/11/2014 11:15 AM
are
defined
by the
Library
vendor
s.
In
FPGA
the
data
sheet
provide
s the
setup
and
hold
time.
Reply With
Quote
24th December
2005,06:33
cfriend
Full Member level 1
9 of 23
Join Date:
Oct 2005
Posts:
97
Helped:
470 / 470
Points:
6,008
Level:
18
#10
Calculation
of
Setup
time
and
Hold
time
Calcula
ting the
setup
and
hold
times
at the
pins of
a chip
I'm
recordi
ng this
informa
tion not
becaus
e it is
difficult
to
rederiv
e, but
04/11/2014 11:15 AM
becaus
e I've
derived
it at
least
twice
now,
and it
always
takes
me
about
half an
hour.
Next
time I
need
this
informa
tion, I'll
know
where
to look
it up
quickly!
Summ
ary
A
positiv
e setup
time
indicat
es a
time
before
the
active
edge of
clock,
a
negativ
e setup
time,
after.
(setup
time at
pin of
whole
chip) =
(setup
time of
flip-flop
data
pin)
10 of 23
04/11/2014 11:15 AM
- (min
clock
delay
from
chip
pin to
FF pin)
+ (max
data
delay
from
chip
pin to
FF pin)
A
positiv
e hold
time
indicat
es a
time
after
the
active
edge of
clock,
a
negativ
e hold
time,
before.
(hold
time at
pin of
whole
chip) =
(hold
time of
flip-flop
data
pin)
+ (max
clock
delay
from
chip
pin to
FF pin)
- (min
data
delay
from
chip
11 of 23
04/11/2014 11:15 AM
pin to
FF pin)
Details
Suppo
se that
you
have a
chip
with a
data
input
pin
whose
signal
goes
throug
h some
delay
on chip
(e.g.,
the
input
pad,
RC
delay
on the
wire to
a FF
(flip-flo
p)
input,
some
logic
inserte
d
expres
sly for
adding
delay)
before
being
sample
d at a
FF.
This
FF
respon
ds to
active
edges
of a
clock
pin,
12 of 23
04/11/2014 11:15 AM
which
is also
delaye
d
before
it
reache
s the
FF
clock
input.
Given
the
setup
and
hold
times
of the
FF
data
input
relative
the the
FF
clock
input,
what
are the
setup
and
hold
times
of the
pin A
relative
to the
the pin
CK of
the
chip?
Here
are
some
abbrevi
ations
used
below:
cf time
when
active
edge
13 of 23
04/11/2014 11:15 AM
occurs
on
Clock
pin of
Flip-flo
p
cc time
when
active
edge
occurs
on
Clock
pin of
the
whole
Chip
df time of
a
transiti
on on
Data
input of
Flip-flo
p
dc time of
a
transiti
on on
Data
input of
the
whole
Chip
Let's
specify
the
setup-h
old
window
of the
FF as
follows.
The FF
will
reliably
sample
the
data
input
as its
next
14 of 23
04/11/2014 11:15 AM
state
as long
as the
data
input of
the FF
remain
s
stable
in the
interval
[cf-fset
up,
cf+fhol
d], or:
df is
not in
[cf-fset
up,
cf+fhol
d]
Alterna
tely:
(df < cf
fsetup)
(1)
OR
(df > cf
+
fhold)
(2)
then
the FF
will
reliably
sample
the
data
input
as its
next
state.
Also
suppos
e that
the
delay
from a
transiti
on on
the
15 of 23
04/11/2014 11:15 AM
data
pin of
the
whole
chip to
a
transiti
on on
the
data
input of
the FF
is in
the
range
[dmin,
dmax].
Stated
anothe
r way:
(dc+d
min <=
df) (3)
AND
(df <=
dc+dm
ax) (4)
Finally,
suppos
e that
the
delay
from
an
active
transiti
on on
the
clock
pin of
the
whole
chip to
an
active
transiti
on on
the
clock
input of
the FF
is in
the
16 of 23
04/11/2014 11:15 AM
range
[cmin,
cmax].
(cc+cm
in <=
cf) (5)
AND
(cf <=
cc+cm
ax) (6)
Now,
we
wish to
determi
ne the
smalle
st
interval
that the
data
pin of
the
whole
chip
must
be
stable,
of the
form
[cc-cse
tup,
cc+cho
ld], to
guaran
tee that
the FF
data
pin
meets
its
setup
and
hold
times.
I'm
going
to
derive
these
"backw
ards",
with a
17 of 23
04/11/2014 11:15 AM
sequen
ce of
statem
ents of
the
form:
statem
ent 1
<== {
reason
1}
statem
ent 2
<==> {
reason
2}
statem
ent 3
This
means
that
statem
ent 2
implies
that
statem
ent 1 is
true,
with
any
justifica
tion or
comme
nts
given
as
reason
1. It
also
means
that
statem
ent 2 is
true if
and
only if
statem
ent 3 is
true,
with
any
justifica
tion
18 of 23
04/11/2014 11:15 AM
given
as
reason
2.
Here
we go,
for the
setup
time:
df < cf
- fsetup
<== {
(4) }
(dc+d
max) <
cf fsetup
<== {
(5) }
(dc+d
max) <
(cc+cm
in) fsetup
<==> {
algebra
}
dc < cc
(fsetup
- cmin
+
dmax)
The
final
result
implies
that the
setup
time at
the
whole
chip is
(fsetup
- cmin
+
dmax),
as
summa
rized at
the
beginni
19 of 23
04/11/2014 11:15 AM
ng.
Now
for the
hold
time,
which
is
derived
almost
identic
ally:
df > cf
+ fhold
<== {
(3) }
(dc+d
min) >
cf +
fhold
<== {
(6) }
(dc+d
min) >
(cc+cm
ax) +
fhold
<==> {
algebra
}
dc > cc
+
(fhold
+ cmax
- dmin)
The
final
result
implies
that the
setup
time at
the
whole
chip is
(fhold
+ cmax
dmin),
as
summa
rized at
the
20 of 23
04/11/2014 11:15 AM
beginni
ng.
Added
after
35
second
s:
http://w
ww.arl.
wustl.e
du
/~jaf/ha
rdwa...l
culatio
n.html
Reply With
Quote
#11
24th December
2005,20:13
Resistance
Member level 4
Join Date:
Dec 2005
Posts:
74
Helped:
5/5
Points:
1,776
Level:
Re:
Calculation
of
Setup
time
and
Hold
time
Hi,
Set up
times
and
hold
times
of a
flop or
latch
are
specifi
ed by
the
vendor.
.
but
these
21 of 23
04/11/2014 11:15 AM
depend
on the
technol
gy u
would
be
choosi
ng and
many
more
factors.
.
but set
up
times
for a
port(in
put or
output)
is
differen
t and
ought
to
estimat
ed by
the
user..
ru
interest
ed in
that?
Plus
for
FPGA
and
ASIC
dont
have
diff
concep
ts for
set and
hold
times..
may be
the
values
may
differ .
plus if
22 of 23
04/11/2014 11:15 AM
u are
taking
about
pin set
up
times
then
differen
ce
does
exist..
Reply With
Quote
Please
login
+ Post
New Thread
conceptual objective questions in
DIGITAL DESIGN.. | Can the netlist info
guide to the technology library?
Similar Threads
How are we calculating the setup time &
hold time of a f (11)
If setup time is met, so how hold time
violation maybe occur (1)
setup and hold time calculation for a flop
(5)
what happens if hold time greater than
setup time (6)
Examples of setup time and hold time (12)
-- Edaboard Classic
Contact Us Forum for Electronics Privacy Statement

Terms of Service Top
All times are GMT +1. The time now is 06:22.
Powered by vBulletin
Copyright 2010 vBulletin Solutions, Inc. All rights reserved.
SEO by vBSEO 2011, Crawlability, Inc.
23 of 23
04/11/2014 11:15 AM

Setup and Hold Basics - 1 PDF

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Setup and Hold Basics - 1 PDF

Uploaded by

Copyright:

Available Formats

Calculation of Setup time and Hold time

Digital Design and Programming

ASIC Design Methodologies and Tools (Digital)

+ Post New Thread

Junior Member level 1

lvision model generation for clock

Interfacing rtc(ds1307) pic24f

Threads Without Replies

Calculation of Setup time and Hold time

9th December 2005,10:12

Posted By Ranjitharanju. Today 05:56 in

HFSS field calculator

help required -- HFSS to Gerber

12th December 2005,15:46

Posted By shilpa.k. Today 05:44 in Electromagnetic

How design the encapsulation M-bus in

Hello, As I am novice in embedded sofware

Precision Metal Parts

Posted By hajeur. Today 05:34 in Analog Circuit

Calculation of Setup time and Hold time

EE News, Tips and Resources

Sine Wave Generation 03/21/2014

Calculation of Setup time and Hold time

Altera Introduces OTN Solutions for 400G and

Flashing Dome Signal Lights Combine the

Recently Updated Groups

Enter Part Number

Top Helped / Month

Calculation of Setup time and Hold time

FvM (25582), keith1200rs (10883), alexan_e

Top Experience Points

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Calculation of Setup time and Hold time

Contact Us Forum for Electronics Privacy Statement

You might also like