ELEN 475 Lab 4

Cadence Custom Layout - Simulation

1. Introduction
In today's lab we will extract the layout of the inverter we created last week and simulate it using Spectre. For this you
will need MOS models, so copy the two files cell30.spi, model25.spi, and spicemodel.spi from my website to
your cadence/models directory. If you do not have models directory, create it.

2. Layout extraction
1. In this section we will extract the second inverter layout drawn in last lab with minimum design rules. We can
simulate it using Spectre later.
2. Open the layout view of the myinverter cell in edit mode. Make sure you have done the substrate contacts and pins
correctly; without this you cannot extract.
3. Run DRC again to see there are design rule errors. Fix them at this point if there are any.
4. Choose Verify -> Extract in the layout window, Extract form appears. Click on OK and the extraction process starts.
5. After some messages are displayed in the CIW, the extracted view is created and can be seen in the Browser. Open
the extracted view in read mode, click shiftf, you can see two transistors and the width and length of the transistor
are shown on the graph. The original view is restored when you click ctrlf.
(If you zoom in near one of the transistors, choose Edit Properties and click on the region near the transistor, then The
Edit Instance Properties form appears; click the Parameter field and you can see the width, length, area of drain and
source diffusion (ad and as respectively) etc. However, this value is the default minimum value for this technology, and
they do not change. You can see the width is different from width shown on the graph. You will find that if you change
your channel width of your layout, the value in Parameter field do not change, but if you click shift-f, that value will
change. Please always write down the value shown by clicking shiftf. )

3. Circuit Simulation with Spectre

1. In one of the previous labs, we did logic simulation using Verilog XL simulator. However, as mentioned before logic
simulation does not have any timing information extracted from the circuit. In the actual circuit, due to parasitic
capacitance, the waveforms appearing at the output are not ideal (as we will see in this lab). This timing information is
captured by circuit simulation (using SPICE). In this section we will use Spectre for circuit simulation, which is almost
the same as SPICE.
2. Spectre is an advanced circuit simulator that simulates analog and digital circuits at the differential equation level.
The simulator uses improved algorithms that offer increased simulation speed and greatly improved convergence
characteristics over SPICE. Besides the basic capabilities, the Spectre circuit simulator provides significant additional
capabilities over SPICE. In this lab, we do not have time to learn the whole software. Instead, you will learn how to
write a spice format netlist consisting of transistors, resistors and capacitors. You will also learn how to do the timing
simulation with Spectre. In later labs, you will still use it to write a spice format file by yourself and do the time
simulation. For the help of Spectre, you can check /baby/cadence/ic50/doc/spectreref/spectreref.pdf and
/baby/cadence/ic50/doc/spectreref/spectreuser.pdf

3. Spice uses several models of the MOS for simulation, for example, level 1 model, level 2 model, BSIM model and so
on. These models define various parameters, which spice uses for simulation. We will be using BSIM level 3.1 models
for our simulation, which is defined in model25.spi(The technology is TSMC 0.25 um. If you want to know more
about device model information, go to http://www.mosis.com/Technical/Testdata/tsmc-025-prm.html, look at
T14Y_LO_EPI).
4. Go to your ~/cadence/models directory, open spicemodel.spi file. In spicemodel.spi, you will find following
texts
//Spice netlist for an inverter and a capacitor
simulator lang=spectre
include "~/course/elen475/models/model25.spi"
include "~/course/elen475/models/cell30.spi"
vgnd (gnd 0) vsource dc=0
vvdd (vdd 0) vsource dc=3
vpulse1 (IV_in 0) vsource type=pulse val0=0 val1=3 period=4n width=2n
X1 (IV_in IV_out vdd gnd) IV
C1 (IV_out 0) capacitor c=0.05p
TransientAnalysis tran start=0 stop=60ns step=1ps
save IV_in IV_out
The first line is the title. Note that anything put in the first line will be taken as comments by Spectre. You can also use
* or // to comment one line.
The second sentence tells the Spectre that the language used in this file is Spectre format. The third line and forth line
defines the power and ground voltage. Include commands are used to include subcircuit and device model files that
will be used in this lab. Note that the general format for any instance is Name [() node1 nodeN []] master
[[param1=value1] [paramN=valueN]], where Name is the instance name, node1, nodeN tells the nodes
connected to the component, master tells the component is a built-in premitive (like vsource, resistor, capacitor) or a
subcircuit, param is the parameter information associated with this component. [] means the option inside is not
necessary.
The sentence vpulse1 (IV_in 0) vsource type=pulse val0=0 val1=3 period=4n width=2n defines a voltage source
vpulse1. It connects between IV_in terminal and ground, and is a voltage source (vsource). The type is a pulse signal.
Val0 defines the low voltage, and val1 defines the higher voltage. Period defines the period of the pulse signal, and
width defines the duration of vol1 value in one cycle.
The sentence X1 IV_in IV_out vdd gnd IV creates a inverter (IV) instance X1. The definition of IV can be found in
cell30.spi. In cell30.spi, a p-mos transistor and an nmos transistor are claimed. The sentence M1 (output input
VDD VDD) tsmc25P w=wp l=lp claim a pmos transistor M1 using device model tsmc25P (defined in model25.spi).
The general format of mos transistor is Name (d s g b) devicemodel w=... l =. w is channel width and l is
channel length. You need to change the width and length of the transistor to be the values you got from
extraction from your layout.
The sentence C1 (IV_out 0) capacitor c=0.05p connect a capacitor with value 0.05pF to the output of the inverter.
The sentence TransientAnalysis tran start=0 stop=60ns step=1ps tells Spectre to do Transient analysis (tran) from 0ns
to 100ns that computes the transient response of the circuit over a specified time interval. Spectre can also do some
other analysis, such as dc/ac analysis, noise analysis, and RF analysis.

The sentence save IV_in IV_out tells Spectre to save the voltage waveform of these two nodes.
5. After you set the transistor width and length value in cell30.spi, type spectre spicemodel.spi from terminal. If
you meet errors, please ask TA. If there is no error, you will see simulation information displayed and the final line is
like spectre complete with 0 errors, xx warnings, . The waveform display tool for Spectre is AWD (Analog
Waveform Display), a display tool you receive when you purchase the Spectre simulator. Type awd & from the
terminal. Click OK in the Browse Project Hierarchy form. Once AWD is running, four windows appear on your screen,

Command Interpreter Window (CIW).

Calculator window

Waveform Window

Results browser.
6. In the Results Browser, scroll, if necessary, until spicemodel.raw is visible and then click on spicemodel.raw by
middle key and choose Create ROF. Then click on spicemodel.raw by left mouse key, then you can see the names of
waveform you just saved. To display a waveform, click on its name in the Results Browser with the right mouse button.
Then the waveform appears in Waveform Window. You can zoom in and zoom out from Zoom.
7. Compute the delay. There are several ways to define the delay. In general, delay is defined as the time from 50%
point of the input waveform to 50% point of the output waveform. In this lab, since the vdd is set to 3v, then we will
use 1.5v as 50% point for both input and output waveform (sometimes output may have value bigger than 3v or smaller
than 0v. So 1.5v chosen as 50% point for output is an acceptable approximation). Choose Markers > Horizontal
Marker, enter 1.5 at Maker location shown as follows. Click Apply, then click Display Intercept Data.

A window will pop up, as shown in next page, in which the time when the saved waveform achieved 1.5v is shown for
each curve. The rising delay (rising here corresponds to input, not output) can be computed by taking the difference of
the time when output falls to 1.5v and the time when input rise to 1.5v. Falling delay can be computed as the same way.
The data in this window can be saved to a file by choosing File > Save as and you can print it out using lp
command.
8. Record the difference of the falling delay and rising delay. Try to adjust your layout and use the new extracted
transistor information to make the falling delay and rising delay as close as possible ( If the difference between rising

and falling delay is about 10%,it is enough. If you cannot make it in 10%, try to make the difference smaller). Note that
you cannot open awd and icfb at the same time. After you change the layout, you must exit icfb and then open awd.
p W p
(
) , the gain
After you change your spice file, you need run Spectre again. The gain of Pmos transistor is p =
t ox L p
of Nmos transistor is n =

n Wn
t ox

Ln

) . p and n are the effective surface mobility of the carriers in the channel. You

can find p and n at model25.spi, the parameter is U0. Note that they are different for Nmos and Pmos. is the
permitivity of the gate insulator, and tox is the thickness of the gate insulator. These two parameters are same for Nmos
and Pmos for this technology. W and L are the width and length of the channel, respectively.

4. Report Requirement
1. Print extracted view of myinverter layout (please print the extracted view of the final layout that makes the falling
delay and rising delay as close as possible). Print out the timing information file (got from AWD by setting marker and
choose display intercept data) and show your falling and rising delay in the report.
2. Draw an NAND layout with minimum design rules. Extract your layout and get parasitic parameters of your gate.
Then use Spectre to simulate the NAND gate. Note that in cell30.spi, I already put an ND2 subcircuit there. You
need change spicemodel.spi to claim a ND2 instance, and connect a 0.05p capacitance to its output. You can connect
one input to vdd and another input to a pulse signal so that you can see the output transitions between 1 and 0. Adjust

your layout to make the rising and falling delay as close as possible. Print the layout view of nand gate and extracted
view of nand layout. Print out your timing information file and show your falling and rising delay in the report.
3. Change the load capacitor to 0.10pF for NAND gate. Run Spectre again with the same parameter, print out your
timing information file and show your falling and rising delay in the report.