Curriculum vitae

VEMULA HARINI
D/O: V PULLAIAH
F.NO:304, VIJETHA SUJAYA ENCLAVE,
ROAD NO:4, SRI KRISHNA NAGAR,
DILSUKHNAGAR,
HYDERABAD – 60. Contact No. : 09036731438, 09966032700.

Email ID : harini040@gmail.com

CAREER OBJECTIVE:
To be associated with a progressive organization that would give me a scope to apply
my knowledge and skills and to seek an opportunity to enhance my capability to keep
abreast with the emerging challenges.

Academic Qualifications

EXAMINATION INSTITUTION BOARD PERCENTAGE YEAR

M. Tech
VIT, Vellore, VIT 2008-2010
(Communication 9.01(CGPA)
Tamil Nadu. University (pursuing)
engineering)

B. Tech BRECW, Hyderabad 2004-2008

J.N.T.U 76.57
(ECE) A.P.

Sri chaitanya junior

Intermediate college,
B.I.E 85.8 2002-2004
(M.P.C) Miyapur
A.P.
CRRHS
10th Standard S.S.C 88 2001-2002
Kurnool, A.P.

Technical Knowledge

Languages : C& DS
Electronics related software : MATLAB, Cadence, HSPICE tool and JMP tool.
Area of interest : Communication systems and Memory.
Projects Summary

B. Tech Project :
Title : Symbol rate estimation of digital modulated signal
Using wavelet transform.
Duration : 45 Days
Project Description:
In electronic warfare applications, there is a need to identify digital modulation
types of an incoming signal and subsequently perform demodulation, where no a priori
information about a signal is available. Demodulation of a digital modulated waveform
requires the symbol rate of a received signal which is not known previously. The use of
wavelet transform to estimate the symbol rate of a BPSK, QPSK, 8PSK, 8QAM, 16QAM
signals. The idea is to wavelet transform to locate the transients gives a symbol rate.
Transients are nothing but the phase changes in the signal and after apply FFT to signal to
get frequency response by which we can peak value better and to get periodicity in the
signal, and the fundamental peak in the spectrum gives estimate of ‘Symbol Rate’.

M. Tech Project (WIP):

Title : Design, Validation and Correlation of Characterized
SODIMM modules supporting DDR3 interface.
Organization : INTEL as an Intern in SI team in MG.
Duration : 9 months.
Project Description:
In any computing environment, it is necessary for the processor to have fast
accessible RAM that allows temporary storage of data. As the processing power increased
manifold- the need for faster, reliable and denser memory keeps increasing. In most of the high
end computing systems today, DDR3 is the standard memory interface which supports higher
bandwidth and speed, at lesser power. DDR3- SODIMM module is a key component in the
memory interface and is becoming increasingly important in enabling higher speeds. Intel is
driving Characterized SODIMM module design to understand and analyze the impact of
SODIMM parameters at higher speeds and thereby define more robust memory interface. This
will include simulation , board design , validation and results correlation and involves high
speed simulation and validation methodologies.
Extracurricular Activities & Awards

 Participated in IEEE section student congress seminar.

 Secured RUNNERS place in Volleyball competition 2002.
 Received merit awards four times in B. Tech.
 Received merit award once in M. Tech.
Personal profile

Name : V Harini
Date of Birth : 25-10-1987
Father’s Name : V Pullaiah
Nationality : Indian
Marital Status : Single
Languages Known : English and Telugu
Hobbies : YOGA , Playing Volleyball .

Declaration

I here by declare that all the above information given by me is true up to my knowledge and I
hope that I can successfully get my attitude under your guidance.
Date:
Place: (V. HARINI)