2 Discrete Logic Design

Elijah Akins 900717110

September 11, 2012

Abstract
The goal of Lab 2 is to familiarize students with the tangible execution of digital
logic using discrete components. In pursuit of this goal, students will refresh
themselves on the implementation of Karnaugh1 maps to simplify logical constructs. Physical implementation of these designs will manifest themselves on a
protoboard2 instead of a FPGA3 . These procedures will solidify the fundamentals of combination design that students will rely on for the rest of the course.
Students will also gain familiarity in circuit construction and troubleshooting
techniques used to implement on protoboards. Additionally, students will learn
adequate preparation and organization that is integral to accurately and efficiently construct, verify, and troubleshoot designed circuits.

1 A Karnuagh map also colloquially know as a Kmap is used as a visual aid to simply
boolean algebra by hand. It is eponymously named for Maurice Karnaughs 1953 refinement
of Edward Veitchs 1952 Veitch diagram.
2 Used for solderless construction of prototype circuits
3 Field Programmable Gate Array.

Contents
1 Introduction and Background
1.1 Logic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Protoboard circuit construction . . . . . . . . . . . . . . . . . . .
1.3 Switches and pull-up resistors . . . . . . . . . . . . . . . . . . . .

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2 Theory

3 list of Equipment Used

4 Overview of Procedure

5 Required Data

6 Analysis of Required Data

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7 Conclusion

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List of Figures
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CMOS HCT dual inline package . . . . . . . . . . . . . .

Typical protoboard . . . . . . . . . . . . . . . . . . . . . .
Trivial example of pull-up resistor in situ . . . . . . . . .
74HCT00 Function diagram . . . . . . . . . . . . . . . . .
74HCT00 Logic diagram . . . . . . . . . . . . . . . . . . .
74HCT04 Function diagram . . . . . . . . . . . . . . . . .
74HCT04 Logic diagram . . . . . . . . . . . . . . . . . . .
74HCT20 Function diagram . . . . . . . . . . . . . . . . .
74HCT20 Logic diagram . . . . . . . . . . . . . . . . . . .
Logic Table, Karnaugh map, and schematics . . . . . . . .
Annotated block diagram schematic created in Quartus II
Oscilloscope output . . . . . . . . . . . . . . . . . . . . . .

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Introduction and Background

This Laboratory requires knowledge in the use of protoboard as well as switches.

These topics are covered in the following subsections. An understanding of
Karnaugh maps is essential, however the instruction of their use is beyond the
scope of this report.

1.1

Logic thresholds

In ones first digital theory class, logical values are introduced as a binary system
consisting of 0 and 1. While this is a useful abstraction, these values appear
as unique voltage ranges4 in real-world circuits. The particular technology we
will concern ourselves with in this lab is Transistor-Transistor Logic, initialized
as TTL. TTL is named for the transistors5 that perform both logic gate operation and amplification. TTL is powered by +5 V. The logical threshold voltage
for low and high is 0.8 V and 2 V respectively. Voltage values between aforementioned voltages within some tolerance results in an undefined logical
function with unpredictable behavior. This undefined state is to be avoided,
which due to the proliferation and adherence to the TTL Standard is trivial
across both time and manufacturer. While TTL is fairly ubiquitous, it is not
suited to high density integrated circuits. In high density circuits, complementary metal-oxide semiconductors, or CMOS, has become the standard. One
advantage of CMOS is the ability to operate at varying voltages. An application of this is to have CMOS devices powered at a low voltage, thusly reducing
the power consumed and heat produced as a result. In this lab we will use logic
components from the CMOS HCT6 family.

Figure 1: CMOS HCT dual inline package

4 Voltage

ranges vary with the physical implementation technology of logic devices

contrast to resistor-Transistor Logic and Diode-Transistor Logic
6 High-speed CMOS with TTL-compatible levels
5 In

1.2

Building circuits on protoboards

In this lab we will use prototyping circuit board, or protoboard. While other
methods of prototyping exist7 , protoboards are reusable, cheap, and efficient;
thus explaining their popularity. Protoboards conistis of a plastic or ceramic
grid and conductive elements below the grid. The grid aligns either DIPs8 or
jumper wires inserted through the grid.

Figure 2: Typical protoboard

DIPs are inserted straddling the grey channel in Figure 2. Each row under
A B C D E and F G H I J are each respectively electrically common. This
allows for multiple jumper wire to interface not only with each other but also
with the pins of the inserted DIP. The pins of a DIP are numerically labeled in a
specific order, starting with the top left number 1 pin and increasing counter
clock-wise. The top of the DIP is easily recognized as such by an indented circle
or half circle. This feature is clearly visible on the DIP in Figure 1. Also of
notice on the protoboard are the buses. The buses are recognized in Figure 2 by
the horizontal blue and red lines. The pins closest to the lines are electrically
common. This allows for the convenient distribution of either power, ground,
or signals.

1.3

Switches and pull-up resistors

The simplest form of input is realized by a physical switch. Consequently, this

is how we will implement input in the lab. Specifically, we will use push-button
and slide switches. While there are many switch configurations, we will concern
ourselves with the two types present in the lab.

7 Stripboard,
8 Dual

point-to-point construction, wire wrap and wiring pencil

Inline Package

1. momentary, normally-open switch

Momentary refers to the switch contacts only in contact for the duration
of the articulation. Normally-open refers to the switch contacts not in
contact while the switch is not actively articulated.
2. single-pole, single-throw (SPST)
Single-pole refers to a single contact made by the switch in the connecting
position. Single-throw refers to the switch being thrown in one direction.
Pull-Up resistors in digital logic refer to resistors specifically placed to keep
logical input from connecting ground to VCC9 . In effect, these pull-up resistors
prevent components from having too much current which can damage logical
components as well as the power supply. The resistors also limit the voltage
provided to logical inputs on the DIPs. Refer to Figure 3 for an example of a
pull-up resistor in use.

Figure 3: Trivial example of pull-up resistor in situ

Theory

After simplification of the table provided for the lab via Karnaugh map and the
transformation into NAND gates, appropriate DIPs are specified. To implement
the function, 3 DIPS from the HCT family are used. Shown below are the
function diagram followed by the pin layout for each respective DIP.

9 Voltage

Controlled Current Source. The power source in most digital designs

1. 74HCT00 Quad 2-input NAND gate

Figure 4: 74HCT00 Function diagram

Figure 5: 74HCT00 Logic diagram

2. 74HCT04 Hex inverter

Figure 6: 74HCT04 Function diagram

Figure 7: 74HCT04 Logic diagram

3. 74HCT20 Dual 4-input NAND gate

Figure 8: 74HCT20 Function diagram

Figure 9: 74HCT20 Logic diagram

list of Equipment Used

1. 4 DIPs
(a) 74hct00
(b) 74hct04
(c) 74hct20
(d) 74hct7410
2. CADET station11
3. jumper wires
4. oscilloscope
5. 2 1k resistors

Overview of Procedure

The laboratory procedures have been noted below as a brief overview. If further
explanation is needed, it is recommended to reference Lab 2 in the Digital Design
Laboratory Manual.
1. Properly insert all three DIPs into the breadboard.
2. Connect all ground and power to each DIP.
3. Connect jumpers to correct pins using reference diagrams.
4. Connect Switches and LEDS.
5. Verify accuracy of logical operation.

Required Data

10 We

will use this DIP in a separate circuit constructed later.

containing breadboard, LEDs, switches, and power supply.

11 Apparatus

Figure 10: Logic Table, Karnaugh map, and schematics

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Figure 11: Annotated block diagram schematic created in Quartus II

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Figure 12: Oscilloscope output

Analysis of Required Data

In Figure 10, The given logic table was simplified by a Karnaugh map. This
may be feasible for simple logical constraints, however more complex logic simplification is achieved using computer programs that employ sophisticated algorithms12 . The schematic created in Quartus, Figure 11, has been annotated
with the pin numbers of each logical representation. This organization is vital
to construct the circuit in an efficient manner. One will also find troubleshooting to be easier with good documentation. Figure 12 shows a square wave.
This signal was created by the oscilloscope to calibrate itself using known signal
values.
12 Ex

Espresso algorithm.

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Conclusion

This lab has refreshed old skills and built a solid foundation for new ones.
The logic simplification process reviews techniques such as Karnaugh maps and
technology mapping. The breadboard apparatus was introduced along with the
HCT family of CMOS chips; also touched upon briefly was the oscilloscope,
a device for visualizing signals. While all of these experiences presented new
challenges, one of the greatest lessons learned from this lab is the importance
of having a structured, and detailed plan of operation to simply, construct, and
verify your circuits.

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References
Digital Design Laboratory Manual Twigg, Collins
Rapid Prototyping of Digital Systems Hamblen, Furman
74HCT00 Data-sheet NXP Conductors
74HCT04 Data-sheet NXP Conductors
74HCT20 Data-sheet NXP Conductors

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