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Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC
z 8 Single-ended Channels
z 7 Differential Channels in TQFP Package Only
z 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
Byte-oriented Two-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
Operating Voltages
2.7 - 5.5V
Speed Grades
0 - 16MHz
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
Pin Configurations
Pinout ATmega16A
PDIP
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
TQFP/QFN/MLF
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
NOTE:
Bottom pad should
be soldered to ground.
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PD3
PD4
PD5
PD6
PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
Figure 1-1.
(INT1)
(OC1B)
(OC1A)
(ICP1)
(OC2)
1.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
2.
Overview
The ATmega16A is a low-power CMOS 8-bit microcontroller based on the Atmel AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega16A achieves throughputs
approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PA0 - PA7
PC0 - PC7
PORTA DRIVERS/BUFFERS
PORTC DRIVERS/BUFFERS
VCC
GND
AVCC
MUX &
ADC
ADC
INTERFACE
TWI
AREF
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
TIMERS/
COUNTERS
OSCILLATOR
INTERNAL
OSCILLATOR
XTAL1
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
WATCHDOG
TIMER
OSCILLATOR
XTAL2
X
INSTRUCTION
DECODER
MCU CTRL.
& TIMING
RESET
CONTROL
LINES
ALU
INTERRUPT
UNIT
AVR CPU
STATUS
REGISTER
EEPROM
PROGRAMMING
LOGIC
SPI
USART
+
-
INTERNAL
CALIBRATED
OSCILLATOR
COMP.
INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
PB0 - PB7
PD0 - PD7
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient
while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega16A provides the following features: 16Kbytes of In-System Programmable Flash Program
memory with Read-While-Write capabilities; 512bytes EEPROM; 1Kbyte SRAM; 32 general purpose I/O lines,
32 general purpose working registers; a JTAG interface for Boundary-scan; On-chip Debugging support and
programming; three flexible Timer/Counters with compare modes; Internal and External Interrupts; a serial
programmable USART; a byte oriented Two-wire Serial Interface, an 8-channel; 10-bit ADC with optional
differential input stage with programmable gain (TQFP package only); a programmable Watchdog Timer with
Internal Oscillator; an SPI serial port; and six software selectable power saving modes. The Idle mode stops the
CPU while allowing the USART; Two-wire interface; A/D Converter; SRAM; Timer/Counters; SPI port; and
interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save
mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous
Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run.
The device is manufactured using Atmels high density nonvolatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional
nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program
can use any interface to download the application program in the Application Flash memory. Software in the
Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega16A is a powerful microcontroller that provides a highly-flexible and costeffective solution to many embedded control applications.
The ATmega16A is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
2.2
2.2.1
Pin Descriptions
VCC
Digital supply voltage.
2.2.2
GND
Ground.
2.2.3
Port A (PA7:PA0)
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide
internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics
with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled
low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
2.2.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega16A as listed on page 57.
2.2.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled,
the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
Port C also serves the functions of the JTAG interface and other special features of the ATmega16A as listed on
page 59.
2.2.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16A as listed on page 62.
2.2.7
RESET
Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the
clock is not running. The minimum pulse length is given in Table 27-2 on page 282. Shorter pulses are not
guaranteed to generate a reset.
2.2.8
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
2.2.9
XTAL2
Output from the inverting Oscillator amplifier.
2.2.10
AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even
if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.2.11
AREF
AREF is the analog reference pin for the A/D Converter.
3.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
Note:
4.
1.
Data retention
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over
20 years at 85C or 100 years at 25C.
5.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
6.
AVR CPU
6.1
Overview
This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform calculations,
control peripherals, and handle interrupts.
Figure 6-1.
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with separate
memories and buses for program and data. Instructions in the program memory are executed with a single level
pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is In-System
Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two
operands are output from the Register File, the operation is executed, and the result is stored back in the
Register File in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing
enabling efficient address calculations. One of the these address pointers can also be used as an address
pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register.
Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is
updated to reflect information about the result of the operation.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that
writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The
Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the
total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before
subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The
data SRAM can easily be accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit
in the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts
have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher
the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the
Register File, $20 - $5F.
6.2
6.3
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction.
This information can be used for altering program flow in order to perform conditional operations. Note that the
Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in
many cases remove the need for using the dedicated compare instructions, resulting in faster and more
compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
6.3.1
Bit
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SREG
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
The S-bit is always an exclusive or between the Negative Flag N and the Twos Complement Overflow Flag V.
See the Instruction Set Description for detailed information.
Bit 3 V: Twos Complement Overflow Flag
The Twos Complement Overflow Flag V supports twos complement arithmetics. See the Instruction Set
Description for detailed information.
Bit 2 N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
Bit 0 C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for
detailed information.
6.4
Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
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Figure 6-2.
Addr.
R0
$00
R1
$01
R2
$02
R13
$0D
General
R14
$0E
Purpose
R15
$0F
Working
R16
$10
Registers
R17
$11
R26
$1A
R27
$1B
R28
$1C
R29
$1D
R30
$1E
R31
$1F
Most of the instructions operating on the Register File have direct access to all registers, and most of them are
single cycle instructions.
As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the
first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this
memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers
can be set to index any register in the file.
6.4.1
X - register
XH
XL
0
R27 ($1B)
15
Y - register
YH
YL
0
R28 ($1C)
15
ZH
R31 ($1F)
R26 ($1A)
R29 ($1D)
Z - register
ZL
7
0
0
R30 ($1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic
increment, and automatic decrement (see the Instruction Set Reference for details).
6.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower
memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
11
the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will
decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or
interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack
Pointer must be set to point above start of the SRAM, see Figure 7-2 on page 17.
See Table 6-1 for Stack Pointer details.
Table 6-1.
Instruction
Stack pointer
Description
PUSH
Decremented by 1
CALL
ICALL
RCALL
Decremented by 2
POP
Incremented by 1
RET
RETI
Incremented by 2
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used
is implementation dependent. Note that the data space in some implementations of the AVR architecture is so
small that only SPL is needed. In this case, the SPH Register will not be present.
6.5.1
Bit
Read/Write
Initial Value
6.6
15
14
13
12
11
10
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
12
Figure 6-4.
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 6-5.
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
6.7
ATmega16A [DATASHEET]
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13
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by
writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global
interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not
necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the
interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will
be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following
example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
C Code Example
char cSREG;
cSREG = SREG;
store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
/*
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any
pending interrupts, as shown in this example
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
14
.
Assembly Code Example
sei
; set global interrupt enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set global interrupt enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s)
*/
6.7.1
ATmega16A [DATASHEET]
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7.
AVR Memories
7.1
Overview
This section describes the different memories in the ATmega16A. The AVR architecture has two main memory
spaces, the Data Memory and the Program Memory space. In addition, the ATmega16A features an EEPROM
Memory for data storage. All three memory spaces are linear and regular.
7.2
$0000
7.3
ATmega16A [DATASHEET]
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The lower 1120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM.
The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the
internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect,
Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature
the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Zregister.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the
ATmega16A are all accessible through all these addressing modes. The Register File is described in General
Purpose Register File on page 10.
Figure 7-2.
R0
R1
R2
...
$0000
$0001
$0002
...
R29
R30
R31
I/O Registers
$00
$01
$02
...
$001D
$001E
$001F
$3D
$3E
$3F
$005D
$005E
$005F
Internal SRAM
$0060
$0061
...
$0020
$0021
$0022
...
$045E
$045F
7.3.1
ATmega16A [DATASHEET]
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Figure 7-3.
T2
T3
clkCPU
Address
Compute Address
Address Valid
Write
Data
WR
Read
Data
RD
7.4
Next Instruction
7.4.1
7.4.2
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7.4.3
7.5
I/O Memory
The I/O space definition of the ATmega16A is shown in Register Summary on page 319.
All ATmega16A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and
OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O
Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
Instruction Set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses
$00 - $3F must be used. When addressing I/O Registers as data space using LD and ST instructions, $20 must
be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will
operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI
and SBI instructions work with registers $00 to $1F only.
The I/O and Peripherals Control Registers are explained in later sections.
ATmega16A [DATASHEET]
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7.6
7.6.1
Register Description
EEARH and EEARL The EEPROM Address Register
Bit
Read/Write
Initial Value
15
14
13
12
11
10
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MSB
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
EEDR
EERIE
EEMWE
EEWE
EERE
Read/Write
R/W
R/W
R/W
R/W
Initial Value
EECR
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zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the
bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
Bit 1 EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are
correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must
be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The
following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEWE becomes zero.
2.
3.
4.
5.
Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6.
Within four clock cycles after setting EEMWE, write a logical one to EEWE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that
the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the
software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by
the CPU, step 2 can be omitted. See Boot Loader Support Read-While-Write Self-Programming on
page 237 for details about boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write
Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM Access, the
EEAR or EEDR reGister will be modified, causing the interrupted EEPROM Access to fail. It is recommended to
have the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this
bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles
before the next instruction is executed.
Bit 0 EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is
set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The
EEPROM read access takes one instruction, and the requested data is available immediately. When the
EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is
neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 7-1 lists the typical programming time for
EEPROM access from the CPU.
Table 7-1.
8448
8.5ms
Note:
1.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples
assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur
during execution of these functions. The examples also assume that no Flash Boot Loader is present in the
software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to
finish
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.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic
EECR,EEWE
rjmp
EEPROM_write
; Set up address (r18:r17) in address register
out
EEARH, r18
out
EEARL, r17
; Write data (r16) to data register
out
EEDR,r16
; Write logical one to EEMWE
sbi
EECR,EEMWE
; Start eeprom write by setting EEWE
sbi
EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that
interrupts are controlled so that no interrupts will occur during execution of these functions
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.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic
EECR,EEWE
rjmp
EEPROM_read
; Set up address (r18:r17) in address register
out
EEARH, r18
out
EEARL, r17
; Start eeprom read by writing EERE
sbi
EECR,EERE
; Read data from data register
in
r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
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8.
8.1
Clock Distribution
Asynchronous
Timer/Counter
General I/O
Modules
ADC
CPU Core
Flash and
EEPROM
RAM
clkADC
clkI/O
AVR Clock
Control Unit
clkASY
clkCPU
clkFLASH
Reset Logic
Source Clock
Watchdog Clock
Clock
Multiplexer
Timer/Counter
Oscillator
8.1.1
External RC
Oscillator
External Clock
Watchdog Timer
Watchdog
Oscillator
Crystal
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
8.1.2
8.1.3
24
8.1.4
8.1.5
8.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock
from the selected source is input to the clock generator, and routed to the appropriate modules.
Table 8-1.
CKSEL3:0
1111 - 1010
1001
External RC Oscillator
1000 - 0101
0100 - 0001
External Clock
Note:
1.
0000
The various choices for each clocking option is given in the following sections. When the CPU wakes up from
Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator
operation before instruction execution starts. When the CPU starts from Reset, there is as an additional delay
allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is
used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each timeout is shown in Table 8-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in Typical
Characteristics on page 290.
Table 8-2.
8.3
Number of Cycles
4.1ms
4.3ms
4K (4,096)
65ms
69ms
64K (65,536)
8.4
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use
as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a ceramic resonator may be used.
The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the
Oscillator output will oscillate will a full rail-to-rail swing on the output. This mode is suitable when operating in a
very noisy environment or when the output from XTAL2 drives a second clock buffer. This mode has a wide
frequency range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces
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power consumption considerably. This mode has a limited frequency range and it can not be used to drive other
clock buffers.
For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT
programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic
noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table
8-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.
Figure 8-2.
C2
XTAL2
C1
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The
operating mode is selected by the fuses CKSEL3:1 as shown in Table 8-3.
Table 8-3.
CKOPT
CKSEL3:1
Frequency Range
(MHz)
101(1)
0.4 - 0.9
110
0.9 - 3.0
12 - 22
111
3.0 - 8.0
12 - 22
1.0
12 - 22
Note:
1.
This option should not be used with crystals, only with ceramic resonators.
The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in Table 8-4.
Table 8-4.
CKSEL0
SUT1:0
Additional Delay
from Reset
(VCC = 5.0V)
00
258 CK(1)
4.1ms
01
258 CK(1)
65ms
10
1K CK(2)
11
1K CK(2)
4.1ms
00
1K CK(2)
65ms
Recommended Usage
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Table 8-4.
CKSEL0
SUT1:0
01
16K CK
10
16K CK
4.1ms
1
Notes:
1.
Additional Delay
from Reset
(VCC = 5.0V)
Recommended Usage
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast rising
power
2.
8.5
16K CK
65ms
SUT1:0
Recommended Usage
00
(1)
1K CK
4.1ms
01
1K CK(1)
65ms
10
32K CK
65ms
11
Note:
8.6
Additional Delay
from Reset
(VCC = 5.0V)
Reserved
1.
These options should only be used if frequency stability at start-up is not important for the application.
External RC Oscillator
For timing insensitive applications, the external RC configuration shown in Figure 8-3 can be used. The
frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22pF. By programming the
CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, thereby removing the
need for an external capacitor. For more information on Oscillator operation and details on how to choose R and
C, refer to the External RC Oscillator application note.
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Figure 8-3.
External RC Configuration
VCC
NC
XTAL2
XTAL1
C
GND
The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating
mode is selected by the fuses CKSEL3:0 as shown in Table 8-6.
Table 8-6.
0101
0.1 0.9
0110
0.9 - 3.0
0111
3.0 - 8.0
1000
8.0 - 12.0
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-7.
Table 8-7.
SUT1:0
Additional Delay
from Reset
(VCC = 5.0V)
00
18 CK
01
18 CK
4.1ms
10
18 CK
65ms
11
6 CK(1)
4.1ms
Note:
8.7
1.
Recommended Usage
BOD enabled
This option should not be used when operating close to the maximum frequency of the device.
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Table 8-8.
Note:
1.
0001(1)
1.0
0010
2.0
0011
4.0
0100
8.0
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-9. XTAL1
and XTAL2 should be left unconnected (NC).
Table 8-9.
SUT1:0
Additional Delay
from Reset
(VCC = 5.0V)
00
6 CK
01
6 CK
4.1ms
6 CK
65ms
10
(1)
11
Note:
8.8
Recommended Usage
BOD enabled
Reserved
1.
External Clock
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 8-4. To run the
device on an external clock, the CKSEL Fuses must be programmed to 0000. By programming the CKOPT
Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND.
Figure 8-4.
EXTERNAL
CLOCK
SIGNAL
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When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 8-10.
Table 8-10.
SUT1:0
Additional Delay
from Reset
(VCC = 5.0V)
00
6 CK
01
6 CK
4.1ms
10
6 CK
65ms
11
Recommended Usage
BOD enabled
Reserved
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to
ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next
can lead to unpredictable behavior. It is required to ensure that the MCU is kept in reset during such changes in
the clock frequency.
8.9
Timer/Counter Oscillator
For microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly
between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768kHz
watch crystal. Applying an external clock source to TOSC1 is not recommended.
Note:
8.10
8.10.1
The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal
capacitors have the same nominal value of 36pF.
Register Description
OSCCAL Oscillator Calibration Register
Bit
Read/Write
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
OSCCAL
OSCCAL Value
$00
50
100
$7F
75
150
$FF
100
200
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9.
9.1
Overview
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The
Atmel AVR provides various sleep modes allowing the user to tailor the power consumption to the applications
requirements.
9.2
Sleep Modes
Figure 8-1 on page 24 presents the different clock systems in the ATmega16A, and their distribution. The figure
is helpful in selecting an appropriate sleep mode. Table 9-1 shows the different sleep modes and their wake-up
sources.
Active Clock Domains and Wake Up Sources in the Different Sleep Modes
Idle
ADC NRM
1.
2.
3.
X(2)
X(2)
X(3)
X(3)
(3)
X(3)
X(3)
(2)
X
X(2)
X(2)
Other I/O
ADC
Standby(1)
Notes:
(2)
Extended
Standby(1)
Timer2
Power Down
Power Save
clkASY
Sleep Mode
Wake-up Sources
TWI Address Match
Oscillators
clkADC
clkIO
clkFLASH
clkCPU
Table 9-1.
X(2)
X(2)
To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction
must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC
Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP
instruction. See Table 9-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes
up from sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
9.3
Idle Mode
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the
CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters,
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Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH,
while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a
conversion starts automatically when this mode is entered.
9.4
9.5
Power-down Mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this
mode, the External Oscillator is stopped, while the External interrupts, the Two-wire Serial Interface address
watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brownout Reset, a Two-wire Serial Interface address match interrupt, an External level interrupt on INT0 or INT1, or
an External interrupt on INT2 can wake up the MCU. This sleep mode basically halts all generated clocks,
allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be
held for some time to wake up the MCU. Refer to External Interrupts on page 66 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL Fuses that define the reset time-out period, as described in Clock
Sources on page 25.
9.6
Power-save Mode
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This
mode is identical to Power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during
sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the
corresponding Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in
SREG is set.
If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended instead of
Power-save mode because the contents of the registers in the Asynchronous Timer should be considered
undefined after wake-up in Power-save mode if AS2 is 0.
This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules,
including Timer/Counter2 if clocked asynchronously.
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9.7
Standby Mode
When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the
Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.
9.8
9.9
9.9.1
9.9.2
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise
Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator
is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as
input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference
will be enabled, independent of sleep mode. Refer to Analog Comparator on page 193 for details on how to
configure the Analog Comparator.
9.9.3
Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out
Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to
Brown-out Detection on page 38 for details on how to configure the Brown-out Detector.
9.9.4
9.9.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer
is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes,
this will contribute significantly to the total current consumption. Refer to Watchdog Timer on page 40 for
details on how to configure the Watchdog Timer.
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9.9.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important
thing is then to ensure that no pins drive resistive loads. In sleep modes where the both the I/O clock (clkI/O) and
the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power
is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up
conditions, and it will then be enabled. Refer to the section Digital Input Enable and Sleep Modes on page 53
for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an
analog signal level close to VCC/2, the input buffer will use excessive power.
9.9.7
The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting
data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will
increase. Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem.
Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG
interface.
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9.10
9.10.1
Register Description
MCUCR MCU Control Register
The MCU Control Register contains control bits for power management.
Bit
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
MCUCR
Note:
SM2
SM1
SM0
Idle
Power-down
Power-save
Reserved
Reserved
Standby(1)
Extended Standby(1)
1.
Sleep Mode
Standby mode and Extended Standby mode are only available with external crystals or resonators.
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10.
10.1
10.1.1
Reset Sources
The ATmega16A has five sources of reset:
z
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold
(VPOT).
External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the
minimum pulse length.
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is
enabled.
Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold
(VBOT) and the Brown-out Detector is enabled.
JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan
chains of the JTAG system. Refer to the section IEEE 1149.1 (JTAG) Boundary-scan on page 219 for
details.
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Figure 10-1.
Reset Logic
DATA BUS
PORF
BORF
EXTRF
WDRF
JTRF
Power-on
Reset Circuit
INTERNAL RESET
Brown-out
Reset Circuit
BODEN
BODLEVEL
SPIKE
FILTER
Reset Circuit
JTAG Reset
Register
Watchdog
Timer
COUNTER RESET
Pull-up Resistor
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
CKSEL[3:0]
SUT[1:0]
10.1.2
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in
System and Reset Characteristics on page 282. The POR is activated whenever VCC is below the detection
level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC
rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level.
Figure 10-2.
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
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Figure 10-3.
VPOT
RESET
TIME-OUT
VRST
tTOUT
INTERNAL
RESET
10.1.3
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse
width (see System and Reset Characteristics on page 282) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset
Threshold Voltage VRST on its positive edge, the delay counter starts the MCU after the Time-out period
tTOUT has expired.
Figure 10-4.
10.1.4
Brown-out Detection
The ATmega16A has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during
operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse
BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has
a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be
interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN
programmed), and VCC decreases to a value below the trigger level (VBOT- in Figure 10-5), the Brown-out Reset
is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 10-5), the delay counter
starts the MCU after the Time-out period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD
given in System and Reset Characteristics on page 282.
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Figure 10-5.
VBOT-
VBOT+
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
10.1.5
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge
of this pulse, the delay timer starts counting the Time-out period tTOUT. For details, refer to Watchdog Timer on
page 40.
Figure 10-6.
CK
10.2
10.2.1
When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).
3.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow
the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power
consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference
is turned off before entering Power-down mode.
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10.3
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value
at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer
prescaler, the Watchdog Reset interval can be adjusted as shown in Table 10-1 on page 42. The WDR
Watchdog Reset instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled
and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period.
If the reset period expires without another Watchdog Reset, the ATmega16A resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to page 39.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the
Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details.
Figure 10-7.
Watchdog Timer
WATCHDOG
OSCILLATOR
ATmega16A [DATASHEET]
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10.4
10.4.1
Register Description
MCUCSR MCU Control and Status Register
The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
Bit
JTD
ISC2
JTRF
WDRF
BORF
EXTRF
PORF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
MCUCSR
WDTOE
WDE
WDP2
WDP1
WDP0
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
WDTCR
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Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
WDP2
WDP1
WDP0
Number of WDT
Oscillator Cycles
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
16K (16,384)
17.1 ms
16.3 ms
32K (32,768)
34.3 ms
32.5 ms
64K (65,536)
68.5 ms
65 ms
128K (131,072)
0.14 s
0.13 s
256K (262,144)
0.27 s
0.26 s
512K (524,288)
0.55 s
0.52 s
1,024K (1,048,576)
1.1 s
1.0 s
2,048K (2,097,152)
2.2 s
2.1 s
The following code example shows one assembly and one C function for turning off the WDT. The example
assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will
occur during execution of these functions.
ATmega16A [DATASHEET]
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C Code Example
void WDT_off(void)
{
/* Reset WDT*/
_WDR();
/* Write logical one to WDTOE and WDE */
WDTCR |= (1<<WDTOE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
}
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11.
Interrupts
11.1
Overview
This section describes the specifics of the interrupt handling as performed in ATmega16A. For a general
explanation of the AVR interrupt handling, refer to Reset and Interrupt Handling on page 13.
11.2
Interrupt Vectors
Table 11-1.
Vector No.
Program
Address(2)
Source
Interrupt Definition
$000(1)
RESET
$002
INT0
$004
INT1
$006
TIMER2 COMP
$008
TIMER2 OVF
$00A
TIMER1 CAPT
$00C
TIMER1 COMPA
$00E
TIMER1 COMPB
$010
TIMER1 OVF
Timer/Counter1 Overflow
10
$012
TIMER0 OVF
Timer/Counter0 Overflow
11
$014
SPI, STC
12
$016
USART, RXC
13
$018
USART, UDRE
14
$01A
USART, TXC
15
$01C
ADC
16
$01E
EE_RDY
17
$020
ANA_COMP
18
$022
TWI
19
$024
INT2
20
$026
TIMER0 COMP
21
$028
SPM_RDY
Notes:
1.
2.
USART, Rx Complete
USART Data Register Empty
USART, Tx Complete
ADC Conversion Complete
EEPROM Ready
Analog Comparator
When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see Boot
Loader Support Read-While-Write Self-Programming on page 237.
When the IVSEL bit in GICR is set, interrupt vectors will be moved to the start of the Boot Flash section. The
address of each Interrupt Vector will then be the address in this table added to the start address of the Boot
Flash section.
Table 11-2 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL
settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular
program code can be placed at these locations. This is also the case if the Reset Vector is in the Application
section while the Interrupt Vectors are in the Boot section or vice versa.
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Table 11-2.
BOOTRST
IVSEL
Note:
Reset address
$0000
$0002
$0000
$0002
1.
The Boot Reset Address is shown in Table 25-6 on page 249. For the BOOTRST Fuse 1 means
unprogrammed while 0 means programmed.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16A is:
Address Labels
$000
$002
$004
$006
$008
$00A
$00C
$00E
$010
$012
$014
$016
$018
$01A
$01C
$01E
$020
$022
$024
$026
$028
;
$02A RESET:
$02B
$02C
$02D
$02E
$02F
:.
:.
Code
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
RESET
EXT_INT0
EXT_INT1
TIM2_COMP
TIM2_OVF
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_OVF
SPI_STC
USART_RXC
USART_UDRE
USART_TXC
ADC
EE_RDY
ANA_COMP
TWSI
EXT_INT2
TIM0_COMP
SPM_RDY
Comments
; Reset Handler
; IRQ0 Handler
; IRQ1 Handler
; Timer2 Compare Handler
; Timer2 Overflow Handler
; Timer1 Capture Handler
; Timer1 CompareA Handler
; Timer1 CompareB Handler
; Timer1 Overflow Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; USART RX Complete Handler
; UDR Empty Handler
; USART TX Complete Handler
; ADC Conversion Complete Handler
; EEPROM Ready Handler
; Analog Comparator Handler
; Two-wire Serial Interface Handler
; IRQ2 Handler
; Timer0 Compare Handler
; Store Program Memory Ready Handler
ldi
r16,high(RAMEND; Main program start
out
SPH,r16
; Set Stack Pointer to top of RAM
ldi
r16,low(RAMEND)
out
SPL,r16
sei
; Enable interrupts
<instr> xxx
:.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the
GICR Register is set before any interrupts are enabled, the most typical and general program setup for the
Reset and Interrupt Vector Addresses is:
Address Labels
$000 RESET:
$001
$002
$003
$004
$005
;
Code
ldi
r16,high(RAMEND)
out
SPH,r16
ldi
r16,low(RAMEND)
out
SPL,r16
sei
<instr> xxx
Comments
; Main program start
; Set Stack Pointer to top of RAM
; Enable interrupts
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.org $1C02
$1C02
$1C04
:.
:..
$1C28
jmp
jmp
:
jmp
EXT_INT0
EXT_INT1
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
SPM_RDY
When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and
general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels
.org $002
$002
$004
:.
:..
$028
jmp
Ready Handler
;
.org $1C00
$1C00 RESET:
$1C01
$1C02
$1C03
$1C04
$1C05
Code
jmp
jmp
:
Comments
EXT_INT0
EXT_INT1
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory
SPM_RDY
ldi
r16,high(RAMEND)
out
SPH,r16
ldi
r16,low(RAMEND)
out
SPL,r16
sei
<instr> xxx
; Enable interrupts
When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the GICR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses is:
Address Labels
.org $1C00
$1C00
$1C02
$1C04
:.
:..
$1C28
;
$1C2A RESET:
$1C2B
$1C2C
$1C2D
$1C2E
$1C2F
11.2.1
Code
jmp
jmp
jmp
:
jmp
Comments
RESET
EXT_INT0
EXT_INT1
;
;
;
;
; Store
SPM_RDY
ldi
r16,high(RAMEND)
out
SPH,r16
ldi
r16,low(RAMEND)
out
SPL,r16
sei
<instr> xxx
Reset handler
IRQ0 Handler
IRQ1 Handler
Program Memory Ready Handler
; Enable interrupts
11.2.2
Bit
INT1
INT0
INT2
IVSEL
IVCE
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
GICR
ATmega16A [DATASHEET]
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Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle
IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not
written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic
disabling.
Note:
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are
disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and
Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to
the section Boot Loader Support Read-While-Write Self-Programming on page 237 for details on Boot Lock bits.
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C Code Example
void Move_interrupts(void)
{
/* Enable change of interrupt vectors */
GICR = (1<<IVCE);
/* Move interrupts to boot Flash section */
GICR = (1<<IVSEL);
}
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12.
I/O Ports
12.1
Overview
All ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the
direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or
enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive
characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays
directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All
I/O pins have protection diodes to both VCC and Ground as indicated in Figure 12-1. Refer to Electrical
Characteristics on page 279 for a complete list of parameters.
Figure 12-1.
Rpu
Logic
Pxn
Cpin
See Figure 23
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case x represents the
numbering letter for the port, and a lower case n represents the bit number. However, when using the register
or bit defines in a program, the precise form must be used. i.e., PORTB3 for bit no. 3 in Port B, here
documented generally as PORTxn. The physical I/O Registers and bit locations are listed in Register
Description on page 64.
Three I/O memory address locations are allocated for each port, one each for the Data Register PORTx, Data
Direction Register DDRx, and the Port Input Pins PINx. The Port Input Pins I/O location is read only, while
the Data Register and the Data Direction Register are read/write. In addition, the Pull-up Disable PUD bit in
SFIOR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in Ports as General Digital I/O on page 50. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function
interferes with the port pin is described in Alternate Port Functions on page 53. Refer to the individual module
sections for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the
port as general digital I/O.
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12.2
PUD
DDxn
Q CLR
RESET
WDx
Pxn
PORTxn
Q CLR
WPx
DATA BUS
RDx
RESET
RRx
SLEEP
SYNCHRONIZER
D
RPx
PINxn
Q
clk I/O
PUD:
SLEEP:
clkI/O:
Note:
12.2.1
1.
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WPx:
RRx:
RPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are
common to all ports.
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Switching between input with pull-up and output low generates the same problem. The user must use either the
tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 12-1 summarizes the control signals for the pin value.
Port Pin Configurations
Table 12-1.
12.2.2
DDxn
PORTxn
PUD
(in SFIOR)
I/O
Pull-up
Input
No
Tri-state (Hi-Z)
Input
Yes
Input
No
Tri-state (Hi-Z)
Output
No
Output
No
Comment
SYSTEM CLK
INSTRUCTIONS
XXX
in r17, PINx
XXX
SYNC LATCH
PINxn
r17
0xFF
0x00
tpd, max
tpd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the SYNC
LATCH signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn
Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal
transition on the pin will be delayed between and 1 system clock period depending upon the time of
assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 124. The out instruction sets the SYNC LATCH signal at the positive edge of the clock. In this case, the delay tpd
through the synchronizer is one system clock period.
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Figure 12-4.
SYSTEM CLK
r16
INSTRUCTIONS
0xFF
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0xFF
0x00
tpd
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins
from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but
as previously discussed, a nop instruction is included to be able to read back the value recently assigned to
some of the pins.
Assembly Code Example(1)
:.
; Define pull-ups and set outputs high
; Define directions for port pins
ldi
r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out
PORTB,r16
out
DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in
r16,PINB
:.
C Code Example(1)
unsigned char i;
:.
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
_NOP();
/* Read port pins */
i = PINB;
:.
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Note:
12.2.3
1.
For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins
0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as
strong high drivers.
12.2.4
Unconnected pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and
Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case,
the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended
to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended,
since this may cause excessive currents if the pin is accidentally configured as an output.
12.3
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Figure 12-5.
PUD
DDOExn
DDOVxn
1
Q D
DDxn
Q CLR
WDx
PVOExn
RESET
1
Pxn
Q
PORTxn
Q CLR
DIEOExn
WPx
DATA BUS
RDx
PVOVxn
RESET
DIEOVxn
1
0
RRx
SLEEP
SYNCHRONIZER
D
SET
RPx
PINxn
L
CLR
CLR
clk I/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
Note:
1.
PUD:
WDx:
RDx:
RRx:
WPx:
RPx:
clkI/O:
DIxn:
AIOxn:
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are
common to all ports. All other signals are unique for each pin.
Table 12-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 12-5 are not
shown in the succeeding tables. The overriding signals are generated internally in the modules having the
alternate function.
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Table 12-2.
Signal Name
Full Name
Description
PUOE
Pull-up Override
Enable
PUOV
DDOE
Data Direction
Override Enable
DDOV
Data Direction
Override Value
PVOE
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared,
and the Output Driver is enabled, the port Value is controlled
by the PORTxn Register bit.
PVOV
DIEOE
DIEOV
DI
Digital Input
AIO
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals
to the alternate function. Refer to the alternate function description for further details.
12.3.1
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Table 12-3.
Port Pin
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Table 12-4 and Table 12-5 relate the alternate functions of Port A to the overriding signals shown in Figure 12-5
on page 54.
Table 12-4.
Signal Name
PA6/ADC6
PA5/ADC5
PA4/ADC4
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
ADC7 INPUT
ADC6 INPUT
ADC5 INPUT
ADC4 INPUT
AIO
Table 12-5.
Signal Name
PA2/ADC2
PA1/ADC1
PA0/ADC0
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
ADC0 INPUT
AIO
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12.3.2
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
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OC0, Output Compare Match output: The PB3 pin can serve as an external output for the Timer/Counter0
Compare Match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The
OC0 pin is also the output pin for the PWM mode timer function.
AIN0/INT2 Port B, Bit 2
AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up switched off to
avoid the digital port function from interfering with the function of the Analog Comparator.
INT2, External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to the MCU.
T1 Port B, Bit 1
T1, Timer/Counter1 Counter Source.
T0/XCK Port B, Bit 0
T0, Timer/Counter0 Counter Source.
XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is output (DDB0
set) or input (DDB0 cleared). The XCK pin is active only when the USART operates in Synchronous mode.
Table 12-7 and Table 12-8 relate the alternate functions of Port B to the overriding signals shown in Figure 12-5
on page 54. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into
SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 12-7.
Signal
Name
PB7/SCK
PB6/MISO
PB5/MOSI
PB4/SS
PUOE
SPE MSTR
SPE MSTR
SPE MSTR
SPE MSTR
PUOV
PORTB7 PUD
PORTB6 PUD
PORTB5 PUD
PORTB4 PUD
DDOE
SPE MSTR
SPE MSTR
SPE MSTR
SPE MSTR
DDOV
PVOE
SPE MSTR
SPE MSTR
SPE MSTR
PVOV
SCK OUTPUT
DIEOE
DIEOV
DI
SCK INPUT
SPI SS
AIO
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Table 12-8.
12.3.3
Signal
Name
PB3/OC0/AIN1
PB2/INT2/AIN0
PB1/T1
PB0/T0/XCK
PUOE
PUOV
DDOE
DDOV
PVOE
OC0 ENABLE
UMSEL
PVOV
OC0
XCK OUTPUT
DIEOE
INT2 ENABLE
DIEOV
DI
INT2 INPUT
T1 INPUT
AIO
AIN1 INPUT
AIN0 INPUT
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
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ATmega16A [DATASHEET]
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Table 12-10.
Signal
Name
PC7/TOSC2
PC6/TOSC1
PC5/TDI
PC4/TDO
PUOE
AS2
AS2
JTAGEN
JTAGEN
PUOV
DDOE
AS2
AS2
JTAGEN
JTAGEN
DDOV
SHIFT_IR + SHIFT_DR
PVOE
JTAGEN
PVOV
TDO
DIEOE
AS2
AS2
JTAGEN
JTAGEN
DIEOV
DI
AIO
TDI
Table 12-11.
Signal
Name
PC3/TMS
PC2/TCK
PC1/SDA
PC0/SCL
PUOE
JTAGEN
JTAGEN
TWEN
TWEN
PUOV
PORTC1 PUD
PORTC0 PUD
DDOE
JTAGEN
JTAGEN
TWEN
TWEN
DDOV
SDA_OUT
SCL_OUT
PVOE
TWEN
TWEN
PVOV
DIEOE
JTAGEN
JTAGEN
DIEOV
DI
AIO
TMS
TCK
SDA INPUT
SCL INPUT
Note:
1.
When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins PC0 and PC1. This
is not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port
figure and the digital logic of the TWI module.
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12.3.4
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
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Signal Name
PD7/OC2
PD6/ICP1
PD5/OC1A
PD4/OC1B
PUOE
PUOV
DDOE
DDOV
PVOE
OC2 ENABLE
OC1A ENABLE
OC1B ENABLE
PVOV
OC2
OC1A
OC1B
DIEOE
DIEOV
DI
ICP1 INPUT
AIO
Table 12-14.
Signal Name
PD3/INT1
PD2/INT0
PD1/TXD
PD0/RXD
PUOE
TXEN
RXEN
PUOV
PORTD0 PUD
DDOE
TXEN
RXEN
DDOV
PVOE
TXEN
PVOV
TXD
DIEOE
INT1 ENABLE
INT0 ENABLE
DIEOV
DI
INT1 INPUT
INT0 INPUT
RXD
AIO
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12.4
12.4.1
Register Description
SFIOR Special Function I/O Register
Bit
ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SFIOR
12.4.3
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
12.4.4
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Read/Write
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PINA
12.4.6
DDRA
12.4.5
PORTA
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PORTB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
DDRB
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12.4.7
12.4.8
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12.4.9
PINB
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PORTC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
DDRC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Read/Write
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PINC
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
PORTD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
DDRD
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
Read/Write
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PIND
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13.
External Interrupts
The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts
will trigger even if the INT0:2 pins are configured as outputs. This feature provides a way of generating a
software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only
an edge triggered interrupt). This is set up as indicated in the specification for the MCU Control Register
MCUCR and MCU Control and Status Register MCUCSR. When the external interrupt is enabled and is
configured as level triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low. Note that
recognition of falling or rising edge interrupts on INT0 and INT1 requires the presence of an I/O clock, described
in Clock Systems and their Distribution on page 24. Low level interrupts on INT0/INT1 and the edge interrupt
on INT2 are detected asynchronously. This implies that these interrupts can be used for waking the part also
from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be
held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is
sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V
and 25C. The frequency of the Watchdog Oscillator is voltage dependent as shown in Electrical
Characteristics on page 279. The MCU will wake up if the input has the required level during this sampling or if
it is held until the end of the start-up time. The start-up time is defined by the SUT Fuses as described in
System Clock and Clock Options on page 24. If the level is sampled twice by the Watchdog Oscillator clock
but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated.
The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt.
13.1
13.1.1
Register Description
MCUCR MCU Control Register
The MCU Control Register contains control bits for interrupt sense control and general MCU functions.
Bit
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
MCUCR
ISC11
ISC10
Description
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13.1.2
ISC01
ISC00
Description
JTD
ISC2
JTRF
WDRF
BORF
EXTRF
PORF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
MCUCSR
INT1
INT0
INT2
IVSEL
IVCE
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
GICR
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INTF1
INTF0
INTF2
Read/Write
R/W
R/W
R/W
Initial Value
GIFR
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14.
14.1
Features
14.2
Overview
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block
diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, refer to Pinout
ATmega16A on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
device-specific I/O Register and bit locations are listed in the Register Description on page 79.
Figure 14-1.
TCCRn
count
TOVn
(Int.Req.)
clear
Control Logic
direction
clk Tn
Clock Select
Edge
Detector
DATABUS
BOTTOM
Tn
TOP
( From Prescaler )
Timer/Counter
TCNTn
=0
= 0xFF
OCn
(Int.Req.)
Waveform
Generation
OCn
OCRn
14.2.1
Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request
(abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not
shown in the figure since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or
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decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock
Select logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times.
The result of the compare can be used by the waveform generator to generate a PWM or variable frequency
output on the Output Compare Pin (OC0). See Output Compare Unit on page 71. for details. The compare
match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt
request.
14.2.2
Definitions
Many register and bit references in this document are written in general form. A lower case n replaces the
Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise
form must be used i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 14-1 are also used extensively throughout the document.
Table 14-1.
14.3
Definitions
BOTTOM
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0 Register. The assignment is dependent
on the mode of operation.
14.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 14-2 shows a
block diagram of the counter and its surroundings.
Figure 14-2.
DATA BUS
Clock Select
count
TCNTn
clear
Control Logic
clkTn
Edge
Detector
Tn
direction
( From Prescaler )
BOTTOM
TOP
direction
clear
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clkTn
TOP
BOTTOM
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can
be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over)
all counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the
Timer/Counter Control Register (TCCR0). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare output OC0. For more details about
advanced counting sequences and waveform generation, see Modes of Operation on page 73.
The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by the WGM01:0
bits. TOV0 can be used for generating a CPU interrupt.
14.5
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top
bottom
Waveform Generator
OCn
FOCn
WGMn1:0
COMn1:0
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The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR0 Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0 Buffer Register, and if double buffering is disabled the CPU will access the OCR0
directly.
14.5.1
14.5.2
14.5.3
14.6
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Figure 14-4.
COMn1
COMn0
FOCn
Waveform
Generator
Q
1
OCn
DATA BUS
OCn
Pin
PORT
D
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC0) from the Waveform Generator if either
of the COM01:0 bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be
set as output before the OC0 value is visible on the pin. The port override function is independent of the
Waveform Generation mode.
The design of the output compare pin logic allows initialization of the OC0 state before the output is enabled.
Note that some COM01:0 bit settings are reserved for certain modes of operation. See Register Description on
page 79.
14.6.1
14.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM). For non-PWM modes the COM01:0 bits control whether the output should be set, cleared, or
toggled at a compare match (See Compare Match Output Unit on page 72.).
For detailed timing information refer to Figure 14-8, Figure 14-9, Figure 14-10 and Figure 14-11 in
Timer/Counter Timing Diagrams on page 77.
14.7.1
Normal Mode
The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the counting direction is
always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its
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maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the
Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The
TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with
the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by
software. There are no special cases to consider in the normal mode, a new counter value can be written
anytime.
The output compare unit can be used to generate interrupts at some given time. Using the output compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
14.7.2
TCNTn
OCn
(Toggle)
Period
(COMn1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If
the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must
be done with care since the CTC mode does not have the double buffering feature. If the new value written to
OCR0 is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then
have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1). The OC0 value will
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will
have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is
defined by the following equation:
f clk_I/O
f OCn = ----------------------------------------------2 N ( 1 + OCRn )
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
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14.7.3
TCNTn
OCn
(COMn1:0 = 2)
OCn
(COMn1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled,
the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting the
COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM01:0 to 3 (See Table 14-4 on page 80). The actual OC0 value will only be visible on the port pin if the
data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0
Register at the compare match between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the
timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnPWM = -----------------N 256
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0 Register represents special cases when generating a PWM waveform output
in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM01:0 bits.)
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A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0 to
toggle its logical level on each compare match (COM01:0 = 1). The waveform generated will have a maximum
frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero. This feature is similar to the OC0 toggle in CTC mode,
except the double buffer feature of the output compare unit is enabled in the fast PWM mode.
14.7.4
OCRn Update
TCNTn
OCn
(COMn1:0 = 2)
OCn
(COMn1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag
can be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting
the COM01:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM01:0 to 3 (see Table 14-5 on page 81). The actual OC0 value will only be visible on the port pin if the
data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0
Register at the compare match between OCR0 and TCNT0 when the counter increments, and setting (or
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clearing) the OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnPCPWM = -----------------N 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output
in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the output will be continuously low and if
set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output
will have the opposite logic values.
At the very start of Period 2 in Figure 14-7 OCn has a transition from high to low even though there is no
Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases
that give a transition without Compare Match:
14.8
OCR0A changes its value from MAX, like in Figure 14-7. When the OCR0A value is MAX the OCn pin
value is the same as the result of a down-counting Compare Match. To ensure symmetry around
BOTTOM the OCn value at MAX must be correspond to the result of an up-counting Compare Match.
The Timer starts counting from a value higher than the one in OCR0A, and for that reason misses the
Compare Match and hence the OCn change that would have happened on the way up.
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 14-9 shows the same timing data, but with the prescaler enabled.
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Figure 14-9.
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 14-10 shows the setting of OCF0 in all modes except CTC mode.
Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn Value
OCFn
Figure 14-11 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
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Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
OCRn
BOTTOM + 1
TOP
OCFn
14.9
14.9.1
Register Description
TCCR0 Timer/Counter Control Register
Bit
FOC0
WGM00
COM01
COM00
WGM01
CS02
CS01
CS00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TCCR0
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Table 14-2.
Mode
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter Mode of
Operation
TOP
Update of
OCR0
TOV0 Flag
Set-on
Normal
0xFF
Immediate
MAX
0xFF
TOP
BOTTOM
CTC
OCR0
Immediate
MAX
Fast PWM
0xFF
BOTTOM
MAX
Note:
1.
The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the
functionality and location of these bits are compatible with previous versions of the timer.
COM01
COM00
Description
Table 14-4 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.
Table 14-4.
COM01
COM00
Reserved
Note:
1.
Description
A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored,
but the set or clear is done at TOP. See Fast PWM Mode on page 75 for more details.
Table 14-5 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode.
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Table 14-5.
COM01
COM00
Reserved
Clear OC0 on compare match when up-counting. Set OC0 on compare match
when downcounting.
Set OC0 on compare match when up-counting. Clear OC0 on compare match
when downcounting.
Note:
1.
Description
A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare match is ignored,
but the set or clear is done at TOP. See Phase Correct PWM Mode on page 76 for more details.
CS02
CS01
CS00
Description
clkI/O/(No prescaling)
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
14.9.2
TCNT0[7:0]
TCNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock.
Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match
between TCNT0 and the OCR0 Register.
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14.9.3
OCR0[7:0]
OCR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Register contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on
the OC0 pin.
14.9.4
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TIMSK
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TIFR
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15.
15.1
Overview
Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have
different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0.
15.2
15.3
Prescaler Reset
The prescaler is free running, i.e., operates independently of the clock select logic of the Timer/Counter, and it is
shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counters clock
select, the state of the prescaler will have implications for situations where a prescaled clock is used. One
example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1).
The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to
N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However,
care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler
reset will affect the prescaler period for all Timer/Counters it is connected to.
15.4
Tn
Tn_sync
(To Clock
Select Logic)
LE
clk I/O
Synchronization
Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge
has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system
clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct
sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk <
fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an
external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to
variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and
capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than
fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 15-2.
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
Note:
15.5
15.5.1
clkT0
1. The synchronization logic on the input pins (T1/T0) is shown in Figure 15-1.
Register Description
SFIOR Special Function IO Register
Bit
ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SFIOR
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16.
16-bit Timer/Counter1
16.1
Features
16.2
Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation,
and signal timing measurement. Most register and bit references in this section are written in general form. A
lower case n replaces the Timer/Counter number, and a lower case x replaces the output compare unit.
However, when using the register or bit defines in a program, the precise form must be used (i.e., TCNT1 for
accessing Timer/Counter1 counter value and so on).
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 16-1. For the actual placement of I/O
pins, refer to Figure 1-1 on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in
bold. The device specific I/O Register and bit locations are listed in the Register Description on page 105.
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Figure 16-1.
TOVn
(Int.Req.)
Control Logic
clkTn
Clock Select
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=0
OCnA
(Int.Req.)
Waveform
Generation
OCnA
DATABUS
OCRnA
OCnB
(Int.Req.)
Fixed
TOP
Values
Waveform
Generation
=
OCRnB
OCnB
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
ICRn
Noise
Canceler
ICPn
TCCRnA
Note:
16.2.1
1.
TCCRnB
Refer to Figure 1-1 on page 3, Table 12-6 on page 57, and Table 12-12 on page 62 for Timer/Counter1 pin
placement and description.
Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures
are described in the section Accessing 16-bit Registers on page 87. The Timer/Counter Control Registers
(TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req.
in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since
these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin.
The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or
decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock
select logic is referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all
time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable
frequency output on the Output Compare pin (OC1A/B). See Output Compare Units on page 93. The compare
match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an output
compare interrupt request.
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The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on
either the Input Capture Pin (ICP1) or on the Analog Comparator pins (See Analog Comparator on page 193.)
The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing
noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM
mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this
case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the
ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output.
16.2.2
Definitions
The following definitions are used extensively throughout the document:
Table 16-1.
16.2.3
Definitions
BOTTOM
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF,
0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.
Compatibility
The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR
Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding:
z
All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers.
Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.
Interrupt Vectors.
The following control bits have changed name, but have same functionality and register location:
z
The following bits are added to the 16-bit Timer/Counter Control Registers:
z
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases.
16.3
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Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit registers
does not involve using the temporary register.
To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be
read before the High byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts
updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1
Registers. Note that when using C, the compiler handles the 16-bit access.
Assembly Code Example(1)
:.
; Set TCNT1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
out
TCNT1H,r17
out
TCNT1L,r16
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
:.
C Code Example(1)
unsigned int i;
:.
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
:.
Note:
1.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the
two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by
accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt
will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the
main code must disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of
the OCR1A/B or ICR1 Registers can be done by using the same principle
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.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note:
1.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of
the OCR1A/B or ICR1 Registers can be done by using the same principle.
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C Code Example(1)
void TIM16_WriteTCNT1 ( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
Note:
1.
The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1.
16.3.1
16.4
16.5
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2
shows a block diagram of the counter and its surroundings.
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Figure 16-2.
DATA BUS
(8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
Count
TCNTnH (8-bit)
TCNTnL (8-bit)
Clear
Direction
Control Logic
clkTn
Edge
Detector
Tn
( From Prescaler )
TOP
BOTTOM
Direction
Clear
clkT1
Timer/Counter clock.
TOP
BOTTOM
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper
eight bits of the counter, and Counter Low (TCNT1L) containing the lower 8 bits. The TCNT1H Register can only
be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU
accesses the High byte temporary register (TEMP). The temporary register is updated with the TCNT1H value
when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written.
This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is
counting that will give unpredictable results. The special cases are described in the sections where they are of
importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select
bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value
can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority
over) all counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation Mode bits (WGM13:0) located
in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between
how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x.
For more details about advanced counting sequences and waveform generation, see Modes of Operation on
page 96.
The Timer/Counter Overflow (TOV1) Flag is set according to the mode of operation selected by the WGM13:0
bits. TOV1 can be used for generating a CPU interrupt.
16.6
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The Input Capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of the block
diagram that are not directly a part of the Input Capture unit are gray shaded. The small n in register and bit
names indicates the Timer/Counter number.
Figure 16-3.
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit)
ICRnL (8-bit)
TCNTnH (8-bit)
WRITE
ACO*
Analog
Comparator
ACIC*
TCNTnL (8-bit)
ICNC
ICES
Noise
Canceler
Edge
Detector
ICFn (Int.Req.)
ICPn
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog
Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be
triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture
Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied
into ICR1 Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an Input Capture Interrupt. The
ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by
software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and
then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary
register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register
for defining the counters TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be
set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the High byte
must be written to the ICR1H I/O location before the Low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to Accessing 16-bit Registers on page 87.
16.6.1
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Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same
technique as for the T1 pin (Figure 15-1 on page 83). The edge detector is also identical. However, when the
noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by
four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless
the Timer/Counter is set in a waveform generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
16.6.2
Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input
is monitored over four samples, and all four must be equal for changing the output that in turn is used by the
edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control
Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system
clock and is therefore not affected by the prescaler.
16.6.3
16.7
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Figure 16-4 shows a block diagram of the output compare unit. The small n in the register and bit names
indicates the device number (n = 1 for Timer/Counter1), and the x indicates output compare unit (A/B). The
elements of the block diagram that are not directly a part of the output compare unit are gray shaded.
Figure 16-4.
DATA BUS
(8-bit)
TEMP (8-bit)
TCNTnH (8-bit)
OCRnxH (8-bit)
TCNTnL (8-bit)
OCRnxL (8-bit)
= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
BOTTOM
Waveform Generator
WGMn3:0
OCnx
COMnx1:0
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The
double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the
counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses,
thereby making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the
OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation
(the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore
OCR1x is not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low
byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP
Register since the compare of all 16 bits is done continuously. The High byte (OCR1xH) has to be written first.
When the High byte I/O location is written by the CPU, the TEMP Register will be updated by the value written.
Then when the Low byte (OCR1xL) is written to the lower eight bits, the High byte will be copied into the upper
8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Accessing 16-bit Registers on page 87.
16.7.1
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16.7.2
16.7.3
COMnx1
COMnx0
FOCnx
Waveform
Generator
Q
1
OCnx
D
DATABUS
16.8
OCnx
Pin
PORT
D
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if
either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the
Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x)
must be set as output before the OC1x value is visible on the pin. The port override function is generally
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independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 16-2, Table 163 and Table 16-4 for details.
The design of the output compare pin logic allows initialization of the OC1x state before the output is enabled.
Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See Register Description
on page 105.
The COM1x1:0 bits have no effect on the Input Capture unit.
16.8.1
16.9
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the
combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or
toggle at a compare match (See Compare Match Output Unit on page 95.)
For detailed timing information refer to Timer/Counter Timing Diagrams on page 103.
16.9.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is
always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its
maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the
Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The
TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with
the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between
the external events must not exceed the resolution of the counter. If the interval between events are too long,
the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using the output compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
16.9.2
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The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNT1) increases until a
compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.
Figure 16-6.
TCNTn
OCnA
(Toggle)
Period
(COMnA1:0 = 1)
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A
or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt
handler routine can be used for updating the TOP value. However, changing the TOP to a value close to
BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC
mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the
current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its
maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for
defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each
compare match by setting the compare output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will
not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The
waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000).
The waveform frequency is defined by the following equation:
f clk_I/O
f OCnA = --------------------------------------------------2 N ( 1 + OCRnA )
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x0000.
16.9.3
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The
minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit
(ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log ( TOP + 1 )
R FPWM = ----------------------------------log ( 2 )
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A
(WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 16-7. The figure shows fast PWM mode when OCR1A or ICR1 is used to define
TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.
The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a
compare match occurs.
Figure 16-7.
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or
ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining
the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the
TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value
of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match
will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits
are masked to zero when any of the OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1
Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running
with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value
of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter
will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare
match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location
to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A
Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the
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next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the
TCNT1 is cleared and the TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is
actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its
double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the
COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM1x1:0 to 3 (See Table 16-2 on page 105). The actual OC1x value will only be visible on the port pin if
the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or
clearing) the OC1x Register at the compare match between OCR1x and TCNT1, and clearing (or setting) the
OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ----------------------------------N ( 1 + TOP )
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform
output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike
for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output
(depending on the polarity of the output set by the COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to
toggle its logical level on each compare match (COM1A1:0 = 1). This applies only if OCR1A is used to define
the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2
when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double
buffer feature of the output compare unit is enabled in the fast PWM mode.
16.9.4
99
The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a
compare match occurs.
Figure 16-8.
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A
or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock
cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be
used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value
of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match
will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits
are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 16-8
illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in
an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since
the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the
falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the
new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in
length gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when
changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically
no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting
the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by
setting the COM1x1:0 to 3 (See Table 16-2 on page 105). The actual OC1x value will only be visible on the port
pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by
setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter
increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when
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the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated
by the following equation:
f clk_I/O
f OCnxPCPWM = ---------------------------2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output
in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and
if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the
output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
16.9.5
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Figure 16-9.
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are
updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP
value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to
generate an interrupt each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value
of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match
will never occur between the TCNT1 and the OCR1x.
As Figure 16-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods.
Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always
be equal. This gives symmetrical output pulses and is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A
Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is
actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its
double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can
be generated by setting the COM1x1:0 to 3 (See Table on page 106). The actual OC1x value will only be
visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is
generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when
the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency
correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPFCPWM = ---------------------------2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM waveform
output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously
low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the
output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and
COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.
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clkI/O
clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 16-11 shows the same timing data, but with the prescaler enabled.
Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency
correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but
TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes
that set the TOV1 Flag at BOTTOM.
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clkI/O
clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Figure 16-13 shows the same timing data, but with the prescaler enabled.
Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
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COM1A1
COM1A0
COM1B1
COM1B0
FOC1A
FOC1B
WGM11
WGM10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TCCR1A
COM1A1/COM1B1
COM1A0/COM1B0
Description
Table 16-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
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Table 16-3.
COM1A1/COM1B1
Note:
1.
COM1A0/COM1B0
Description
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the
compare match is ignored, but the set or clear is done at BOTTOM. See Fast PWM Mode on page 97. for
more details.
Table 16-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the
phase and frequency correct, PWM mode.
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM (1)
Table 16-4.
COM1A1/COM1B1
COM1A0/COM1B0
Clear OC1A/OC1B on compare match when upcounting. Set OC1A/OC1B on compare match
when downcounting.
Set OC1A/OC1B on compare match when upcounting. Clear OC1A/OC1B on compare match
when downcounting.
Note:
1.
Description
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See Phase Correct
PWM Mode on page 99. for more details.
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Table 16-5.
Mode
WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
TOP
Update of
OCR1x
Normal
0xFFFF
Immediate
MAX
0x00FF
TOP
BOTTOM
0x01FF
TOP
BOTTOM
0x03FF
TOP
BOTTOM
CTC
OCR1A
Immediate
MAX
0x00FF
BOTTOM
TOP
0x01FF
BOTTOM
TOP
0x03FF
BOTTOM
TOP
ICR1
BOTTOM
BOTTOM
OCR1A
BOTTOM
BOTTOM
10
ICR1
TOP
BOTTOM
11
OCR1A
TOP
BOTTOM
12
CTC
ICR1
Immediate
MAX
13
Reserved
14
Fast PWM
ICR1
BOTTOM
TOP
15
Note:
Fast PWM
OCR1A
BOTTOM
TOP
1
1
1
1
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality
and location of these bits are compatible with previous versions of the timer.
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TCCR1B
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When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture
Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input
Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the
TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
Bit 5 Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero
when TCCR1B is written.
Bit 4:3 WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
Bit 2:0 CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 16-10 and
Figure 16-11.
Table 16-6.
CS12
CS10
Description
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
16.11.3 TCNT1H and TCNT1L Timer/Counter1 High and Low Register
Bit
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for
read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low
bytes are read and written simultaneously when the CPU accesses these registers, the access is performed
using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See Accessing 16-bit Registers on page 87.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match
between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare
units.
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OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value
(TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on
the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High
Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See Accessing 16-bit
Registers on page 87.
16.11.6 ICR1H and ICR1L Input Capture Register 1
Bit
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or
optionally on the analog comparator output for Timer/Counter1). The Input Capture can be used for defining the
counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously
when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See Accessing 16-bit Registers on
page 87.
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
Note:
1.
TIMSK
This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this
section. The remaining bits are described in their respective timer sections.
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OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
Note:
TIFR
This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The
remaining bits are described in their respective timer sections.
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17.
17.1
Features
17.2
Overview
Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block
diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement of I/O pins, refer to Pinout
ATmega16A on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
device-specific I/O Register and bit locations are listed in the Register Description on page 125.
Figure 17-1.
count
TOVn
(Int.Req.)
clear
Control Logic
direction
clkTn
TOSC1
BOTTOM
TOP
Prescaler
T/C
Oscillator
TOSC2
Timer/Counter
TCNTn
=0
= 0xFF
DATABUS
OCn
(Int.Req.)
Waveform
Generation
clkI/O
OCn
OCRn
Synchronized Status flags
clkI/O
Synchronization Unit
clkASY
Status flags
ASSRn
asynchronous mode
select (ASn)
17.2.1
Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request
(shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are
individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the
figure since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2
pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status
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Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment
(or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the
Clock Select logic is referred to as the timer clock (clkT2).
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times.
The result of the compare can be used by the waveform generator to generate a PWM or variable frequency
output on the Output Compare Pin (OC2). See Output Compare Unit on page 114. for details. The compare
match event will also set the Compare Flag (OCF2) which can be used to generate an output compare interrupt
request.
17.2.2
Definitions
Many register and bit references in this document are written in general form. A lower case n replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in Table
17-1 are also used extensively throughout the document.
Table 17-1.
17.3
Definitions
BOTTOM
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2 Register. The assignment is dependent
on the mode of operation.
17.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 shows a
block diagram of the counter and its surrounding environment.
Figure 17-2.
DATA BUS
TOSC1
count
TCNTn
clear
clk Tn
Control Logic
Prescaler
T/C
Oscillator
direction
bottom
TOSC2
top
clkI/O
direction
113
clear
clkT2
Timer/Counter clock.
top
bottom
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer
clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can
be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over)
all counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the
Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare output OC2. For more details about
advanced counting sequences and waveform generation, see Modes of Operation on page 116.
The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0
bits. TOV2 can be used for generating a CPU interrupt.
17.5
DATA BUS
OCRn
TCNTn
= (8-bit Comparator )
OCFn (Int.Req.)
top
bottom
Waveform Generator
OCxy
FOCn
WGMn1:0
COMn1:0
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The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double
buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting
sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2
directly.
17.5.1
17.5.2
17.5.3
17.6
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Figure 17-4.
COMn1
COMn0
FOCn
Waveform
Generator
Q
1
OCn
DATA BUS
OCn
Pin
PORT
D
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either
of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be
set as output before the OC2 value is visible on the pin. The port override function is independent of the
Waveform Generation mode.
The design of the output compare pin logic allows initialization of the OC2 state before the output is enabled.
Note that some COM21:0 bit settings are reserved for certain modes of operation. See Register Description on
page 125.
17.6.1
17.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the
combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or noninverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or
toggled at a compare match (See Compare Match Output Unit on page 115.).
For detailed timing information refer to Timer/Counter Timing Diagrams on page 120.
17.7.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is
always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its
maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the
Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The
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TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with
the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by
software. There are no special cases to consider in the normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the output compare to
generate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
17.7.2
TCNTn
OCn
(Toggle)
Period
(COMn1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If
the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value
must be done with care since the CTC mode does not have the double buffering feature. If the new value written
to OCR2 is lower than the current value of TCNT2, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match
can occur.
For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will
have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is
defined by the following equation:
f clk_I/O
f OCn = ----------------------------------------------2 N ( 1 + OCRn )
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
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17.7.3
TCNTn
OCn
(COMn1:0 = 2)
OCn
(COMn1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled,
the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the
COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM21:0 to 3 (see Table 17-4 on page 126). The actual OC2 value will only be visible on the port pin if the
data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2
Register at the compare match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the
timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnPWM = -----------------N 256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output
in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM21:0 bits.)
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A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to
toggle its logical level on each compare match (COM21:0 = 1). The waveform generated will have a maximum
frequency of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode,
except the double buffer feature of the output compare unit is enabled in the fast PWM mode.
17.7.4
OCRn Update
TCNTn
OCn
(COMn1:0 = 2)
OCn
(COMn1:0 = 3)
Period
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting
the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM21:0 to 3 (see Table 17-5 on page 126). The actual OC2 value will only be visible on the port pin if the
data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2
Register at the compare match between OCR2 and TCNT2 when the counter increments, and setting (or
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clearing) the OC2 Register at compare match between OCR2 and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnPCPWM = -----------------N 510
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output
in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if
set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output
will have the opposite logic values.
At the very start of Period 2 in Figure 17-7 OCn has a transition from high to l ow even though there is no
Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases
that will give transition without Compare Match:
17.8
OCR2A changes its value from Max, like in Figure 17-7. When the OCR2A value is MAX the OCn pin
value is the same as the result of a down-counting Compare Match. To ensure symmetry around
BOTTOM the OCn value at MAX must be correspond the the result of an up-counting Compare Match.
The Timer starts counting from a value higher than the one in OCR2A, and for that reason misses the
Compare Match and hence the OCn that would have happened on the way up.
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 17-9 shows the same timing data, but with the prescaler enabled.
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Figure 17-9.
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 17-10 shows the setting of OCF2 in all modes except CTC mode.
Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRn
OCRn - 1
OCRn
OCRn + 1
OCRn + 2
OCRn Value
OCFn
Figure 17-11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
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Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
TOP - 1
TOP
OCRn
BOTTOM
BOTTOM + 1
TOP
OCFn
17.9
Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer
Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is:
3.
4.
5.
6.
The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the
TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be
more than four times the Oscillator frequency.
When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary
register, and latched after two positive edges on TOSC1. The user should not write a new value before the
contents of the temporary register have been transferred to its destination. Each of the three mentioned
registers have their individual temporary register, which means for example that writing to TCNT2 does
not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place,
the Asynchronous Status Register ASSR has been implemented.
When entering Power-save or Extended Standby mode after having written to TCNT2, OCR2, or TCCR2,
the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the
device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly
important if the Output Compare2 interrupt is used to wake up the device, since the output compare
function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU
enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match
interrupt, and the MCU will not wake up.
If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby mode,
precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one
TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether
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the time before re-entering Power-save or Extended Standby mode is sufficient, the following algorithm
can be used to ensure that one TOSC1 cycle has elapsed:
1. Write a value to TCCR2, TCNT2, or OCR2.
2.
Wait until the corresponding Update Busy Flag in ASSR returns to zero.
3.
When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is always
running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Powerdown or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one
second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after
power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers
must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal
upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
Description of wake up from Power-save or Extended Standby mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle
of the timer clock, that is, the timer is always advanced by at least one before the processor can read the
counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result.
Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a
register synchronized to the internal I/O clock domain. Synchronization takes place for every rising
TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active,
TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The
phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it
depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
3.
Read TCNT2.
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer
takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before
the processor can read the timer value causing the setting of the Interrupt Flag. The output compare pin is
changed on the timer clock and is not synchronized to the processor clock.
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PSR2
clkT2S/1024
clkT2S/256
clkT2S/128
AS2
clkT2S/64
Clear
clkT2S/32
TOSC1
clkT2S
clkT2S/8
clkI/O
CS20
CS21
CS22
The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O
clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2
are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve
as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz
crystal. Applying an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256,
and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR
Special Function IO Register on page 129, resets the prescaler. This allows the user to operate with a
predictable prescaler.
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FOC2
WGM20
COM21
COM20
WGM21
CS22
CS21
CS20
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TCCR2
Mode
WGM21
(CTC2)
WGM20
(PWM2)
Timer/Counter Mode of
Operation
TOP
Update of
OCR2
TOV2 Flag
Set on
Normal
0xFF
Immediate
MAX
0xFF
TOP
BOTTOM
CTC
OCR2
Immediate
MAX
Fast PWM
0xFF
BOTTOM
MAX
Note:
1.
The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the
functionality and location of these bits are compatible with previous versions of the timer.
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When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting.
Table 17-3 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (nonPWM).
Table 17-3.
COM21
COM20
Description
Table 17-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode.
Table 17-4.
COM21
COM20
Reserved
Note:
1.
Description
A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored,
but the set or clear is done at BOTTOM. See Fast PWM Mode on page 118 for more details.
Table 17-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode
.
Table 17-5.
COM21
COM20
Reserved
Clear OC2 on compare match when up-counting. Set OC2 on compare match
when downcounting.
Set OC2 on compare match when up-counting. Clear OC2 on compare match
when downcounting.
Note:
1.
Description
A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored,
but the set or clear is done at TOP. See Phase Correct PWM Mode on page 119 for more details.
CS22
CS21
CS20
Description
clkT2S/(No prescaling)
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Table 17-6.
CS22
CS21
CS20
Description
TCNT2[7:0]
TCNT2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8bit counter. Writing to the TCNT2 Register blocks (removes) the compare match on the following timer clock.
Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match
between TCNT2 and the OCR2 Register.
17.11.3 OCR2 Output Compare Register
Bit
OCR2[7:0]
OCR2
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The Output Compare Register contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on
the OC2 pin.
17.11.4 ASSR Asynchronous Status Register
Bit
AS2
TCN2UB
OCR2UB
TCR2UB
Read/Write
R/W
Initial Value
ASSR
127
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TIMSK
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TIFR
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ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SFIOR
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18.
18.1
Features
Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16A
and peripheral devices or between several AVR devices. The ATmega16A SPI iSPI Block Diagram(1)
DIVIDER
/2/4/8/16/32/64/128
SPI2X
SPI2X
18.2
Note:
1. Refer to Figure 1-1 on page 3, and Table 12-6 on page 57 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-1. The system consists of
two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when
pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their
respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange
data. Data is always shifted from Master to Slave on the Master Out Slave In, MOSI, line, and from Slave to
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Master on the Master In Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave
by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled
by user software before communication can start. When this is done, writing a byte to the SPI Data Register
starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the
SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in
the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it
into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is
driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not
be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been
completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR
Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR
before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 18-1.
MASTER
LSB
MISO
MISO
SPI
CLOCK GENERATOR
MSB
SLAVE
LSB
MOSI
SCK
SCK
SS
SHIFT
ENABLE
SS
The system is single buffered in the transmit direction and double buffered in the receive direction. This means
that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed.
When receiving data, however, a received character must be read from the SPI Data Register before the next
character has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling
of the clock signal, the minimum low and high periods should be:
Low periods: Longer than 2 CPU clock cycles.
High periods: Longer than 2 CPU clock cycles.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 18-1 on page 132. For more details on automatic port overrides, refer to Alternate Port Functions on
page 53.
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Table 18-1.
Pin
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
Note:
See Alternate Functions of Port B on page 57 for a detailed description of how to define the direction of the user
defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a simple
transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the
SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins.
For example if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
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C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
}
Note:
1.
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output,
ldi
out
; Enable SPI
ldi
out
ret
SPI_SlaveReceive:
; Wait for reception complete
sbis
SPSR,SPIF
rjmp
SPI_SlaveReceive
; Read received data and return
in
r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return data register */
return SPDR;
}
Note:
18.3
18.3.1
1.
SS Pin Functionality
Slave Mode
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI
is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is
driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive,
which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven
high.
The SS pin is useful for packet/byte synchronization to keep the Slave Bit Counter synchronous with the Master
Clock generator. When the SS pin is driven high, the SPI Slave will immediately reset the send and receive
logic, and drop any partially received data in the Shift Register.
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18.3.2
Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS
pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically,
the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by
peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system
interprets this as another Master selecting the SPI as a Slave and starting to send data to it. To avoid bus
contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2.
The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt
routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is
driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by
a Slave Select, it must be set by the user to re-enable SPI Master mode.
18.4
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by
control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 18-2 and Figure 18-3. Data
bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals
to stabilize. This is clearly seen by summarizing Table 18-3 and Table 18-4, as done below:
Table 18-2.
Trailing Edge
SPI Mode
CPOL = 0, CPHA = 0
Sample (Rising)
Setup (Falling)
CPOL = 0, CPHA = 1
Setup (Rising)
Sample (Falling)
CPOL = 1, CPHA = 0
Sample (Falling)
Setup (Rising)
CPOL = 1, CPHA = 1
Setup (Falling)
Sample (Rising)
Figure 18-2.
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
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Figure 18-3.
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
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18.5
18.5.1
Register Description
SPCR SPI Control Register
Bit
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SPCR
CPOL Functionality
CPOL
Leading Edge
Trailing Edge
Rising
Falling
Falling
Rising
CPHA Functionality
CPHA
Leading Edge
Trailing Edge
Sample
Setup
Setup
Sample
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Table 18-5.
18.5.2
SPI2X
SPR1
SPR0
SCK Frequency
fosc/4
fosc/16
fosc/64
fosc/128
fosc/2
fosc/8
fosc/32
fosc/64
SPIF
WCOL
SPI2X
Read/Write
R/W
Initial Value
SPSR
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18.5.3
MSB
0
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SPDR
Undefined
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift
Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register
Receive buffer to be read.
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19.
USART
19.1
Features
19.2
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible
serial communication device. A simplified block diagram of the USART transmitter is shown in Figure 19-1. CPU
accessible I/O Registers and I/O pins are shown in bold.
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Figure 19-1.
Clock Generator
UBRR[H:L]
OSC
SYNC LOGIC
PIN
CONTROL
XCK
Transmitter
TX
CONTROL
UDR (Transmit)
DATABUS
PARITY
GENERATOR
TxD
Receiver
CLOCK
RECOVERY
RX
CONTROL
DATA
RECOVERY
PIN
CONTROL
UDR (Receive)
PARITY
CHECKER
UCSRA
Note:
PIN
CONTROL
UCSRB
RxD
UCSRC
1. Refer to Figure 1-1 on page 3, Table 12-14 on page 63, and Table 12-8 on page 59 for USART pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock
Generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic
consists of synchronization logic for external clock input used by synchronous Slave operation, and the baud
rate generator. The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitter
consists of a single write buffer, a serial Shift Register, parity generator and control logic for handling different
serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames.
The Receiver is the most complex part of the USART module due to its clock and data recovery units. The
recovery units are used for asynchronous data reception. In addition to the recovery units, the receiver includes
a parity checker, control logic, a Shift Register and a two level receive buffer (UDR). The receiver supports the
same frame formats as the transmitter, and can detect frame error, data overrun and parity errors.
19.2.1
Transmitter Operation
Receiver Operation
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However, the receive buffering has two improvements that will affect the compatibility in some special cases:
z
A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
Therefore the UDR must only be read once for each incoming data! More important is the fact that the
Error Flags (FE and DOR) and the 9th data bit (RXB8) are buffered with the data in the receive buffer.
Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status
will be lost since the buffer state is lost.
The receiver Shift Register can now act as a third buffer level. This is done by allowing the received data
to remain in the serial Shift Register (see Figure 19-1) if the Buffer Registers are full, until a new start bit is
detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions.
The following control bits have changed name, but have same functionality and register location:
19.3
OR is changed to DOR
Clock Generation
The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports
four modes of clock operation: Normal Asynchronous, Double Speed Asynchronous, Master Synchronous and
Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between
asynchronous and synchronous operation. Double Speed (Asynchronous mode only) is controlled by the U2X
found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the
XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The
XCK pin is only active when using Synchronous mode.
Figure 19-2 shows a block diagram of the clock generation logic.
Figure 19-2.
fosc
Prescaling
Down-Counter
UBRR+1
/2
/4
/2
0
1
0
OSC
DDR_XCK
xcki
XCK
Pin
Sync
Register
Edge
Detector
UMSEL
xcko
DDR_XCK
txclk
UCPOL
rxclk
Signal description:
txclk
rxclk
xcki
Input from XCK pin (Internal Signal). Used for synchronous Slave operation.
xcko
Clock output to XCK pin (Internal Signal). Used for synchronous Master
operation.
fosc
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19.3.1
f OSC
BAUD = --------------------------------------16 ( UBRR + 1 )
f OSC
UBRR = ------------------------ 1
16BAUD
f OSC
BAUD = ----------------------------------8 ( UBRR + 1 )
f OSC
UBRR = -------------------- 1
8BAUD
f OSC
BAUD = ----------------------------------2 ( UBRR + 1 )
f OSC
UBRR = -------------------- 1
2BAUD
Operating Mode
Asynchronous Normal Mode
(U2X = 0)
Note:
1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD
fOSC
UBRR
Some examples of UBRR values for some system clock frequencies are found in Table 19-9 (see page
163).
19.3.2
19.3.3
External Clock
External clocking is used by the synchronous Slave modes of operation. The description in this section refers to
Figure 19-2 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of metastability. The output from the synchronization register must then pass through an edge detector before it can be
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used by the Transmitter and receiver. This process introduces a two CPU clock period delay and therefore the
maximum external XCK clock frequency is limited by the following equation:
f OSC
f XCK < ----------4
Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some
margin to avoid possible loss of data due to frequency variations.
19.3.4
XCK
RxD / TxD
Sample
XCK
UCPOL = 0
RxD / TxD
Sample
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data
change. As Figure 19-3 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled
at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK
edge.
19.4
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and
optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame
formats:
z
1 start bit
5, 6, 7, 8, or 9 data bits
1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle (high) state. Figure 19-4 illustrates the possible combinations of the
frame formats. Bits inside brackets are optional.
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Figure 19-4.
Frame Formats
FRAME
(IDLE)
St
St
(n)
Sp
[5]
[6]
[7]
[8]
(St / IDLE)
IDLENo transfers on the communication line (RxD or TxD). An IDLE line must be
high.
The frame format used by the USART is set by the UCSZ2:0, UPM1:0, and USBS bits in UCSRB and UCSRC.
The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will
corrupt all ongoing communication for both the Receiver and Transmitter.
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity
mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by
the USART Stop Bit Select (USBS) bit. The receiver ignores the second stop bit. An FE (Frame Error) will
therefore only be detected in the cases where the first stop bit is zero.
19.4.1
Podd
dn
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
19.5
USART Initialization
The USART has to be initialized before any communication can take place. The initialization process normally
consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending
on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts
globally disabled) when doing the initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing
transmissions during the period the registers are changed. The TXC Flag can be used to check that the
Transmitter has completed all transfers, and the RXC Flag can be used to check that there are no unread data
in the receive buffer. Note that the TXC Flag must be cleared before each transmission (before UDR is written)
if it is used for this purpose.
The following simple USART initialization code examples show one assembly and one C function that are equal
in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed
frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter
is assumed to be stored in the r17:r16 registers. When the function writes to the UCSRC Register, the URSEL
bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC.
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C Code Example(1)
#define FOSC 1843200// Clock Speed
#define BAUD 9600
#define MYUBRR FOSC/16/BAUD-1
void main( void )
{
:.
USART_Init ( MYUBRR );
:.
}
void USART_Init( unsigned int ubrr)
{
/* Set baud rate */
UBRRH = (unsigned char)(ubrr>>8);
UBRRL = (unsigned char)ubrr;
/* Enable receiver and transmitter */
UCSRB = (1<<RXEN)|(1<<TXEN);
/* Set frame format: 8data, 2stop bit */
UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);
}
Note:
1.
More advanced initialization routines can be made that include frame format as parameters, disable interrupts
and so on. However, many applications use a fixed setting of the Baud and Control Registers, and for these
types of applications the initialization code can be placed directly in the main routine, or be combined with
initialization code for other I/O modules.
19.6
19.6.1
146
transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate
given by the Baud Register, U2X bit or by XCK depending on mode of operation.
The following code examples show a simple USART transmit function based on polling of the Data Register
Empty (UDRE) Flag. When using frames with less than eight bits, the most significant bits written to the UDR
are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data
to be sent is assumed to be stored in Register R16.
Assembly Code Example(1)
USART_Transmit:
; Wait for empty transmit buffer
sbis
UCSRA,UDRE
rjmp
USART_Transmit
; Put data (r16) into buffer, sends the data
out
UDR,r16
ret
C Code Example(1)
void USART_Transmit( unsigned char data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRA & (1<<UDRE)) )
;
/* Put data into buffer, sends the data */
UDR = data;
}
Note:
1.
The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with
new data to be transmitted. If the Data Register Empty Interrupt is utilized, the interrupt routine writes the data
into the buffer.
19.6.2
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C Code Example(Note:)
void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRA & (1<<UDRE))) )
;
/* Copy 9th bit to TXB8 */
UCSRB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDR = data;
}
Note:
These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRB is
static. (i.e., only the TXB8 bit of the UCSRB Register is used after initialization).
The ninth bit can be used for indicating an address frame when using multi processor communication mode or
for other protocol handling as for example synchronization.
19.6.3
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application must enter receive mode and free the communication bus immediately after completing the
transmission.
When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit Complete
Interrupt will be executed when the TXC Flag becomes set (provided that global interrupts are enabled). When
the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXC Flag, this is
done automatically when the interrupt is executed.
19.6.4
Parity Generator
The parity generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPM1 = 1),
the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is
sent.
19.6.5
19.7
19.7.1
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.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis
UCSRA, RXC
rjmp
USART_Receive
; Get and return received data from buffer
in
r16, UDR
ret
C Code Example(1)
unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRA & (1<<RXC)) )
;
/* Get and return received data from buffer */
return UDR;
}
Note:
1.
The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading
the buffer and returning the value.
19.7.2
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The following code example shows a simple USART receive function that handles both 9-bit characters and the
status bits.
Assembly Code Example(1)
USART_Receive:
; Wait for data to be received
sbis
UCSRA, RXC
rjmp
USART_Receive
; Get status and 9th bit, then data from buffer
in
r18, UCSRA
in
r17, UCSRB
in
r16, UDR
; If error, return -1
andi
r18,(1<<FE)|(1<<DOR)|(1<<PE)
breq
USART_ReceiveNoError
ldi
r17, HIGH(-1)
ldi
r16, LOW(-1)
USART_ReceiveNoError:
; Filter the 9th bit, then return
lsr
r17
andi
r17, 0x01
ret
C Code Example(1)
unsigned int USART_Receive( void )
{
unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRA & (1<<RXC)) )
;
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSRA;
resh = UCSRB;
resl = UDR;
/* If error, return -1 */
if ( status & (1<<FE)|(1<<DOR)|(1<<PE) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
}
Note:
1.
The receive function example reads all the I/O Registers into the Register File before any computation is done.
This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as
early as possible.
19.7.3
151
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete
Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When
interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in
order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
19.7.4
19.7.5
Parity Checker
The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be
performed (odd or even) is selected by the UPM0 bit. When enabled, the parity checker calculates the parity of
the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of
the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag
can then be read by software to check if the frame had a parity error.
The PE bit is set if the next character that can be read from the receive buffer had a parity error when received
and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is
read.
19.7.6
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19.7.7
UCSRA, RXC
r16, UDR
USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
}
Note:
19.8
19.8.1
IDLE
START
BIT 0
Sample
(U2X = 0)
10
11
12
13
14
15
16
Sample
(U2X = 1)
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection
sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic
then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated
with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these
three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the
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receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock
recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for
each start bit.
19.8.2
BIT n
Sample
(U2X = 0)
10
11
12
13
14
15
16
Sample
(U2X = 1)
The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three
samples in the center of the received bit. The center samples are emphasized on the figure by having the
sample number inside boxes. The majority voting process is done as follows: If two or all three samples have
high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received
bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on
the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop
bit. Note that the receiver only uses the first stop bit of a frame.
Figure 19-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next
frame.
Figure 19-7.
RxD
STOP 1
(A)
(B)
(C)
Sample
(U2X = 0)
10
0/1
0/1
0/1
Sample
(U2X = 1)
0/1
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is
registered to have a logic 0 value, the Frame Error (FE) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used
for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 197. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early
start bit detection influences the operational range of the receiver.
19.8.3
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internally generated baud rate of the receiver does not have a similar (see Table 19-2) base frequency, the
receiver will not be able to synchronize the frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud
rate.
( D + 1 )S
R slow = ------------------------------------------S 1 + D S + SF
( D + 2 )S
R fast = ----------------------------------( D + 1 )S + S M
D
SF
First sample number used for majority voting. SF = 8 for Normal Speed and
SF = 4 for Double Speed mode.
SM
Middle sample number used for majority voting. SM = 9 for Normal Speed and
SM = 5 for Double Speed mode.
Rslow
is the ratio of the slowest incoming data rate that can be accepted in relation to the
receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be
accepted in relation to the receiver baud rate.
Table 19-2 and Table 19-3 list the maximum receiver baud rate error that can be tolerated. Note that Normal
Speed mode has higher toleration of baud rate variations.
Table 19-2.
Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0)
D
# (Data+Parity Bit)
Rslow (%)
Rfast(%)
93.20
106.67
+6.67/-6.8
3.0
94.12
105.79
+5.79/-5.88
2.5
94.81
105.11
+5.11/-5.19
2.0
95.36
104.58
+4.58/-4.54
2.0
95.81
104.14
+4.14/-4.19
1.5
10
96.17
103.78
+3.78/-3.83
1.5
Table 19-3.
Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1)
D
# (Data+Parity Bit)
Rslow (%)
Rfast (%)
94.12
105.66
+5.66/-5.88
2.5
94.92
104.92
+4.92/-5.08
2.0
95.52
104.35
+4.35/-4.48
1.5
96.00
103.90
+3.90/-4.00
1.5
96.39
103.53
+3.53/-3.61
1.5
10
96.70
103.23
+3.23/-3.30
1.0
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The recommendations of the maximum receiver baud rate error was made under the assumption that the
receiver and transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The receivers system clock (XTAL) will always
have some minor instability over the supply voltage range and the temperature range. When using a crystal to
generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than
2% depending of the resonators tolerance. The second source for the error is more controllable. The baud rate
generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case
an UBRR value that gives an acceptable low error can be used if possible.
19.9
19.9.1
Using MPCM
For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ = 7). The ninth bit (TXB8)
must be set when an address frame (TXB8 = 1) or cleared when a data frame (TXB = 0) is being transmitted.
The Slave MCUs must in this case be set to use a 9-bit character frame format.
The following procedure should be used to exchange data in Multi-processor Communication mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set).
2.
The Master MCU sends an address frame, and all Slaves receive and read this frame. In the Slave
MCUs, the RXC Flag in UCSRA will be set as normal.
3.
Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the
MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps the MPCM setting.
4.
The addressed MCU will receive all data frames until a new address frame is received. The other Slave
MCUs, which still have the MPCM bit set, will ignore the data frames.
5.
When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCM bit and
waits for a new address frame from Master. The process then repeats from 2.
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change
between using n and n+1 character frame formats. This makes full-duplex operation difficult since the
transmitter and receiver uses the same character size setting. If 5- to 8-bit character frames are used, the
transmitter must be set to use two stop bit (USBS = 1) since the first stop bit is used for indicating the frame
type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares
the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI
instructions.
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C Code Example(1)
:.
/* Set UBRRH to 2 */
UBRRH = 0x02;
:.
/* Set the USBS and the UCSZ1 bit to one, and */
/* the remaining bits to zero. */
UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);
:.
Note:
1.
As the code examples illustrate, write accesses of the two registers are relatively unaffected of the sharing of I/O
location.
19.10.2 Read Access
Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most
applications, it is rarely necessary to read any of these registers.
The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register
contents. If the register location was read in previous system clock cycle, reading the register in the current
clock cycle will return the UCSRC contents. Note that the timed sequence for reading the UCSRC is an atomic
operation. Interrupts must therefore be controlled (for example by disabling interrupts globally) during the read
operation.
The following code example shows how to read the UCSRC Register contents.
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C Code Example(1)
unsigned char USART_ReadUCSRC( void )
{
unsigned char ucsrc;
/* Read UCSRC */
ucsrc = UBRRH;
ucsrc = UCSRC;
return ucsrc;
}
Note:
1.
RXB[7:0]
UDR (Read)
TXB[7:0]
UDR (Write)
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O
address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the
destination for data written to the UDR Register location. Reading the UDR Register location will return the
contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the
Receiver.
The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR
when the UDRE Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit
buffer, and the Transmitter is enabled, the Transmitter will load the data into the transmit Shift Register when the
Shift Register is empty. Then the data will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is
accessed. Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on
this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state
of the FIFO.
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RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
Read/Write
R/W
R/W
R/W
Initial Value
UCSRA
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transmitter is unaffected by the MPCM setting. For more detailed information see Multi-processor
Communication Mode on page 156.
19.11.3 UCSRB USART Control and Status Register B
Bit
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
UCSRB
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URSEL
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
UCSRC
The UCSRC Register shares the same I/O location as the UBRRH Register. See the Accessing UBRRH/
UCSRC Registers on page 157 section which describes how to access this register.
Bit 7 URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC.
The URSEL must be one when writing the UCSRC.
Bit 6 UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 19-4.
UMSEL
Mode
Asynchronous Operation
Synchronous Operation
UPM1
UPM0
Parity Mode
Disabled
Reserved
Stop Bit(s)
1-bit
2-bit
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UCSZ2
UCSZ1
UCSZ0
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
UCPOL
15
14
13
12
URSEL
11
10
UBRR[11:8]
UBRRH
UBRR[7:0]
7
Read/Write
Initial Value
UBRRL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The UBRRH Register shares the same I/O location as the UCSRC Register. See the Accessing UBRRH/
UCSRC Registers on page 157 section which describes how to access this register.
Bit 15 URSEL: Register Select
This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when reading
UBRRH. The URSEL must be zero when writing the UBRRH.
Bit 14:12 Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero
when UBRRH is written.
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BaudRate
Table 19-9.
fosc = 1.8432MHz
fosc = 2.0000MHz
Baud
Rate
(bps)
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
2400
25
0.2%
51
0.2%
47
0.0%
95
0.0%
51
0.2%
103
0.2%
4800
12
0.2%
25
0.2%
23
0.0%
47
0.0%
25
0.2%
51
0.2%
9600
-7.0%
12
0.2%
11
0.0%
23
0.0%
12
0.2%
25
0.2%
14.4k
8.5%
-3.5%
0.0%
15
0.0%
-3.5%
16
2.1%
19.2k
8.5%
-7.0%
0.0%
11
0.0%
-7.0%
12
0.2%
28.8k
8.5%
8.5%
0.0%
0.0%
8.5%
-3.5%
38.4k
-18.6%
8.5%
0.0%
0.0%
8.5%
-7.0%
57.6k
8.5%
8.5%
0.0%
0.0%
8.5%
8.5%
76.8k
-18.6%
-25.0%
0.0%
-18.6%
8.5%
115.2k
8.5%
0.0%
0.0%
8.5%
8.5%
230.4k
0.0%
250k
0.0%
Max (1)
1.
U2X = 0
U2X = 1
62.5kbps
125kbps
U2X = 0
U2X = 1
115.2kbps
U2X = 0
230.4kbps
125kbps
U2X = 1
250kbps
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Table 19-10.
fosc = 4.0000MHz
fosc = 7.3728MHz
Baud
Rate
(bps)
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
2400
95
0.0%
191
0.0%
103
0.2%
207
0.2%
191
0.0%
383
0.0%
4800
47
0.0%
95
0.0%
51
0.2%
103
0.2%
95
0.0%
191
0.0%
9600
23
0.0%
47
0.0%
25
0.2%
51
0.2%
47
0.0%
95
0.0%
14.4k
15
0.0%
31
0.0%
16
2.1%
34
-0.8%
31
0.0%
63
0.0%
19.2k
11
0.0%
23
0.0%
12
0.2%
25
0.2%
23
0.0%
47
0.0%
28.8k
0.0%
15
0.0%
-3.5%
16
2.1%
15
0.0%
31
0.0%
38.4k
0.0%
11
0.0%
-7.0%
12
0.2%
11
0.0%
23
0.0%
57.6k
0.0%
0.0%
8.5%
-3.5%
0.0%
15
0.0%
76.8k
0.0%
0.0%
8.5%
-7.0%
0.0%
11
0.0%
115.2k
0.0%
0.0%
8.5%
8.5%
0.0%
0.0%
230.4k
0.0%
0.0%
8.5%
8.5%
0.0%
0.0%
250k
-7.8%
-7.8%
0.0%
0.0%
-7.8%
-7.8%
0.5M
-7.8%
0.0%
-7.8%
-7.8%
1M
-7.8%
Max (1)
230.4kbps
1.
U2X = 0
U2X = 1
U2X = 0
460.8kbps
250kbps
U2X = 1
0.5Mbps
U2X = 0
U2X = 1
460.8kbps
921.6kbps
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Table 19-11.
fosc = 8.0000MHz
fosc = 14.7456MHz
Baud
Rate
(bps)
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
UBRR
Error
2400
207
0.2%
416
-0.1%
287
0.0%
575
0.0%
383
0.0%
767
0.0%
4800
103
0.2%
207
0.2%
143
0.0%
287
0.0%
191
0.0%
383
0.0%
9600
51
0.2%
103
0.2%
71
0.0%
143
0.0%
95
0.0%
191
0.0%
14.4k
34
-0.8%
68
0.6%
47
0.0%
95
0.0%
63
0.0%
127
0.0%
19.2k
25
0.2%
51
0.2%
35
0.0%
71
0.0%
47
0.0%
95
0.0%
28.8k
16
2.1%
34
-0.8%
23
0.0%
47
0.0%
31
0.0%
63
0.0%
38.4k
12
0.2%
25
0.2%
17
0.0%
35
0.0%
23
0.0%
47
0.0%
57.6k
-3.5%
16
2.1%
11
0.0%
23
0.0%
15
0.0%
31
0.0%
76.8k
-7.0%
12
0.2%
0.0%
17
0.0%
11
0.0%
23
0.0%
115.2k
8.5%
-3.5%
0.0%
11
0.0%
0.0%
15
0.0%
230.4k
8.5%
8.5%
0.0%
0.0%
0.0%
0.0%
250k
0.0%
0.0%
-7.8%
-7.8%
-7.8%
5.3%
0.5M
0.0%
0.0%
-7.8%
-7.8%
-7.8%
1M
0.0%
-7.8%
-7.8%
Max (1)
1.
U2X = 0
U2X = 1
0.5Mbps
1Mbps
U2X = 0
U2X = 1
691.2kbps
U2X = 0
1.3824Mbps
921.6kbps
U2X = 1
1.8432Mbps
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Table 19-12.
U2X = 1
UBRR
Error
UBRR
Error
2400
416
-0.1%
832
0.0%
4800
207
0.2%
416
-0.1%
9600
103
0.2%
207
0.2%
14.4k
68
0.6%
138
-0.1%
19.2k
51
0.2%
103
0.2%
28.8k
34
-0.8%
68
0.6%
38.4k
25
0.2%
51
0.2%
57.6k
16
2.1%
34
-0.8%
76.8k
12
0.2%
25
0.2%
115.2k
-3.5%
16
2.1%
230.4k
8.5%
-3.5%
250k
0.0%
0.0%
0.5M
0.0%
0.0%
1M
0.0%
0.0%
Max (1)
1.
1Mbps
2Mbps
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20.
20.1
Features
20.2
Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed
Both Master and Slave Operation Supported
Device Can Operate as Transmitter or Receiver
7-bit Address Space allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition causes Wake-up when AVR is in Sleep Mode
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
20.2.1
TWI Terminology
The following definitions are frequently encountered in this section.
Table 20-1.
TWI Terminology
Term
Description
Master
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
Slave
Transmitter
Receiver
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20.2.2
Electrical Interconnection
As depicted in Figure 20-1, both bus lines are connected to the positive supply voltage through pull-up resistors.
The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND
function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one
or more TWI devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing
the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered
in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF
and the 7-bit Slave address space. A detailed specification of the electrical characteristics of the TWI is given in
Two-wire Serial Interface Characteristics on page 283. Two different sets of specifications are presented
there, one relevant for bus speeds below 100kHz, and one valid for bus speeds up to 400kHz.
20.3
20.3.1
Data Validity
SDA
SCL
Data Stable
Data Stable
Data Change
20.3.2
SDA
SCL
START
STOP START
REPEATED START
STOP
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20.3.3
Addr LSB
R/W
ACK
SDA
SCL
1
START
20.3.4
Data LSB
ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
receiverR
SCL from
Master
1
SLA+R/W
7
Data Byte
STOP, REPEATED
START or Next
Data Byte
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20.3.5
Addr LSB
R/W
ACK
Data MSB
Data LSB
ACK
SDA
SCL
1
START
20.4
SLA+R/W
7
Data Byte
STOP
An algorithm must be implemented allowing only one of the Masters to complete the transmission. All
other Masters should cease transmission when they discover that they have lost the selection process.
This selection process is called arbitration. When a contending Master discovers that it has lost the
arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by
the winning Master. The fact that multiple Masters have started transmission at the same time should not
be detectable to the Slaves, i.e., the data being transferred on the bus must not be corrupted.
Different Masters may use different SCL frequencies. A scheme must be devised to synchronize the serial
clocks from all Masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate
the arbitration process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all Masters will
be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the
shortest high period. The low period of the combined clock is equal to the low period of the Master with the
longest low period. Note that all Masters listen to the SCL line, effectively starting to count their SCL high and
low time-out periods when the combined SCL line goes high or low, respectively.
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Figure 20-7.
TA high
SCL from
Master A
SCL from
Master B
SCL bus
Line
TBlow
Masters Start
Counting Low Period
TBhigh
Masters Start
Counting High Period
Arbitration is carried out by all Masters continuously monitoring the SDA line after outputting data. If the value
read from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a
Master can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The
losing Master should immediately go to Slave mode, checking if it is being addressed by the winning Master.
The SDA line should be left high, but losing Masters are allowed to generate a clock signal until the end of the
current data or address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several Masters are trying to address the same Slave, arbitration will continue into the data packet.
Figure 20-8.
Master A Loses
Arbitration, SDAA SDA
SDA from
Master B
SDA Line
Synchronized
SCL Line
It is the user softwares responsibility to ensure that these illegal arbitration conditions never occur. This implies
that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets.
In other words: All transmissions must contain the same number of data packets, otherwise the result of the
arbitration is undefined.
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20.5
SDA
Spike
Filter
Slew-rate
Control
Spike
Filter
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Ack
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
TWI Unit
Address Comparator
20.5.1
20.5.2
Note:
Note: Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load.
See Table 27-4 on page 283 for value of pull-up resistor.
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20.5.3
20.5.4
20.5.5
Control Unit
The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control
Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI
Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a
status code identifying the event. The TWSR only contains relevant status information when the TWI Interrupt
Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status
information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application
software to complete its tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
20.6
After the TWI has been addressed by own Slave address or general call
After a STOP or REPEATED START has been received while still addressed as a Slave.
When a bus error has occurred due to an illegal START or STOP condition
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When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this
case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The
application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the
TWCR and TWDR Registers.
Figure 20-10 is a simple example of how the application can interface to the TWI hardware. In this example, a
Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed
explanation follows later in this section. A simple code example implementing the desired behavior is also
presented.
Figure 20-10. Interfacing the Application to the TWI in a Typical Transmission
Application
Action
1. Application
writes to TWCR to
initiate
transmission of
START
TWI bus
START
2. TWINT set.
Status code indicates
START condition sent
TWI
Hardware
Action
SLA+W
4. TWINT set.
Status code indicates
SLA+W sent, ACK
received
Data
6. TWINT set.
Status code indicates
data sent, ACK received
STOP
Indicates
TWINT set
1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific
value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is
described later on. However, it is important that the TWINT bit is set in the value written. Writing a one
to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START
condition.
2.
When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated
with a status code indicating that the START condition has successfully been sent.
3.
The application software should now examine the value of TWSR, to make sure that the START condition
was successfully transmitted. If TWSR indicates otherwise, the application software might take some
special action, like calling an error routine. Assuming that the status code is as expected, the application
must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has
been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI
hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it
is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI
will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has
cleared TWINT, the TWI will initiate transmission of the address packet.
4.
When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated
with a status code indicating that the address packet has successfully been sent. The status code will also
reflect whether a Slave acknowledged the packet or not.
5.
The application software should now examine the value of TWSR, to make sure that the address packet
was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates
otherwise, the application software might take some special action, like calling an error routine. Assuming
that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a
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specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present
in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in
the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as
the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate
transmission of the data packet.
6.
When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with
a status code indicating that the data packet has successfully been sent. The status code will also reflect
whether a Slave acknowledged the packet or not.
7.
The application software should now examine the value of TWSR, to make sure that the data packet was
successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise,
the application software might take some special action, like calling an error routine. Assuming that the
status code is as expected, the application must write a specific value to TWCR, instructing the TWI
hardware to transmit a STOP condition. Which value to write is described later on. However, it is important
that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start
any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared
TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a
STOP condition has been sent.
Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be
summarized as follows:
z
When the TWI has finished an operation and expects application response, the TWINT Flag is set. The
SCL line is pulled low until TWINT is cleared.
When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next
TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus
cycle.
After all TWI Register updates and other pending application software tasks have been completed, TWCR
is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The
TWI will then commence executing whatever operation was specified by the TWCR setting.
In the following an assembly and C implementation of the example is given. Note that the code below assumes
that several definitions have been made, for example by using include-files.
ldi
r16, (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
out
Comments
TWCR = (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
TWCR, r16
wait1:
in
C example
r16,TWCR
sbrs r16,TWINT
rjmp wait1
in
r16,TWSR
r16, START
brne ERROR
ldi
r16, SLA_W
TWDR = SLA_W;
out
TWDR, r16
ldi
out
TWCR, r16
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wait2:
in
C example
Comments
r16,TWCR
sbrs r16,TWINT
rjmp wait2
in
r16,TWSR
ERROR();
r16, MT_SLA_ACK
brne ERROR
ldi
r16, DATA
TWDR = DATA;
out
TWDR, r16
ldi
out
TWCR, r16
wait3:
in
r16,TWCR
sbrs r16,TWINT
rjmp wait3
in
r16,TWSR
if ((TWSR & 0xF8) != MT_DATA_ACK) Check value of TWI Status Register. Mask
ERROR();
prescaler bits. If status different from
MT_DATA_ACK go to ERROR
r16, MT_DATA_ACK
brne ERROR
ldi
r16, (1<<TWINT)|(1<<TWEN)|
TWCR = (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO)
out
20.7
(1<<TWSTO);
TWCR, r16
Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver
(MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same
application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the
data back from the EEPROM. If other Masters are present in the system, some of these might transmit data to
the TWI, and then SR mode would be used. It is the application software that decides which modes are legal.
The following sections describe each of these modes. Possible status codes are described along with figures
detailing data transmission in each of the modes. These figures contain the following abbreviations:
S:
START condition
Rs:
R:
W:
A:
A:
STOP condition
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When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate software action. For
each status code, the required software action and details of the following serial transfer are given in Table 20-2
to Table 20-5. Note that the prescaler bits are masked to zero in these tables.
20.7.1
Device 1
Device 2
MASTER
TRANSMITTER
SLAVE
RECEIVER
........
Device 3
R1
Device n
R2
SDA
SCL
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START
condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the Two-wire Serial
Bus and generate a START condition as soon as the bus becomes free. After a START condition has been
transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be $08 (See Table 20-2). In
order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the
following value to TWCR:
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is set again and
a number of status codes in TWSR are possible. Possible status codes in Master mode are $18, $20, or $38.
The appropriate action to be taken for each of these status codes is detailed in Table 20-2.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing
the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded,
and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following
value to TWCR:
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
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This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP
condition or a repeated START condition. A STOP condition is generated by writing the following value to
TWCR:
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
After a repeated START condition (state $10) the Two-wire Serial Interface can access the same Slave again,
or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between
Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus.
Table 20-2.
Status Code
(TWSR)
Prescaler Bits
are 0
To TWCR
To/from TWDR
STA
STO
TWINT
TWEA
$08
Load SLA+W
$10
Load SLA+W or
Load SLA+R
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
No TWDR action or
No TWDR action
$18
$20
$28
$30
$38
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Successfull
transmission
to a slave
receiver
SLA
$08
DATA
$18
$28
Next transfer
started with a
repeated start
condition
RS
SLA
$10
Not acknowledge
received after the
slave address
$20
MR
Not acknowledge
received after a data
byte
$30
Arbitration lost in slave
address or data byte
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
$68
20.7.2
A or A
Other master
continues
$38
Other master
continues
$78
DATA
To corresponding
states in slave mode
$B0
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Device 1
Device 2
MASTER
RECEIVER
SLAVE
TRANSMITTER
........
Device 3
R1
Device n
R2
SDA
SCL
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit
a START condition and TWINT must be set to clear the TWINT Flag. The TWI will then test the Two-wire Serial
Bus and generate a START condition as soon as the bus becomes free. After a START condition has been
transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be $08 (See Table 20-2). In
order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the
TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the
following value to TWCR:
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is set again and a
number of status codes in TWSR are possible. Possible status codes in Master mode are $38, $40, or $48. The
appropriate action to be taken for each of these status codes is detailed in Table 20-3. Received data can be
read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the
last byte has been received. After the last byte has been received, the MR should inform the ST by sending a
NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated
START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
After a repeated START condition (state $10) the Two-wire Serial Interface can access the same Slave again,
or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between
Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus.
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Table 20-3.
Status Code
(TWSR)
Prescaler Bits
are 0
To TWCR
To/from TWDR
TWINT
TWEA
$08
Load SLA+R
$10
Load SLA+R or
Load SLA+W
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
X
0
$38
$40
$48
STA
STO
$50
$58
1
0
0
1
1
1
X
X
Successfull
reception
from a slave
receiver
SLA
$08
DATA
$40
DATA
$50
$58
Next transfer
started with a
repeated start
condition
RS
SLA
$10
Not acknowledge
received after the
slave address
$48
MT
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
$68
Other master
continues
$38
Other master
continues
$78
DATA
To corresponding
states in slave mode
$B0
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20.7.3
Device 1
Device 2
SLAVE
RECEIVER
MASTER
TRANSMITTER
........
Device 3
R1
Device n
R2
SDA
SCL
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
TWA6
TWA5
Value
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a
Master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the
general call address.
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the
acknowledgement of the devices own Slave address or the general call address. TWSTA and TWSTO must be
written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own Slave address (or
the general call address if enabled) followed by the data direction bit. If the direction bit is 0 (write), the TWI will
operate in SR mode, otherwise ST mode is entered. After its own Slave address and the write bit have been
received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each status code is detailed in
Table 20-4. The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master
mode (see states $68 and $78).
If the TWEA bit is reset during a transfer, the TWI will return a Not Acknowledge (1) to SDA after the next
received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While
TWEA is zero, the TWI does not acknowledge its own Slave address. However, the Two-wire Serial Bus is still
monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit
may be used to temporarily isolate the TWI from the Two-wire Serial Bus.
In all sleep modes other than Idle Mode, the clock system to the TWI is turned off. If the TWEA bit is set, the
interface can still acknowledge its own Slave address or the general call address by using the Two-wire Serial
Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low
during the wake up and until the TWINT Flag is cleared (by writing it to one). Further data reception will be
carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long startup time, the SCL line may be held low for a long time, blocking other data transmissions.
Note that the Two-wire Serial Interface Data Register TWDR does not reflect the last byte present on the bus
when waking up from these sleep modes.
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Table 20-4.
Status Code
(TWSR)
Prescaler Bits
are 0
To TWCR
To/from TWDR
STA
STO
TWINT
TWEA
No TWDR action or
$60
No TWDR action
$68
No TWDR action or
No TWDR action
$70
No TWDR action or
No TWDR action
$78
No TWDR action or
No TWDR action
$80
$88
$90
$98
No action
$A0
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SLA
DATA
$60
DATA
$80
P or S
$80
$A0
P or S
$88
Arbitration lost as master
and addressed as slave
$68
Reception of the general call
address and one or more data
bytes
General Call
DATA
$70
DATA
$90
P or S
$90
$A0
P or S
$98
Arbitration lost as master and
addressed as slave by general call
$78
DATA
20.7.4
Device 1
Device 2
SLAVE
TRANSMITTER
MASTER
RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
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To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR
TWA6
TWA5
Value
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a
Master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the
general call address.
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Value
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the
acknowledgement of the devices own Slave address or the general call address. TWSTA and TWSTO must be
written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own Slave address (or
the general call address if enabled) followed by the data direction bit. If the direction bit is 1 (read), the TWI will
operate in ST mode, otherwise SR mode is entered. After its own Slave address and the write bit have been
received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to
determine the appropriate software action. The appropriate action to be taken for each status code is detailed in
Table 20-5. The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master
mode (see state $B0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State $C0 or
state $C8 will be entered, depending on whether the Master Receiver transmits a NACK or ACK after the final
byte. The TWI is switched to the not addressed Slave mode, and will ignore the Master if it continues the
transfer. Thus the Master Receiver receives all 1 as serial data. State $C8 is entered if the Master demands
additional data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero
and expecting NACK from the Master).
While TWEA is zero, the TWI does not respond to its own Slave address. However, the Two-wire Serial Bus is
still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA
bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the
interface can still acknowledge its own Slave address or the general call address by using the Two-wire Serial
Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low
during the wake up and until the TWINT Flag is cleared (by writing it to one). Further data transmission will be
carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long startup time, the SCL line may be held low for a long time, blocking other data transmissions.
Note that the Two-wire Serial Interface Data Register TWDR does not reflect the last byte present on the bus
when waking up from these sleep modes.
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Table 20-5.
Status Code
(TWSR)
Prescaler Bits
are 0
$A8
$B0
$B8
$C0
$C8
To TWCR
To/from TWDR
STA
STO
TWINT
TWEA
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
SLA
DATA
$A8
Arbitration lost as master
and addressed as slave
DATA
$B8
P or S
$C0
$B0
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
All 1's
P or S
$C8
DATA
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20.7.5
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 20-6.
Status $F8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs
between other states, and when the TWI is not involved in a serial transfer.
Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs
when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal
positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error
occurs, TWINT is set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared by
writing a logic one to it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO
Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
Table 20-6.
Status Code
(TWSR)
Prescaler Bits
are 0
Miscellaneous States
Application Software Response
Status of the Two-wire Serial
Bus and Two-wire Serial Interface Hardware
To TWCR
To/from TWDR
$F8
No TWDR action
$00
No TWDR action
20.7.6
STA
STO
TWINT
TWEA
No TWCR action
0
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
3.
4.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what
location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave,
implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control
of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is
violated in a multi-master system, another Master can alter the data pointer in the EEPROM between steps 2
and 3, and the Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception of the data.
After a REPEATED START, the Master keeps ownership of the bus. The following figure shows the flow in this
transfer.
Figure 20-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter
SLA+W
ADDRESS
S = START
Transmitted from Master to Slave
Master Receiver
Rs
SLA+R
Rs = REPEATED START
DATA
P = STOP
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20.8
Device 1
Device 2
Device 3
MASTER
TRANSMITTER
MASTER
TRANSMITTER
SLAVE
RECEIVER
........
Device n
R1
R2
SDA
SCL
Two or more Masters are performing identical communication with the same Slave. In this case, neither
the Slave nor any of the Masters will know about the bus contention.
Two or more Masters are accessing the same Slave with different data or direction bit. In this case,
arbitration will occur, either in the READ/WRITE bit or in the data bits. The Masters trying to output a one
on SDA while another Master outputs a zero will lose the arbitration. Losing Masters will switch to not
addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on
application software action.
Two or more Masters are accessing different Slaves. In this case, arbitration will occur in the SLA bits.
Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the
winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the
READ/WRITE bit. If they are not being addressed, they will switch to not addressed Slave mode or wait
until the bus is free and transmit a new START condition, depending on application software action.
This is summarized in Figure 20-21. Possible status values are given in circles.
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SLA
Data
Own
Address / General Call
received
STOP
No
38
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Yes
Direction
Write
68/78
Read
B0
20.9
20.9.1
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Register Description
TWBR TWI Bit Rate Register
Bit
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TWBR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access
by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition,
and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates
a write collision if data is attempted written to TWDR while the register is inaccessible.
Bit 7 TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application software response.
If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT
Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one
to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note
that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI
Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.
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A general call has been received, while the TWGCE bit in the TWAR is set.
3.
A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire Serial Bus
temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.
Bit 5 TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the Two-wire Serial Bus.
The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free.
However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new
START condition to claim the bus Master status. TWSTA must be cleared by software when the START
condition has been transmitted.
Bit 4 TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When
the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the
TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI
returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance
state.
Bit 3 TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register TWDR when TWINT is low. This flag
is cleared by writing the TWDR Register when TWINT is high.
Bit 2 TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI
takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike
filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of
any ongoing operation.
Bit 1 Res: Reserved Bit
This bit is a reserved bit and will always read as zero.
Bit 0 TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long
as the TWINT Flag is high.
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20.9.3
TWS7
TWS6
TWS5
TWS4
TWS3
TWPS1
TWPS0
Read/Write
R/W
R/W
Initial Value
TWSR
TWPS1
TWPS0
Prescaler Value
16
64
To calculate bit rates, see Bit Rate Generator Unit on page 172. The value of TWPS1:0 is used in the
equation.
20.9.4
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the
last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI
Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before
the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out,
data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except
after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the
case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is
controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
Bits 7:0 TWD: TWI Data Register
These eight bits contain the next data byte to be transmitted, or the latest data byte received on the Two-wire
Serial Bus.
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20.9.5
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
TWAR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which
the TWI will respond when programmed as a Slave Transmitter or receiver. In multi-master systems, TWAR
must be set in Masters which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated
address comparator that looks for the Slave address (or general call address if enabled) in the received serial
address. If a match is found, an interrupt request is generated.
Bits 7:1 TWA[6:0]: TWI (Slave) Address Register
These seven bits constitute the Slave address of the TWI unit.
Bit 0 TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.
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21.
Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the
voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator
Output, ACO, is set. The comparators output can be set to trigger the Timer/Counter1 Input Capture function. In
addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can
select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its
surrounding logic is shown in Figure 21-1.
Figure 21-1.
ACME
ADEN
ADC MULTIPLEXER
OUTPUT (1)
Notes:
21.1
1.
2.
ADEN
MUX2:0
xxx
AIN1
xxx
AIN1
000
ADC0
001
ADC1
010
ADC2
011
ADC3
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21.2
21.2.1
ACME
ADEN
MUX2:0
100
ADC4
101
ADC5
110
ADC6
111
ADC7
Register Description
SFIOR Special Function IO Register
Bit
ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SFIOR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
N/A
ACSR
194
ACIS1/ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
Reserved
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its
Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
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22.
22.1
Features
10-bit Resolution
0.5 LSB Integral Non-linearity
2 LSB Absolute Accuracy
13 - 260 s Conversion Time
Up to 15 kSPS at Maximum Resolution
8 Multiplexed Single Ended Input Channels
7 Differential Input Channels
2 Differential Input Channels with Optional Gain of 10x and 200x(1)
Optional Left adjustment for ADC Result Readout
0 - VCC ADC Input Voltage Range
Selectable 2.56V ADC Reference Voltage
Free Running or Single Conversion Mode
ADC Start Conversion by Auto Triggering on Interrupt Sources
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
Note:
22.2
1.
The differential input channels are not tested for devices in PDIP Package. This feature is only guaranteed to
work for devices in TQFP and QFN/MLF Packages
Overview
The ATmega16A features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel
Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the pins of Port A. The singleended voltage inputs refer to 0V (GND).
The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0
and ADC3, ADC2) are equipped with a programmable gain stage, providing amplification steps of 0 dB (1x), 20
dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog
input channels share a common negative terminal (ADC1), while any other ADC input can be selected as the
positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit
resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a
constant level during conversion. A block diagram of the ADC is shown in Figure 22-1.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than 0.3 V from VCC.
See the paragraph ADC Noise Canceler on page 203 on how to connect this pin.
Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be
externally decoupled at the AREF pin by a capacitor for better noise performance.
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Figure 22-1.
INTERRUPT
FLAGS
ADTS[2:0]
TRIGGER
SELECT
ADC[9:0]
ADPS1
0
ADC DATA REGISTER
(ADCH/ADCL)
ADPS0
ADPS2
ADIF
ADATE
ADEN
ADSC
MUX1
15
MUX3
MUX2
MUX4
ADLAR
REFS1
REFS0
ADC MULTIPLEXER
SELECT (ADMUX)
ADIE
ADIF
AVCC
PRESCALER
START
GAIN SELECTION
CHANNEL SELECTION
MUX DECODER
CONVERSION LOGIC
INTERNAL 2.56V
REFERENCE
AREF
10-BIT DAC
GND
BANDGAP
REFERENCE
ADC7
POS.
INPUT
MUX
ADC MULTIPLEXER
OUTPUT
ADC4
ADC3
+
ADC2
GAIN
AMPLIFIER
ADC1
ADC0
NEG.
INPUT
MUX
22.3
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The
minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB.
Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the
REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external
capacitor at the AREF pin to improve noise immunity.
The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX. Any of the
ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs
to the ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential gain
amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage difference between the
selected input channel pair by the selected gain factor. This amplified value then becomes the analog input to
the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
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The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel
selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so
it is recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default,
the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in
ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same
conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been
read, and a conversion completes before ADCH is read, neither register is updated and the result from the
conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the
Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is
lost.
22.4
Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high
as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a
different data channel is selected while a conversion is in progress, the ADC will finish the current conversion
before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by
setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC
Trigger Select bits, ADTS in SFIOR (see description of the ADTS bits for a list of the trigger sources). When a
positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This
provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion
completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during
conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is
disabled or the global interrupt enable bit in SREG is cleared. A conversion can thus be triggered without
causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the
next interrupt event.
Figure 22-2.
PRESCALER
START
ADIF
CLKADC
ADATE
SOURCE 1
.
.
.
.
SOURCE n
CONVERSION
LOGIC
EDGE
DETECTOR
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
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this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF
is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
ADC Prescaler
ADEN
START
Reset
7-BIT ADC PRESCALER
CK/64
CK/128
CK/32
CK/8
CK/16
CK/4
CK
CK/2
22.5
ADPS0
ADPS1
ADPS2
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200
kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the
ADC can be higher than 200 kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU
frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting
from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for
as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the
following rising edge of the ADC clock cycle. See Differential Gain Channels on page 201 for details on
differential conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in
ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5
ADC clock cycles after the start of a first conversion. When a conversion is complete, the result is written to the
ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The
software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay
from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place 2 ADC clock
cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for
synchronization logic. When using Differential mode, along with Auto triggering from a source other than the
ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be
disabled and re-enabled after every conversion.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while
ADSC remains high. For a summary of conversion times, see Table 22-1.
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Figure 22-4.
First Conversion
Cycle Number
13
12
14
15
16
17
18
19
20
21
22
23
24
25
ADC Clock
ADEN
ADSC
ADIF
ADCH
MSB of Result
ADCL
LSB of Result
Figure 22-5.
Conversion
Complete
Cycle Number
Next Conversion
10
11
12
13
ADC Clock
ADSC
ADIF
ADCH
MSB of Result
ADCL
LSB of Result
Sample & Hold
MUX and REFS
Update
Figure 22-6.
Conversion
Complete
Cycle Number
Next Conversion
10
11
12
13
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
MSB of Result
ADCL
LSB of Result
Prescaler
Reset
Conversion
Complete
Prescaler
Reset
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Figure 22-7.
Cycle Number
11
12
Next Conversion
13
ADC Clock
ADSC
ADIF
ADCH
MSB of Result
ADCL
LSB of Result
Conversion
Complete
Table 22-1.
Condition
First conversion
13.5
25
1.5
13
13.5
1.5/2.5
13/14
22.5.1
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22.6
During conversion, minimum one ADC clock cycle after the trigger event.
3.
After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion.
Special care should be taken when changing differential channels. Once a differential channel has been
selected, the gain stage may take as much as 125 s to stabilize to the new value. Thus conversions should not
be started within the first 125 s after selecting a new differential channel. Alternatively, conversion results
obtained within this period should be discarded.
The same settling time should be observed for the first differential conversion after changing ADC reference (by
changing the REFS1:0 bits in ADMUX).
22.6.1
22.6.2
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AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the
internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly
connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor
between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter.
Note that VREF is a high impedant source, and only a capacitive load should be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference
voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied
to the AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC
conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard
this result.
If differential channels are used, the selected reference should not be closer to AVCC than indicated in
Table 27-6 on page 287.
22.7
Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has
been halted.
3.
If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU
and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU
before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete
interrupt request will be generated when the ADC conversion completes. The CPU will remain in active
mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and
ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to
avoid excessive power consumption. If the ADC is enabled in such sleep modes and the user wants to perform
differential conversions, the user is advised to switch the ADC off and on after waking up from sleep to prompt
an extended conversion to get a valid result.
22.7.1
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Figure 22-8.
IIH
ADCn
1..100 k
CS/H= 14 pF
IIL
VCC/2
Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog
measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following
techniques:
1. Keep analog signal paths as short as possible. Keep them well away from high-speed switching digital
tracks.
2.
The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as
shown in Figure 22-9.
3.
Use the ADC noise canceler function to reduce induced noise from the CPU.
4.
If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion
is in progress.
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
AREF
GND
AVCC
10H
PA7 (ADC7)
100nF
PA2 (ADC2)
PA1 (ADC1)
PA0 (ADC0)
VCC
Figure 22-9.
GND
22.7.2
PC7
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22.7.3
22.7.4
Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB).
Ideal value: 0 LSB.
Ideal ADC
Actual ADC
Offset
Error
Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE
to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB
Gain
Error
Ideal ADC
Actual ADC
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Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of
an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
INL
Ideal ADC
Actual ADC
VREF
Input Voltage
Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between
two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
1 LSB
DNL
0x000
0
Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of
input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB.
Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal
transition for any code. This is the compound effect of Offset, Gain Error, Differential Error, Non-linearity,
and Quantization Error. Ideal value: 0.5 LSB.
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22.8
Output Code
0x1FF
0x000
- V REF/GAIN
0x3FF
VREF/GAIN
Differential Input
Voltage (Volts)
0x200
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Table 22-2.
VADCn
Read code
VADCm + VREF/GAIN
0x1FF
511
0x1FF
511
0x1FE
510
:.
:.
:.
0x001
VADCm
0x000
0x3FF
-1
:.
:.
:.
0x201
-511
VADCm - VREF/GAIN
0x200
-512
Example:
ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)
Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV.
ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL
= 0x70, ADCH = 0x02.
22.9
Register Description
22.9.1
REFS1
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
ADMUX
REFS1
REFS0
Reserved
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to
ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the
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ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit,
see ADCL and ADCH The ADC Data Register on page 211.
Bits 4:0 MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also
select the gain for the differential channels. See Table 22-4 for details. If these bits are changed during a
conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).
Table 22-4.
MUX4:0
Single Ended
Input
00000
ADC0
00001
ADC1
00010
ADC2
00011
ADC3
00100
ADC4
00101
ADC5
00110
ADC6
00111
ADC7
01000
Positive Differential
Input
Negative Differential
Input
Gain
ADC0
ADC0
10x
N/A
ADC1
ADC0
10x
(1)
ADC0
ADC0
200x
(1)
ADC1
ADC0
200x
01100
ADC2
ADC2
10x
01101
01001
01010
01011
ADC3
ADC2
10x
(1)
ADC2
ADC2
200x
(1)
01111
ADC3
ADC2
200x
10000
ADC0
ADC1
1x
10001
ADC1
ADC1
1x
ADC2
ADC1
1x
10011
ADC3
ADC1
1x
10100
ADC4
ADC1
1x
10101
ADC5
ADC1
1x
10110
ADC6
ADC1
1x
10111
ADC7
ADC1
1x
11000
ADC0
ADC2
1x
11001
ADC1
ADC2
1x
11010
ADC2
ADC2
1x
11011
ADC3
ADC2
1x
11100
ADC4
ADC2
1x
01110
10010
N/A
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Table 22-4.
MUX4:0
11101
11110
1.22 V (VBG)
11111
0 V (GND)
Note:
22.9.2
1.
Positive Differential
Input
Negative Differential
Input
Gain
ADC5
ADC2
1x
N/A
The differential input channels are not tested for devices in PDIP Package. This feature is only guaranteed to
work for devices in TQFP and QFN/MLF Packages
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
ADCSRA
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Table 22-5.
ADPS2
ADPS1
ADPS0
Division Factor
16
32
64
128
22.9.3
ADLA
R
Bit
=
0
Read/Write
Initial Value
ADLA
R
Bit
=
1
Read/Write
Initial Value
15
14
13
12
11
10
ADC9
ADC8
ADCH
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
15
14
13
12
11
10
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
ADCL
When an ADC conversion is complete, the result is found in these two registers. If differential channels are
used, the result is presented in twos complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be
read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If
ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted.
ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in ADC Conversion Result on page 207.
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22.9.4
ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
SFIOR
ADTS2
ADTS1
ADTS0
Trigger Source
Analog Comparator
Timer/Counter0 Overflow
Timer/Counter1 Overflow
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23.
23.1
Features
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
All Internal Peripheral Units
Internal and External RAM
The Internal Register File
Program Counter
EEPROM and Flash Memories
Extensive On-chip Debug Support for Break Conditions, Including
AVR Break Instruction
Break on Change of Program Memory Flow
Single Step Break
Program Memory Breakpoints on Single Address or Address Range
Data Memory Breakpoints on Single Address or Address Range
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
23.2
Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
z
On-chip Debugging
A brief description is given in the following sections. Detailed descriptions for Programming via the JTAG
interface, and using the Boundary-scan Chain can be found in the sections Programming via the JTAG
Interface on page 267 and IEEE 1149.1 (JTAG) Boundary-scan on page 219, respectively. The On-chip
Debug support is considered being private JTAG instructions, and distributed within Atmel and to selected third
party vendors only.
Figure 23-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is
a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction
Register or one of several Data Registers as the scan chain (Shift Register) between the TDI input and TDO
output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used for board-level
testing. The JTAG Programming Interface (actually consisting of several physical and virtual Data Registers) is
used for JTAG Serial Programming via the JTAG interface. The Internal Scan Chain and Break Point Scan
Chain are used for On-chip Debugging only.
23.3
TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.
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TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan
Chains).
TDO: Test Data Out. Serial output data from Instruction register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST Test ReSeT which is not provided.
When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in
reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled
high and the JTAG is enabled for Boundary-scan and programming. In this case, the TAP output pin (TDO) is
left floating in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a
pull-up resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan
chain). The device is shipped with this fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the
debugger to be able to detect external reset sources. The debugger can also pull the RESET pin low to reset the
whole system, assuming only open collectors on the reset line are used in the application.
Block Diagram
I/O PORT 0
DEVICE BOUNDARY
JTAG PROGRAMMING
INTERFACE
TAP
CONTROLLER
AVR CPU
ID
REGISTER
M
U
X
Address
Data
BREAKPOINT
UNIT
BYPASS
REGISTER
INTERNAL
SCAN
CHAIN
PC
Instruction
FLOW CONTROL
UNIT
DIGITAL
PERIPHERAL
UNITS
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
OCD STATUS
AND CONTROL
Analog inputs
INSTRUCTION
REGISTER
FLASH
MEMORY
TDI
TDO
TCK
TMS
ANALOG
PERIPHERIAL
UNITS
Figure 23-1.
I/O PORT n
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Figure 23-2.
Test-Logic-Reset
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Pause-DR
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
23.4
Exit1-IR
Exit1-DR
Update-IR
0
TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry,
JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 23-2 depend on
the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The
initial state after a Power-On Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
z
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction
Register Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG
Instruction Register from the TDI input at the rising edge of TCK. The TMS input must be held low during
input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when
this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-
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state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a particular Data Register as path
between TDI and TDO and controls the circuitry surrounding the selected Data Register.
z
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the
parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR
states are only used for navigating the state machine.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register
Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG
instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to
remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The
MSB of the data is shifted in when this state is left by setting TMS high. While the Data Register is shifted
in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out
on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a
latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and
Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction
and using Data Registers, and some JTAG instructions may select certain functions to be performed in the RunTest/Idle, making it unsuitable as an Idle state.
Note:
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding
TMS high for five TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in Bibliography on page 218.
23.5
23.6
A scan chain on the interface between the internal AVR CPU and the internal peripheral units
All read or modify/write operations needed for implementing the Debugger are done by applying AVR
instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location
which is part of the communication interface between the CPU and the JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, 2 Program Memory
Break Points, and 2 combined Break Points. Together, the 4 Break Points can be configured as either:
z
3 Single Program Memory Break Point + 1 single Data Memory Break Point
2 single Program Memory Break Points + 2 single Data Memory Break Points
2 single Program Memory Break Points + 1 Program Memory Break Point with mask (range Break Point)
2 single Program Memory Break Points + 1 Data Memory Break Point with mask (range Break Point)
A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose,
leaving less flexibility to the end-user.
A list of the On-chip Debug specific JTAG instructions is given in On-chip Debug Specific JTAG Instructions on
page 217.
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The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse
must be programmed and no Lock bits must be set for the On-chip Debug system to work. As a security feature,
the On-chip Debug system is disabled when any Lock bits are set. Otherwise, the On-chip Debug system would
have provided a back-door into a secured device.
The AVR JTAG ICE from Atmel is a powerful development tool for On-chip Debugging of all AVR 8-bit RISC
Microcontrollers with IEEE 1149.1 compliant JTAG interface. The JTAG ICE and the AVR Studio user interface
give the user complete control of the internal resources of the microcontroller, helping to reduce development
time by making debugging easier. The JTAG ICE performs real-time emulation of the microcontroller while it is
running in a target system.
Please refer to the Support Tools section on the AVR pages on www.atmel.com for a full description of the AVR
JTEG ICE. AVR Studio can be downloaded free from Software section on the same web site.
All necessary execution commands are available in AVR Studio, both on source level and on disassembly level.
The user can execute the program, single step through the code either by tracing into or stepping over
functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop
the execution, and reset the execution target. In addition, the user can have an unlimited number of code
breakpoints (using the BREAK instruction) and up to two data memory breakpoints, alternatively combined as a
mask (range) Break Point.
23.7
23.7.1
PRIVATE0; $8
Private JTAG instruction for accessing On-chip Debug system.
23.7.2
PRIVATE1; $9
Private JTAG instruction for accessing On-chip Debug system.
23.7.3
PRIVATE2; $A
Private JTAG instruction for accessing On-chip Debug system.
23.7.4
PRIVATE3; $B
Private JTAG instruction for accessing On-chip Debug system.
23.8
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The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed,
the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures
no back-door exists for reading out the content of a secured device.
The details on programming through the JTAG interface and programming specific JTAG instructions are given
in the section Programming via the JTAG Interface on page 267.
23.9
23.9.1
Register Description
OCDR On-chip Debug Register
Bit
MSB/IDRD
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
OCDR
The OCDR Register provides a communication channel from the running program in the microcontroller to the
debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an Internal
Flag; I/O Debug Register Dirty IDRD is set to indicate to the debugger that the register has been written.
When the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD
bit. The debugger clears the IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can
only be accessed if the OCDEN Fuse is programmed, and the debugger enables access to the OCDR Register.
In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
23.10 Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
z
IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE,
1993
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992
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24.
24.1
Features
24.2
Overview
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as
well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. At
system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift
Register. An external controller sets up the devices to drive values at their output pins, and observe the input
values received from other devices. The controller compares the received data with the expected result. In this
way, Boundary-scan provides a mechanism for testing interconnections and integrity of components on Printed
Circuits Boards by using the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and
EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed
Circuit Board. Initial scanning of the Data Register path will show the ID-code of the device, since IDCODE is
the default JTAG instruction. It may be desirable to have the AVR device in Reset during Test mode. If not reset,
inputs to the device may be determined by the scan operations, and the internal software may be in an
undetermined state when exiting the Test mode. Entering reset, the outputs of any Port Pin will instantly enter
the high impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be
issued to make the shortest possible scan chain through the device. The device can be set in the reset state
either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of
the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the
output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IRRegister. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to
avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also
be used for taking a snapshot of the external pins during normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCSR must be cleared to
enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal
chip frequency is possible. The chip clock is not required to run.
24.3
Data Registers
The Data Registers relevant for Boundary-scan operations are:
z
Bypass Register
Reset Register
Boundary-scan Chain
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24.3.1
Bypass Register
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path
between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass
Register can be used to shorten the scan chain on a system when the other devices are to be tested.
24.3.2
Bit
31
Device ID
LSB
28
27
12
11
Version
Part Number
Manufacturer ID
4 bits
16 bits
11 bits
1 bit
24.3.2.1 Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number follows the
revision of the device. Revision A is 0x0, revision B is 0x1 and so on.
24.3.2.2 Part Number
The part number is a 16-bit code identifying the component. The JTAG Part Number for ATmega16A is listed in
Table 24-1.
Table 24-1.
Part Number
ATmega16A
0x9403
24.3.2.3 Manufacturer ID
The Manufacturer ID is a 11 bit code identifying the manufacturer. The JTAG manufacturer ID for Atmel is listed
in Table 24-2.
Table 24-2.
Manufacturer ID
Manufacturer
Atmel
24.3.3
Reset Register
The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states Port Pins when
reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as
there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the
part will remain reset for a Reset Time-Out Period (refer to Clock Sources on page 25) after releasing the
Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as
shown in Figure 24-2.
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Figure 24-2.
Reset Register
To
TDO
Internal Reset
ClockDR AVR_RESET
24.3.4
Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as
well as the boundary between digital and analog logic for analog circuitry having Off-chip connections.
See Boundary-scan Chain on page 222 for a complete description.
24.4
24.4.1
EXTEST; $0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry
external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all
accessible in the scan chain. For Analog circuits having Off-chip connections, the interface between the analog
and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is
driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.
The active states are:
24.4.2
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
IDCODE; $1
Optional JTAG instruction selecting the 32-bit ID-register as Data Register. The ID-register consists of a version
number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after
power-up.
The active states are:
z
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24.4.3
SAMPLE_PRELOAD; $2
Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot of the input/output pins
without affecting the system operation. However, the output latches are not connected to the pins. The
Boundary-scan Chain is selected as Data Register.
The active states are:
24.4.4
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output
latches are not connected to the pins.
AVR_RESET; $C
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG
Reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data
Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from
this chain is not latched.
The active states are:
z
24.4.5
BYPASS; $F
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
24.5
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as
well as the boundary between digital and analog logic for analog circuitry having Off-chip connection.
24.5.1
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Figure 24-3.
To Next Cell
EXTEST
Vcc
0
FF2
LD2
0
D
1
G
LD1
0
D
0
1
1
G
0
1
FF0
LD0
0
Port Pin (PXn)
0
D
1
G
ClockDR
UpdateDR
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Figure 24-4.
PUExn
PUD
DDxn
Q CLR
RESET
OCxn
WDx
Pxn
ODxn
PORTxn
Q CLR
WPx
IDxn
DATA BUS
RDx
RESET
RRx
SLEEP
SYNCHRONIZER
D
RPx
PINxn
CLK I/O
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
Note:
24.5.2
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
WDx:
RDx:
WPx:
RRx:
RPx:
CLK I/O :
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
1.
2.
A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for
digital port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able
to disconnect the slew-rate control buffer when doing boundary-scan.
Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention.
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Figure 24-5.
PUExn
OCxn
ODxn
TWIEN
Pxn
SRC
Slew-rate Limited
IDxn
24.5.3
Observe-only Cell
To
Next
Cell
ShiftDR
To System Logic
FF1
0
D
From
Previous
Cell
24.5.4
ClockDR
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XTAL1/TOSC1
To
Next
Cell
ShiftDR
XTAL2/TOSC2
Oscillator
EXTEST
To
Next
Cell
ShiftDR
ENABLE
OUTPUT
FF1
0
D
From
Previous
Cell
ClockDR
To System Logic
Figure 24-7.
UpdateDR
From
Previous
Cell
ClockDR
Table 24-3 summaries the scan registers for the external clock pin XTAL1, Oscillators with XTAL1/XTAL2
connections as well as 32 kHz Timer Oscillator.
Table 24-3.
Enable Signal
Clock Option
EXTCLKEN
EXTCLK (XTAL1)
External Clock
OSCON
OSCCK
External Crystal
External Ceramic Resonator
RCOSCEN
RCCK
External RC
OSC32EN
OSC32CK
TOSKON
TOSCK
Notes:
1.
2.
3.
24.5.5
Do not enable more than one clock source as main clock at a time.
Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the Internal
Oscillator and the JTAG TCK clock. If possible, scanning an external clock is preferred.
The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock configuration is
considered fixed for a given application. The user is advised to scan the same clock option as to be used in the
final system. The enable signals are supported in the scan chain because the system logic can disable clock
options in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not provided. The
INTCAP Fuses are not supported in the scan-chain, so the boundary scan chain can not make a XTAL
Oscillator requiring internal capacitors to run unless the fuse is correctly programmed.
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Figure 24-8.
Analog Comparator
BANDGAP
REFERENCE
ACBG
ACO
AC_IDLE
ACME
ADCEN
ADC MULTIPLEXER
OUTPUT
Figure 24-9.
General Boundary-scan Cell used for Signals for Comparator and ADC
To
Next
Cell
ShiftDR
EXTEST
0
1
To Analog Circuitry/
To Digital Logic
0
D
1
G
From
Previous
Cell
ClockDR
UpdateDR
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Table 24-4.
Signal
Name
AC_IDLE
Input
ACO
Output
Analog Comparator
Output
ACME
Input
ACBG
Input
Bandgap Reference
enable
24.5.6
Recommended Input
when Not in Use
Description
Figure 24-10 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell
from Figure 24-9 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all
analog inputs are shared with a digital port pin as well.
Figure 24-10. Analog to Digital Converter
VCCREN
AREF
IREFEN
2.56V
ref
To Comparator
PASSEN
MUXEN_7
ADC_7
MUXEN_6
ADC_6
MUXEN_5
ADC_5
MUXEN_4
ADC_4
ADCBGEN
SCTEST
1.22V
ref
EXTCH
MUXEN_3
ADC_3
MUXEN_2
ADC_2
MUXEN_1
ADC_1
MUXEN_0
ADC_0
PRECH
AREF
AREF
DACOUT
10-bit DAC
+
COMP
G10
G20
ADCEN
COMP
DAC_9..0
ACTEN
+
10x
NEGSEL_2
ADC_2
NEGSEL_1
ADC_0
20x
HOLD
GNDEN
ADC_1
NEGSEL_0
ST
ACLK
AMPEN
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Table 24-5.
Comparator Output
Input
ACTEN
Input
ADCBGEN
Input
ADCEN
Input
AMPEN
Input
DAC_9
Input
DAC_8
Input
DAC_7
Input
DAC_6
Input
DAC_5
Input
DAC_4
Input
DAC_3
Input
DAC_2
Input
DAC_1
Input
DAC_0
Input
EXTCH
Input
G10
Input
G20
Input
GNDEN
Input
HOLD
Input
IREFEN
Input
MUXEN_7
Input
MUXEN_6
Input
MUXEN_5
Input
MUXEN_4
Input
MUXEN_3
Input
MUXEN_2
Input
Signal
Name
Direction as Seen
from the ADC
Description
COMP
Output
ACLK
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Table 24-5.
Input
NEGSEL_2
Input
NEGSEL_1
Input
NEGSEL_0
Input
PASSEN
Input
PRECH
Input
SCTEST
Input
ST
Input
VCCREN
Input
Signal
Name
Direction as Seen
from the ADC
Description
MUXEN_1
Input
MUXEN_0
Note: Incorrect setting of the switches in Figure 24-10 will make signal contention and may damage the part. There are several input
choices to the S&H circuitry on the negative input of the output comparator in Figure 24-10. Make sure only one path is
selected from either one ADC pin, Bandgap reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 24-5 should be used. The
user is recommended not to use the Differential Gain stages during scan. Switch-cap based gain stages require
fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning
operations of the differential gain stage is therefore not provided.
The AVR ADC is based on the analog circuitry shown in Figure 24-10 with a successive approximation
algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that
an applied analog voltage is measured within some limits. This can easily be done without running a successive
approximation algorithm: apply the lower limit on the digital DAC[9:0] lines, make sure the output from the
comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the
comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin
as well.
When using the ADC, remember the following:
z
The Port Pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid
signal contention.
In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the
ADC. The user is advised to wait at least 200 ns after enabling the ADC before controlling/observing any
ADC signal, or perform a dummy conversion before using the first result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample
mode).
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As an example, consider the task of verifying a 1.5V 5% input signal at ADC channel 3 when the power supply
is 5.0V and AREF is externally connected to VCC.
The lower limit is:
The upper limit is:
The recommended values from Table 24-5 are used unless other values are given in the algorithm in Table 246. Only the DAC and Port Pin values of the Scan-chain are shown. The column Actions describes what JTAG
instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification
should be done on the data scanned out when scanning in the data on the same row in the table.
Table 24-6.
Step
Actions
ADCEN
DAC
MUXEN
HOLD
PRECH
PA3.
Data
PA3.
Control
PA3.
Pullup_
Enable
SAMPLE_
PRELOAD
0x200
0x08
EXTEST
0x200
0x08
0x200
0x08
0x123
0x08
0x123
0x08
0x200
0x08
0x200
0x08
0x200
0x08
0x143
0x08
10
0x143
0x08
0x200
0x08
11
Verify the
COMP bit
scanned
out to be 0
Verify the
COMP bit
scanned
out to be 1
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the
algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the number of
scan bits divided by the maximum hold time, thold,max.
24.6
Boundary-scan Order
Table 24-7 shows the scan order between TDI and TDO when the Boundary-scan chain is selected as data
path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out
order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant bits of
the scan chain regardless of which physical pin they are connected to. In Figure 24-3, PXn. Data corresponds to
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FF0, PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C
is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.
Table 24-7.
Bit Number
Signal Name
Module
140
AC_IDLE
Comparator
139
ACO
138
ACME
137
ACBG
136
COMP
135
PRIVATE_SIGNAL1(1)
134
ACLK
133
ACTEN
132
PRIVATE_SIGNAL2(2)
131
ADCBGEN
130
ADCEN
129
AMPEN
128
DAC_9
127
DAC_8
126
DAC_7
125
DAC_6
124
DAC_5
123
DAC_4
122
DAC_3
121
DAC_2
120
DAC_1
119
DAC_0
118
EXTCH
117
G10
116
G20
115
GNDEN
114
HOLD
113
IREFEN
112
MUXEN_7
ADC
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Table 24-7.
Bit Number
Signal Name
111
MUXEN_6
110
MUXEN_5
109
MUXEN_4
108
MUXEN_3
107
MUXEN_2
106
MUXEN_1
105
MUXEN_0
104
NEGSEL_2
103
NEGSEL_1
102
NEGSEL_0
101
PASSEN
100
PRECH
99
SCTEST
98
ST
97
VCCREN
96
PB0.Data
95
PB0.Control
94
PB0.Pullup_Enable
93
PB1.Data
92
PB1.Control
91
PB1.Pullup_Enable
90
PB2.Data
89
PB2.Control
88
PB2.Pullup_Enable
87
PB3.Data
86
PB3.Control
85
PB3.Pullup_Enable
84
PB4.Data
83
PB4.Control
82
PB4.Pullup_Enable
81
PB5.Data
80
PB5.Control
79
PB5.Pullup_Enable
78
PB6.Data
77
PB6.Control
76
PB6.Pullup_Enable
Module
Port B
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Table 24-7.
Bit Number
Signal Name
Module
75
PB7.Data
74
PB7.Control
73
PB7.Pullup_Enable
72
RSTT
71
RSTHV
70
EXTCLKEN
69
OSCON
68
RCOSCEN
67
OSC32EN
66
EXTCLK (XTAL1)
65
OSCCK
64
RCCK
63
OSC32CK
62
TWIEN
TWI
61
PD0.Data
Port D
60
PD0.Control
59
PD0.Pullup_Enable
58
PD1.Data
57
PD1.Control
56
PD1.Pullup_Enable
55
PD2.Data
54
PD2.Control
53
PD2.Pullup_Enable
52
PD3.Data
51
PD3.Control
50
PD3.Pullup_Enable
49
PD4.Data
48
PD4.Control
47
PD4.Pullup_Enable
46
PD5.Data
45
PD5.Control
44
PD5.Pullup_Enable
43
PD6.Data
42
PD6.Control
41
PD6.Pullup_Enable
40
PD7.Data
Reset Logic
(Observe-Only)
Enable signals for main clock/Oscillators
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Table 24-7.
Bit Number
Signal Name
39
PD7.Control
38
PD7.Pullup_Enable
37
PC0.Data
36
PC0.Control
35
PC0.Pullup_Enable
34
PC1.Data
33
PC1.Control
32
PC1.Pullup_Enable
31
PC6.Data
30
PC6.Control
29
PC6.Pullup_Enable
28
PC7.Data
27
PC7.Control
26
PC7.Pullup_Enable
25
TOSC
24
TOSCON
23
PA7.Data
22
PA7.Control
21
PA7.Pullup_Enable
20
PA6.Data
19
PA6.Control
18
PA6.Pullup_Enable
17
PA5.Data
16
PA5.Control
15
PA5.Pullup_Enable
14
PA4.Data
13
PA4.Control
12
PA4.Pullup_Enable
11
PA3.Data
10
PA3.Control
PA3.Pullup_Enable
PA2.Data
PA2.Control
PA2.Pullup_Enable
PA1.Data
Module
Port C
Port A
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Table 24-7.
Bit Number
Signal Name
PA1.Control
PA1.Pullup_Enable
PA0.Data
PA0.Control
PA0.Pullup_Enable
Notes:
24.7
1.
2.
Module
24.8
24.8.1
Register Description
MCUCSR MCU Control and Status Register
The MCU Control and Status Register contains control bits for general MCU functions, and provides information
on which reset source caused an MCU Reset.
Bit
JTD
ISC2
JTRF
WDRF
BORF
EXTRF
PORF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
MCUCSR
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25.
25.1
Features
Read-While-Write Self-Programming
Flexible Boot Memory size
High Security (Separate Boot Lock Bits for a Flexible Protection)
Separate Fuse to Select Reset Vector
Optimized Page(1) Size
Code Efficient Algorithm
Efficient Read-Modify-Write Support
Note:
25.2
1.
A page is a section in the flash consisting of several bytes (see Table 26-5 on page 254) used during
programming. The page organization does not affect normal operation.
Overview
The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and
uploading program code by the MCU itself. This feature allows flexible application software updates controlled
by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data
interface and associated protocol to read code and write (program) that code into the Flash memory, or read the
code from the Program memory. The program code within the Boot Loader section has the capability to write
into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can
also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is
configurable with Fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set
independently. This gives the user a unique flexibility to select different levels of protection.
25.3
25.3.1
Application Section
The Application section is the section of the Flash that is used for storing the application code. The protection
level for the application section can be selected by the Application Boot Lock bits (Boot Lock bits 0), see
Table 25-2 on page 241. The Application section can never store any Boot Loader code since the SPM
instruction is disabled when executed from the Application section.
25.3.2
25.4
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(RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWW- and NRWW
sections is given in Table 25-7 on page 249 and Figure 25-2 on page 240. The main difference between the two
sections is:
z
When erasing or writing a page located inside the RWW section, the NRWW section can be read during
the operation.
When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire
operation.
Note that the user software can never read any code that is located inside the RWW section during a Boot
Loader software operation. The syntax Read-While-Write section refers to which section that is being
programmed (erased or written), not which section that actually is being read during a Boot Loader software
update.
25.4.1
25.4.2
Read-While-Write Features
Is the CPU
Halted?
Read-WhileWrite
Supported?
RWW section
NRWW section
No
Yes
NRWW section
None
Yes
No
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Figure 25-1.
Read-While-Write
(RWW) Section
Z-pointer
Addresses RWW
Section
Z-pointer
Addresses NRWW
Section
No Read-While-Write
(NRWW) Section
CPU is Halted
during the Operation
Code Located in
NRWW Section
Can be Read during
the Operation
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Memory Sections(1)
Figure 25-2.
Program Memory
BOOTSZ = '10'
Program Memory
BOOTSZ = '11'
$0000
Read-While-Write Section
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Flashend
No Read-While-Write Section
No Read-While-Write Section
Read-While-Write Section
$0000
Program Memory
BOOTSZ = '01'
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Boot Loader Flash Section
Flashend
Program Memory
BOOTSZ = '00'
$0000
Note:
25.5
1.
Read-While-Write Section
End RWW
Start NRWW
Application Flash Section
End Application
Start Boot Loader
Boot Loader Flash Section
Flashend
No Read-While-Write Section
No Read-While-Write Section
Read-While-Write Section
$0000
Flashend
The parameters in the figure above are given in Table 25-6 on page 249.
To protect only the Boot Loader Flash section from a software update by the MCU
To protect only the Application Flash section from a software update by the MCU
See Table 25-2 and Table 25-3 for further details. The Boot Lock bits can be set in software and in Serial or
Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock
(Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the
general Read/Write Lock (Lock Bit mode 3) does not control reading nor writing by LPM/SPM, if it is attempted.
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Table 25-2.
BLB0 Mode
BLB02
BLB01
4
Note:
1.
Table 25-3.
BLB1 mode
BLB12
BLB11
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read
from the Boot Loader section. If interrupt vectors are placed in
the Application section, interrupts are disabled while executing
from the Boot Loader section.
4
Note:
25.6
Protection
1.
Protection
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Table 25-4.
BOOTRST
Note:
25.6.1
Reset Address
Reset Vector = Boot Loader reset (see Table 25-6 on page 249)
SPMIE
RWWSB
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
SPMCR
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25.7
15
14
13
12
11
10
ZH (R31)
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZL (R30)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Since the Flash is organized in pages (see Table 26-5 on page 254), the Program Counter can be treated as
having two different sections. One section, consisting of the least significant bits, is addressing the words within
a page, while the most significant bits are addressing the pages. This is shown in Figure 25-3. Note that the
Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that
the Boot Loader software addresses the same page in both the Page Erase and Page Write operation. Once a
programming operation is initiated, the address is latched and the Z-pointer can be used for other operations.
The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the
Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z pointer to
store the address. Since this instruction addresses the Flash byte by byte, also the LSB (bit Z0) of the Z-pointer
is used.
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Figure 25-3.
15
ZPCMSB
ZPAGEMSB
Z - REGISTER
1 0
0
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PROGRAM MEMORY
PAGE
PCWORD
WORD ADDRESS
WITHIN A PAGE
PAGE
PCWORD[PAGEMSB:0]:
INSTRUCTION WORD
00
01
02
PAGEEND
Notes:
25.8
1. The different variables used in Figure 25-3 are listed in Table 25-8 on page 250.
2. PCPAGE and PCWORD are listed in Table 26-5 on page 254.
If only a part of the page needs to be changed, the rest of the page must be stored (for example in the
temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader
provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the
necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the
old data while loading since the page is already erased. The temporary page buffer can be accessed in a
random sequence. It is essential that the page address used in both the page erase and page write operation is
addressing the same page. See Simple Assembly Code Example for a Boot Loader on page 247 for an
assembly code example.
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25.8.1
25.8.2
Page Erase to the RWW section: The NRWW section can be read during the page erase.
Page Erase to the NRWW section: The CPU is halted during the operation.
25.8.3
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
25.8.4
Page Write to the RWW section: The NRWW section can be read during the Page Write.
Page Write to the NRWW section: The CPU is halted during the operation.
25.8.5
25.8.6
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25.8.7
R0
BLB12
BLB11
BLB02
BLB01
See Table 25-2 and Table 25-3 for how the different settings of the Boot Loader bits affect the Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is
executed within four cycles after BLBSET and SPMEN are set in SPMCR. The Z-pointer is dont care during this
operation, but for future compatibility it is recommended to load the Z-pointer with $0001 (same as used for
reading the Lock bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to 1 when
writing the Lock bits. When programming the Lock bits the entire Flash can be read during the operation.
25.8.8
25.8.9
Rd
BLB12
BLB11
BLB02
BLB01
LB2
LB1
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To
read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCR. When
an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the
value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 26-4
on page 253 for a detailed description and mapping of the Fuse Low bits.
Bit
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse High bits
(FHB) will be loaded in the destination register as shown below. Refer to Table 26-3 on page 252 for detailed
description and mapping of the Fuse High bits.
Bit
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will
be read as one.
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Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done
by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If
not, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply voltage is sufficient.
3.
Keep the AVR core in Power-down Sleep mode during periods of low VCC. This will prevent the CPU from
attempting to decode and execute instructions, effectively protecting the SPMCR Register and thus the
Flash from unintentional writes.
Symbol
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
3.7 ms
4.5 ms
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ldi
call
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in
temp1, SPMCR
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEWE
rjmp Wait_ee
; SPM timed sequence
out
SPMCR, spmcrval
spm
; restore SREG (to enable interrupts if originally enabled)
out
SREG, temp2
ret
Boot
Size
Boot
Loader
Flash
Section
End
Application
section
Boot Reset
Address (start
Boot Loader
Section)
BOOTSZ1
BOOTSZ0
128
words
$0000 $1F7F
$1F80 $1FFF
$1F7F
$1F80
256
words
$0000 $1EFF
$1F00 $1FFF
$1EFF
$1F00
512
words
$0000 $1DFF
$1E00 $1FFF
$1DFF
$1E00
1024
words
16
$0000 $1BFF
$1C00 $1FFF
$1BFF
$1C00
Note:
1.
Table 25-7.
Pages
Application
Flash
Section
Section
Pages
Address
112
$0000 - $1BFF
16
$1C00 - $1FFF
Note:
1.
For details about these two section, see NRWW No Read-While-Write Section on page 238 and RWW
Read-While-Write Section on page 238
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Table 25-8.
Explanation of Different Variables used in Figure 25-3 and the Mapping to the Z-pointer
Corresponding
Z-value(1)
Variable
PCMSB
12
PAGEMSB
Z13
Z6
PC[12:6]
Z13:Z7
PC[5:0]
Z6:Z1
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
Note:
Description
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26.
Memory Programming
26.1
Table 26-1.
Description
Default Value
1 (unprogrammed)
1 (unprogrammed)
BLB12
1 (unprogrammed)
BLB11
1 (unprogrammed)
BLB02
1 (unprogrammed)
BLB01
1 (unprogrammed)
LB2
Lock bit
1 (unprogrammed)
LB1
Lock bit
1 (unprogrammed)
Note:
1.
Bit No.
Table 26-2.
Protection Type
LB Mode
LB2
LB1
BLB0 Mode
BLB02
BLB01
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Table 26-2.
BLB12
BLB11
SPM is not allowed to write to the Boot Loader section, and LPM
executing from the Application section is not allowed to read
from the Boot Loader section. If interrupt vectors are placed in
the Application section, interrupts are disabled while executing
from the Boot Loader section.
4
Notes:
26.2
Protection Type
1.
2.
Fuse Bits
The ATmega16A has two fuse bytes. Table 26-3 and Table 26-4 describe briefly the functionality of all the fuses
and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, 0, if they are
programmed.
Table 26-3.
Fuse High
Byte
Bit No.
Description
Default Value
OCDEN(4)
Enable OCD
Enable JTAG
SPIEN(1)
CKOPT(2)
Oscillator options
1 (unprogrammed)
EESAVE
BOOTSZ1
0 (programmed)(3)
BOOTSZ0
0 (programmed)(3)
BOOTRST
1 (unprogrammed)
JTAGEN
Notes:
(5)
1.
2.
3.
4.
5.
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Table 26-4.
Fuse Low
Byte
Description
Default Value
BODLEVEL
1 (unprogrammed)
BODEN
SUT1
1 (unprogrammed)(1)
SUT0
0 (programmed)(1)
CKSEL3
0 (programmed)(2)
CKSEL2
0 (programmed)(2)
CKSEL1
0 (programmed)(2)
CKSEL0
1 (unprogrammed)(2)
Notes:
1.
2.
The default value of SUT1:0 results in maximum start-up time. SeeTable 8-9 on page 29 for details.
The default setting of CKSEL3:0 results in internal RC Oscillator @ 1MHz. See Table 8-1 on page 25 for
details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is
programmed. Program the Fuse bits before programming the Lock bits.
26.2.1
Latching of Fuses
The Fuse values are latched when the device enters programming mode and changes of the Fuse values will
have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will
take effect once it is programmed. The fuses are also latched on Power-up in Normal mode.
26.3
Signature Bytes
All Atmel AVR microcontrollers have a three-byte signature code which identifies the device. This code can be
read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate
address space.
For the ATmega16A the signature bytes are:
1. $000: $1E (indicates manufactured by Atmel)
26.4
2.
3.
Calibration Byte
The ATmega16A stores four different calibration values for the internal RC Oscillator. These bytes resides in the
signature row High Byte of the addresses 0x0000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8Mhz
respectively. During Reset, the 1MHz value is automatically loaded into the OSCCAL Register. If other
frequencies are used, the calibration value has to be loaded manually, see OSCCAL Oscillator Calibration
Register on page 30 for details.
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26.5
Page Size
Table 26-5.
Flash Size
8K words (16K bytes)
Table 26-6.
26.6
Page Size
PCWORD
No. of Pages
PCPAGE
PCMSB
64 words
PC[5:0]
128
PC[12:6]
12
EEPROM Size
Page Size
PCWORD
No. of Pages
PCPAGE
EEAMSB
512 bytes
4 bytes
EEA[1:0]
128
EEA[8:2]
26.6.1
Signal Names
In this section, some pins of the ATmega16A are referenced by signal names describing their functionality
during parallel programming, see Figure 26-1 and Table 26-7. Pins not described in the following table are
referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding
is shown in Table 26-9.
When pulsing WR or OE, the command loaded determines the action executed. The different Commands are
shown in Table 26-10.
Figure 26-1.
Parallel Programming
+5V
RDY/BSY
PD1
OE
PD2
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
+12 V
BS2
VCC
+5V
AVCC
PB7 - PB0
DATA
RESET
PA0
XTAL1
GND
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Table 26-7.
Signal Name in
Programming Mode
Pin Name
I/O
Function
RDY/BSY
PD1
OE
PD2
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
BS2
PA0
PB7-0
I/O
DATA
Table 26-8.
Pin
Symbol
Value
PAGEL
Prog_enable[3]
XA1
Prog_enable[2]
XA0
Prog_enable[1]
BS1
Prog_enable[0]
Table 26-9.
XA1
XA0
Load Flash or EEPROM Address (High or low address byte determined by BS1)
Load Data (High or Low data byte for Flash determined by BS1)
Load Command
No Action, Idle
Table 26-10.
Command Byte
Command Executed
1000 0000
Chip Erase
0100 0000
0010 0000
0001 0000
Write Flash
0001 0001
Write EEPROM
0000 1000
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Table 26-10.
Command Byte
26.7
26.7.1
Command Executed
0000 0100
0000 0010
Read Flash
0000 0011
Read EEPROM
Parallel Programming
Enter Programming Mode
The following algorithm puts the device in Parallel Programming mode:
1. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100 s.
2.
3.
Set the Prog_enable pins listed in Table 26-8 on page 255 to 0000 and wait at least 100 ns.
4.
Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied
to RESET, will cause the device to fail entering Programming mode.
Note, if External Crystal or External RC configuration is selected, it may not be possible to apply qualified
XTAL1 pulses. In such cases, the following algorithm should be followed:
1. Set Prog_enable pins listed in Table 26-8 on page 255 to 0000.
26.7.2
26.7.3
2.
Apply 4.5 - 5.5V between VCC and GND simultaneously as 11.5 - 12.5V is applied to RESET.
3.
Wait 100 s.
4.
Re-program the fuses to ensure that External Clock is selected as clock source (CKSEL3:0 = 0b0000) If
Lock bits are programmed, a Chip Erase command must be executed before changing the fuses.
5.
Exit Programming mode by power the device down or by bringing RESET pin to 0b0.
6.
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
The command needs only be loaded once when writing or reading multiple memory locations.
Skip writing the data value $FF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is
programmed) and Flash after a Chip Erase.
Address High byte needs only be loaded before programming or reading a new 256 word window in Flash
or 256 byte EEPROM. This consideration also applies to Signature bytes reading.
Chip Erase
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until
the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be
performed before the Flash and/or the EEPROM are reprogrammed.
Note:
1.
The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is programmed.
3.
Set BS1 to 0.
4.
Set DATA to 1000 0000. This is the command for Chip Erase.
5.
6.
Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
7.
256
26.7.4
Set BS1 to 0.
3.
Set DATA to 0001 0000. This is the command for Write Flash.
4.
3.
4.
Give XTAL1 a positive pulse. This loads the address Low byte.
3.
3.
4.
E. Latch Data
1. Set BS1 to 1. This selects high data byte.
2.
Give PAGEL a positive pulse. This latches the data bytes. (See Figure 26-3 for signal waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address the pages
within the FLASH. This is illustrated in Figure 26-2 on page 258. Note that if less than 8 bits are required to
address words in the page (pagesize < 256), the most significant bit(s) in the address Low byte are used to
address the page when performing a page write.
G. Load Address High byte
1. Set XA1, XA0 to 00. This enables address loading.
2.
3.
4.
Give XTAL1 a positive pulse. This loads the address High byte.
H. Program Page
1. Set BS1 = 0
2.
Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.
3.
Wait until RDY/BSY goes high. (See Figure 26-3 for signal waveforms)
I. Repeat B through H until the entire Flash is programmed or until all data has been programmed.
J. End Page Programming
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3.
Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset.
Figure 26-2.
PAGEMSB
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
PCWORD[PAGEMSB:0]:
00
INSTRUCTION WORD
01
02
PAGEEND
Note:
1.
Figure 26-3.
A
DATA
$10
D
DATA HIGH
XX
ADDR. LOW
DATA LOW
DATA HIGH
XX
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1.
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26.7.5
3.
4.
5.
Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low.
3.
Wait until to RDY/BSY goes high before programming the next page. (See Figure 26-4 for signal
waveforms)
Figure 26-4.
A
DATA
0x11
DATA
XX
ADDR. LOW
DATA
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
26.7.6
3.
4.
Set OE to 0, and BS1 to 0. The Flash word Low byte can now be read at DATA.
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26.7.7
5.
Set BS1 to 1. The Flash word High byte can now be read at DATA.
6.
Set OE to 1.
26.7.8
2.
3.
4.
Set OE to 0, and BS1 to 0. The EEPROM Data byte can now be read at DATA.
5.
Set OE to 1.
26.7.9
2.
C: Load Data Low Byte. Bit n = 0 programs and bit n = 1 erases the Fuse bit.
3.
4.
C: Load Data Low Byte. Bit n = 0 programs and bit n = 1 erases the Fuse bit.
3.
4.
5.
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Figure 26-5.
DATA
$40
DATA
XX
$40
DATA
XX
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
3.
Set OE to 0, BS2 to 0 and BS1 to 0. The status of the Fuse Low bits can now be read at DATA (0
means programmed).
3.
Set OE to 0, BS2 to 1 and BS1 to 1. The status of the Fuse High bits can now be read at DATA (0
means programmed).
4.
Set OE to 0, BS2 to 0 and BS1 to 1. The status of the Lock bits can now be read at DATA (0 means
programmed).
5.
Set OE to 1.
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Figure 26-6.
Mapping between BS1, BS2 and the Fuse- and Lock Bits during Read
DATA
Lock Bits
0
1
BS1
Fuse High Byte
BS2
26.7.12 Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash on page 257 for
details on Command and Address loading):
1. A: Load Command 0000 1000.
2.
3.
Set OE to 0, and BS1 to 0. The selected Signature byte can now be read at DATA.
4.
Set OE to 1.
26.8
3.
Set OE to 0, and BS1 to 1. The Calibration byte can now be read at DATA.
4.
Set OE to 1.
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is
pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO (output). After RESET is set
low, the Programming Enable instruction needs to be executed first before program/erase operations can be
executed. NOTE, in Table 26-11 on page 262, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface.
26.8.1
Symbol
Pins
I/O
Description
MOSI
PB5
Serial Data in
MISO
PB6
SCK
PB7
Serial Clock
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Figure 26-7.
PB5
MISO
PB6
SCK
PB7
AVCC
XTAL1
RESET
GND
Notes:
1.
2.
If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin.
VCC -0.3V < AVCC < VCC +0.3V, however, AVCC should always be within 2.7 - 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the
serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation
turns the content of every memory location in both the Program and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial
clock (SCK) input are defined as follows:
26.8.2
Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck
12 MHz
High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck
12 MHz
Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming Enable serial
instruction to pin MOSI.
3.
The SPI Serial Programming instructions will not work if the communication is out of synchronization.
When in sync. the second byte ($53), will echo back when issuing the third byte of the Programming
Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted.
If the $53 did not echo back, give RESET a positive pulse and issue a new Programming Enable
command.
4.
The Flash is programmed one page at a time. The page size is found in Table 26-5 on page 254. The memory
page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load
Program Memory Page instruction. To ensure correct loading of the page, the data Low byte must be
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loaded before data High byte is applied for a given address. The Program Memory Page is stored by
loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling is not used,
the user must wait at least tWD_FLASH before issuing the next page. (See Table 26-12). Accessing the SPI
Serial Programming interface before the Flash write operation completes can result in incorrect
programming.
26.8.3
5.
The EEPROM array is programmed one byte at a time by supplying the address and data together with
the appropriate Write instruction. An EEPROM memory location is first automatically erased before new
data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte.
(See Table 26-12). In a chip erased device, no $FFs in the data file(s) need to be programmed.
6.
Any memory location can be verified by using the Read instruction which returns the content at the
selected address at serial output MISO.
7.
At the end of the programming session, RESET can be set high to commence normal operation.
8.
26.8.4
Minimum Wait Delay before Writing the Next Flash or EEPROM Location
Symbol
tWD_FUSE
4.5 ms
tWD_FLASH
4.5 ms
tWD_EEPROM
9.0 ms
tWD_ERASE
9.0 ms
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26.8.5
Table 26-13.
Instruction Format
(1)
Instruction /Operation
Byte 1
Byte 2
Byte 3
Byte4
Programming Enable
$AC
$53
$00
$00
$AC
$80
$00
$00
Poll RDY/BSY
$F0
$00
$00
$4D
$00
Extended adr
$00
$48
adr MSB
adr LSB
$40
adr MSB
adr LSB
$C1
$00
adr LSB
data byte in
$28
adr MSB
adr LSB
$20
adr MSB
adr LSB
$A0
adr MSB
adr LSB
$58
$00
$00
$30
$00
0000 000aa
$50
$00
$00
$58
$08
$00
$50
$08
$00
$38
$00
$0b00 000bb
$4C
000a aaaa
aa00 0000
$00
$C0
adr MSB
adr LSB
data byte in
$C2
adr MSB
adr LSB
$00
$AC
$E0
$00
data byte in
$AC
$A0
$00
data byte in
$AC
$A8
$00
data byte in
Load Instructions
(1)
Read Instructions
Write Instructions
data byte in
If the LSB in RDY/BSY data byte out is 1, a programming operation is still pending. Wait until this bit returns 0
before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
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After data is loaded to the page buffer, program the EEPROM page, see Figure 26-8 on page 266.
Figure 26-8.
Byte 1
Byte 2
Adr
A
drr MS
M
MSB
SB
Bit 15 B
Byte 3
Byte 1
Byte 4
Byte 2
Adr LSB
Adr MSB
Bit 15 B
Byte 3
Byte 4
Adr
A
dr LS
LSB
SB
0
Page Buffer
Page Offset
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory/
EEPROM Memory
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26.9
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Figure 26-9.
Test-Logic-Reset
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-IR
Pause-DR
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Exit1-DR
Update-IR
0
Shift-DR: The programming enable signature is shifted into the Data Register.
Update-DR: The programming enable signature is compared to the correct value, and Programming
mode is entered if the signature is valid.
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26.10.4
PROG_COMMANDS ($5)
The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit
Programming Command Register is selected as Data Register. The active states are the following:
z
Capture-DR: The result of the previous command is loaded into the Data Register.
Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command
and shifting in the new command.
Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see
Table 26-14 below).
26.10.5
PROG_PAGELOAD ($6)
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. The 1024 bit
Virtual Flash Page Load Register is selected as Data Register. This is a virtual scan chain with length equal to
the number of bits in one Flash page. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the
Update-DR state is not used to transfer data from the Shift Register. The data are automatically transferred to
the Flash page buffer byte by byte in the Shift-DR state by an internal state machine. This is the only active
state:
Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically loaded into the
Flash page one byte at a time.
Note:
26.10.6
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in JTAG scan chain.
If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used.
PROG_PAGEREAD ($7)
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port. The 1032 bit
Virtual Flash Page Read Register is selected as Data Register. This is a virtual scan chain with length equal to
the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit. Unlike most JTAG instructions,
the Capture-DR state is not used to transfer data to the Shift Register. The data are automatically transferred
from the Flash page buffer byte by byte in the Shift-DR state by an internal state machine. This is the only active
state:
z
Note:
Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the TCK input.
The TDI input is ignored.
The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in JTAG scan chain.
If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used.
Reset Register
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A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as
there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the
part will remain reset for a Reset Time-out Period (refer to Clock Sources on page 25) after releasing the
Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as
shown in Figure 24-2 on page 221.
26.10.9 Programming Enable Register
The Programming Enable Register is a 16-bit register. The contents of this register is compared to the
programming enable signature, binary code 1010_0011_0111_0000. When the contents of the register is equal
to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on
Power-on Reset, and should always be reset when leaving Programming mode.
Figure 26-10. Programming Enable Register
TDI
D
A
T
A
$A370
Programming Enable
TDO
S
T
R
O
B
E
S
A
D
D
R
E
S
S
/
D
A
T
A
Flash
EEPROM
Fuses
Lock Bits
TDO
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Table 26-14.
Instruction
TDI sequence
TDO sequence
Notes
0100011_10000000
0110001_10000000
0110011_10000000
0110011_10000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
0110011_10000000
xxxxxox_xxxxxxxx
0100011_00010000
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
0010111_iiiiiiii
xxxxxxx_xxxxxxxx
0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110111_00000000
xxxxxox_xxxxxxxx
(2)
0100011_00000010
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
0100011_00010001
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
0110111_00000000
1110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
xxxxxox_xxxxxxxx
(2)
0100011_00000011
xxxxxxx_xxxxxxxx
0000111_aaaaaaaa
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
(2)
(9)
(9)
Low byte
High byte
(9)
(9)
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Table 26-14.
Instruction
TDI sequence
TDO sequence
0110011_bbbbbbbb
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0100011_01000000
xxxxxxx_xxxxxxxx
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
(3)
0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110111_00000000
xxxxxox_xxxxxxxx
(2)
0010011_iiiiiiii
xxxxxxx_xxxxxxxx
(3)
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
xxxxxox_xxxxxxxx
(2)
0100011_00100000
xxxxxxx_xxxxxxxx
0010011_11iiiiii
xxxxxxx_xxxxxxxx
(4)
0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
(1)
0110011_00000000
xxxxxox_xxxxxxxx
(2)
0100011_00000100
xxxxxxx_xxxxxxxx
0111110_00000000
0111111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_xxoooooo
(5)
0111110_00000000
0110010_00000000
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
(5)
Fuse High Byte
Fuse Low Byte
Lock bits
0100011_00001000
xxxxxxx_xxxxxxxx
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0110010_00000000
0110011_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
0100011_00001000
xxxxxxx_xxxxxxxx
(6)
(8)
(6)
Notes
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Table 26-14.
Instruction
TDI sequence
TDO sequence
0000011_bbbbbbbb
xxxxxxx_xxxxxxxx
0110110_00000000
0110111_00000000
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
0100011_00000000
xxxxxxx_xxxxxxxx
0110011_00000000
xxxxxxx_xxxxxxxx
This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is
normally the case).
Repeat until o = 1.
Set bits to 0 to program the corresponding fuse, 1 to unprogram the fuse.
Set bits to 0 to program the corresponding lock bit, 1 to leave the lock bit unchanged.
0 = programmed, 1 = unprogrammed.
The bit mapping for Fuses High byte is listed in Table 26-3 on page 252
The bit mapping for Fuses Low byte is listed in Table 26-4 on page 253
The bit mapping for Lock bits byte is listed in Table 26-1 on page 251
Address bits exceeding PCMSB and EEAMSB (Table 26-5 and Table 26-6) are dont care
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Figure 26-12. State Machine Sequence for Changing/Reading the Data Word
1
Test-Logic-Reset
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
1
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Update-IR
0
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TDI
State
Machine
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
TDI
State
Machine
ADDRESS
Flash
EEPROM
Fuses
Lock Bits
D
A
T
A
TDO
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Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register.
3.
Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the programming Enable Register.
4.
3.
Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 27-7 on
page 289).
3.
4.
5.
6.
7.
8.
Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table 27-7 on
page 289).
9.
A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction:
1. Enter JTAG instruction PROG_COMMANDS.
2.
3.
Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 26-5 on
page 254) is used to address within one page and must be written as 0.
4.
5.
Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first
instruction in the page and ending with the MSB of the last instruction in the page.
6.
7.
8.
Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table 27-7 on
page 289).
9.
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3.
4.
5.
A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:
1. Enter JTAG instruction PROG_COMMANDS.
2.
3.
Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 26-5 on
page 254) is used to address within one page and must be written as 0.
4.
5.
Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first
instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first
8 bits shifted out should be ignored.
6.
7.
3.
4.
5.
6.
7.
8.
Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 27-7
on page 289).
9.
Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM
26.10.20 Reading the EEPROM
1. Enter JTAG instruction PROG_COMMANDS.
2.
3.
4.
5.
Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM
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3.
Load data High byte using programming instructions 6b. A bit value of 0 will program the corresponding
fuse, a 1 will unprogram the fuse.
4.
5.
Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 27-7 on
page 289).
6.
Load data Low byte using programming instructions 6e. A 0 will program the fuse, a 1 will unprogram
the fuse.
7.
8.
Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 27-7 on
page 289).
3.
Load data using programming instructions 7b. A bit value of 0 will program the corresponding Lock bit, a
1 will leave the Lock bit unchanged.
4.
5.
Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 27-7 on
page 289).
3.
To read all Fuses and Lock bits, use programming instruction 8e.
To only read Fuse High byte, use programming instruction 8b.
To only read Fuse Low byte, use programming instruction 8c.
To only read Lock bits, use programming instruction 8d.
3.
4.
5.
Repeat steps 3 and 4 with address $01 and address $02 to read the second and third signature bytes,
respectively.
3.
4.
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27.
Electrical Characteristics
27.1
*NOTICE:
27.2
DC Characteristics
Parameter
Condition
Min
VIL
VCC=2.7 - 5.5
VIH
VIH1
Typ
Max
Units
-0.5
0.2 VCC(1)
VCC=2.7 - 5.5
0.6 VCC(2)
VCC +0.5
VCC=2.7 - 5.5
0.7 VCC(2)
VCC +0.5
VIL1
VCC=2.7 - 5.5
-0.5
0.1 VCC(1)
VIH2
VCC=2.7 - 5.5
0.9 VCC(2)
VCC +0.5
VIL2
VCC=2.7 - 5.5
-0.5
0.2 VCC
VOL
0.7
0.5
V
V
VOH
IIL
Input Leakage
Current I/O Pin
IIH
Input Leakage
Current I/O Pin
RRST
30
85
Rpu
20
50
4.2
2.2
V
V
60
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Parameter
Power-down Mode(5)
Condition
1.9
mA
15
mA
0.2
0.6
mA
2.7
mA
<8
15
<1
40
mV
50
nA
Analog Comparator
Input Leakage Current
VCC = 5V
Vin = VCC/2
5.
mA
IACLK
4.
Units
VCC = 5V
Vin = VCC/2
1.
2.
3.
Max
0.6
Analog Comparator
Input Offset Voltage
Notes:
Typ
VACIO
tACPD
Min
-50
mA
750
Analog Comparator
VCC = 2.7V
ns
500
Propagation Delay
VCC = 4.0V
Max means the highest value where the pin is guaranteed to be read as low
Min means the lowest value where the pin is guaranteed to be read as high
Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOL, for all ports, should not exceed 200mA.
2] The sum of all IOL, for port A0 - A7, should not exceed 100mA.
3] The sum of all IOL, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100mA.
TQFP and QFN/MLF Package:
1] The sum of all IOL, for all ports, should not exceed 400mA.
2] The sum of all IOL, for ports A0 - A7, should not exceed 100mA.
3] The sum of all IOL, for ports B0 - B7, should not exceed 100mA.
4] The sum of all IOL, for ports C0 - C7, should not exceed 100mA.
5] The sum of all IOL, for ports D0 - D7, xtal2, should not exceed 100mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test condition.
Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady
state conditions (non-transient), the following must be observed:
PDIP Package:
1] The sum of all IOH, for all ports, should not exceed 200mA.
2] The sum of all IOH, for port A0 - A7, should not exceed 100mA.
3] The sum of all IOH, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100mA.
TQFP and QFN/MLF Package:
1] The sum of all IOH, for all ports, should not exceed 400mA.
2] The sum of all IOH, for ports A0 - A7, should not exceed 100mA.
3] The sum of all IOH, for ports B0 - B7, should not exceed 100mA.
4] The sum of all IOL, for ports C0 - C7, should not exceed 100mA.
5] The sum of all IOL, for ports D0 - D7, xtal2, should not exceed 100mA..
Minimum VCC for Power-down is 2.5V.
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27.3
Speed Grades
Figure 27-1.
16 MHz
8 MHz
2.7V
27.4
27.4.1
4.5V
5.5V
Clock Characteristics
External Clock Drive Waveforms
Figure 27-2.
V IH1
V IL1
27.4.2
Symbol
Parameter
1/tCLCL
Oscillator Frequency
tCLCL
Clock Period
125
62.5
ns
tCHCX
High Time
50
25
ns
tCLCX
Low Time
50
25
ns
Min
Max
Min
Max
Units
16
MHz
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Figure 27-3.
Symbol
Parameter
tCLCH
Rise Time
tCHCL
Fall Time
tCLCL
Note:
1.
Table 27-1.
Notes:
27.5
Min
Max
Min
Max
Units
1.6
0.5
1.6
0.5
C [pF]
f(2)
33
22
650kHz
10
22
1. R should be in the range 3k - 100k, and C should be at least 20pF.
2. The frequency will vary with package type and board layout.
2.0MHz
VPOT
Condition
Min
Typ
Max
Units
1.4
2.3
1.3
2.3
0.9VCC
1.5
VRST
tRST
VBOT
BODLEVEL = 1
2.5
2.7
3.2
BODLEVEL = 0
3.6
4.0
4.5
tBOD
BODLEVEL = 1
BODLEVEL = 0
VHYST
Brown-out Detector
hysteresis
50
mV
VBG
tBG
IBG
Notes:
1.
2.
0.1 VCC
1.15
1.23
1.4
40
70
10
The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).
VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case,
the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will
occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
The test is performed using BODLEVEL = 1 and BODLEVEL = 0 for ATmega16A.
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27.6
Table 27-3.
Symbol
tINT
27.7
Parameter
Condition
Min
Typ
Max
Units
50
ns
Table 27-4 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega16A Two-wire
Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 27-4.
Table 27-4.
Symbol
Parameter
VIL
Min
Max
Units
Input Low-voltage
-0.5
0.3 VCC
VIH
Input High-voltage
0.7 VCC
VCC + 0.5
Vhys(1)
0.05 VCC(2)
VOL
tr
(1)
(1)
Output Low-voltage
0.4
0.1Cb(3)(2)
300
ns
20 + 0.1Cb(3)(2)
250
ns
50(2)
ns
-10
10
10
pF
400
kHz
fSCL 100kHz
V CC 0,4V
---------------------------3mA
1000ns
------------------Cb
V CC 0,4V
---------------------------3mA
300ns
---------------Cb
fSCL 100kHz
4.0
0.6
fSCL 100kHz
4.7
1.3
fSCL 100kHz
4.0
0.6
fSCL 100kHz
4.7
0.6
3.45
0.9
250
ns
100
ns
tSP(1)
Ii
Ci
fSCL
Rp
tHD;STA
tLOW
tHIGH
tSU;DAT
20 +
10pF < Cb < 400pF(3)
0.1VCC < Vi < 0.9VCC
tSU;STA
tHD;DAT
tof(1)
(1)
Condition
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Table 27-4.
Symbol
Parameter
tSU;STO
tBUF
Notes:
1.
2.
3.
4.
5.
Condition
Min
Max
Units
4.0
0.6
s
Bus free time between a STOP and START
condition
1.3
s
fSCL > 100 kHz
In ATmega16A, this parameter is characterized and not 100% tested.
Required only for fSCL > 100kHz.
Cb = capacitance of one bus line in pF.
fCK = CPU clock frequency
This requirement applies to all ATmega16A Two-wire Serial Interface operation. Other devices connected to the Twowire Serial Bus need only obey the general fSCL requirement.
Figure 27-4.
tHIGH
tLOW
tr
tLOW
SCL
tSU;STA
tHD;STA
tHD;DAT
SDA
tSU;DAT
tSU;STO
tBUF
27.8
MSB
LSB
MSB
LSB
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.
Table 27-5.
Mode
SCK period
Master
SCK high/low
Master
Rise/Fall time
Master
3.6
Setup
Master
10
Hold
Master
10
Out to SCK
Master
0.5 tSCK
SCK to out
Master
10
Master
10
SS low to out
Slave
15
10
SCK period
Slave
4 tSCK
11
SCK high/low
Slave
2 tSCK
12
Rise/Fall time
Slave
13
Setup
Slave
10
14
Hold
Slave
10
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Figure 27-6.
Min
Typ
Max
ns
1.6
15
ns
20
10
2 tSCK
SCK
(CPOL = 0)
2
SCK
(CPOL = 1)
4
MISO
(Data Input)
MSB
...
LSB
MOSI
(Data Output)
MSB
...
LSB
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Figure 27-7.
SS
10
16
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
MOSI
(Data Input)
14
12
MSB
...
LSB
15
MISO
(Data Output)
MSB
17
...
LSB
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27.9
ADC Characteristics
Table 27-6.
Symbol
ADC Characteristics
Parameter
Resolution
Min(1)
Condition
Typ(1)
Max(1)
Units
10
Bits
Differential Conversion
Gain = 1x or 10x
Bits
Differential Conversion
Gain = 200x
Bits
1.5
2.5
LSB
LSB
1.5
LSB
LSB
LSB
0.5
LSB
Gain Error
LSB
Offset Error
Conversion Time
Clock Frequency
AVCC
VREF
Reference Voltage
Input voltage
VIN
Input bandwidth
LSB
13
260
50
VCC - 0.3
1000
(2)
VCC + 0.3
kHz
(3)
2.0
AVCC
Differential Conversion
2.0
AVCC - 0.2
GND
VREF
VREF
Differential channels
Single ended channels
Differential channels
38.5
kHz
kHz
VINT
RREF
32
RAIN
100
2.3
2.6
2.9
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Notes:
XTAL1
t DVXH
t XLDX
t BVPH
PAGEL
t BVWL
t WLBX
t PHPL
t WL
WR
WH
t PLWL
WLRL
RDY/BSY
t WLRH
Figure 27-9.
LOAD DATA
(LOW BYTE)
t XLXH
tXLPH
LOAD ADDRESS
(LOW BYTE)
tPLXH
XTAL1
BS1
PAGEL
DATA
XA0
XA1
Note:
1.
The timing requirements shown in Figure 27-8 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
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Figure 27-10. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing
Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
tBVDV
BS1
tOLDV
OE
DATA
tOHDZ
XA0
XA1
Note:
1.
Table 27-7.
The timing requirements shown in Figure 27-8 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
Parallel Programming Characteristics, VCC = 5 V 10%
Symbol
Parameter
Min
VPP
11.5
IPP
tDVXH
67
ns
tXLXH
200
ns
tXHXL
150
ns
tXLDX
67
ns
tXLWL
ns
tXLPH
ns
tPLXH
150
ns
tBVPH
67
ns
tPHPL
150
ns
tPLBX
67
ns
tWLBX
67
ns
tPLWL
67
ns
tBVWL
67
ns
tWLWH
150
ns
tWLRL
tWLRH
Units
12.5
250
3.7
4.5
ms
7.5
ms
tXLOL
tBVDV
tOLDV
tOHDZ
1.
2.
Max
tWLRH_CE
Notes:
Typ
ns
250
ns
250
ns
250
ns
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
tWLRH_CE is valid for the Chip Erase command.
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28.
Typical Characteristics
The following charts show typical behavior. These figures are not tested during manufacturing. All current
consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups
enabled. A sine wave generator with rail-to-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency,
loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors
are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load
capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly
at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Powerdown mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
Active Supply Current
Figure 28-1.
1.4
5.5 V
1.2
5.0 V
1
ICC (mA)
28.0.1
4.5 V
4.0 V
3.6 V
3.3 V
0.8
0.6
2.7 V
0.4
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
290
Figure 28-2.
16
5.5 V
14
5.0 V
12
4.5 V
ICC (mA)
10
4.0 V
3.6 V
3.3 V
2.7 V
2
0
0
10
12
14
16
Frequency (MHz)
Figure 28-3.
10
85 C
25 C
9
8
-40 C
ICC (mA)
7
6
5
4
3
2
1
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
291
Figure 28-4.
85 C
25 C
-40 C
ICC (mA)
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 28-5.
85 C
25 C
-40 C
2.5
ICC (mA)
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
292
Figure 28-6.
1.6
85 C
25 C
1.4
-40 C
1.2
ICC (mA)
1
0.8
0.6
0.4
0.2
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 28-7.
140
25 C
120
ICC (uA)
100
80
60
40
20
0
2,5
3,5
4,5
5,5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
293
0.5
5.5 V
ICC (mA)
0.45
0.4
5.0 V
0.35
4.5 V
0.3
4.0 V
0.25
3.6 V
3.3 V
0.2
2.7 V
0.15
0.1
0.05
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
Figure 28-9.
8
7
5.5 V
5.0 V
5
I CC (mA)
28.0.2
4.5 V
4.0 V
3.6 V
3.3 V
1
2.7 V
0
0
10
12
14
16
Frequency (MHz)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
294
Figure 28-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
5
-40 C
4.5
25 C
85 C
ICC (mA)
3.5
3
2.5
2
1.5
1
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 28-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz)
2.5
85 C
25 C
-40 C
ICC (mA)
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
295
Figure 28-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz)
1.2
85 C
25 C
-40 C
ICC (mA)
0.8
0.6
0.4
0.2
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 28-13. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz)
0.7
85 C
25 C
-40 C
0.6
ICC (mA)
0.5
0.4
0.3
0.2
0.1
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
296
Figure 28-14. Idle Supply Current vs. VCC (32kHz External Oscillator)
30
25
25 C
ICC (uA)
20
15
10
0
2.5
3.5
4.5
5.5
VCC (V)
85 C
-40 C
1.4
1.2
ICC (uA)
28.0.3
25 C
1
0.8
0.6
0.4
0.2
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
297
Figure 28-16. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)
20
85 C
-40 C
25 C
18
16
14
ICC (uA)
12
10
8
6
4
2
0
2.5
3.5
4.5
5.5
VCC (V)
25 C
12
10
ICC (uA)
28.0.4
8
6
4
2
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
298
28.0.5
6MHz_xtal
6MHz_res
0.12
ICC (mA)
0.1
4MHz_res
4MHz_xtal
0.08
0.06
2MHz_res
2MHz_xtal
450kHz_res
0.04
1MHz_res
0.02
0
2.5
3.5
4.5
5.5
VCC (V)
Pin Pullup
Figure 28-19. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5V)
140
120
100
IOP (uA)
28.0.6
80
60
40
25 C
-40 C
85 C
20
0
0
VOP (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
299
Figure 28-20. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V)
80
70
60
IOP (uA)
50
40
30
20
25 C
-40 C
85 C
10
0
0
0.5
1.5
2.5
VOP (V)
Figure 28-21. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
120
100
25 C
-40 C
IRESET (uA)
80
85 C
60
40
20
0
0
VRESET(V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
300
Figure 28-22. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
60
25 C
-40 C
50
IRESET (uA)
40
85 C
30
20
10
0
0
0.5
1.5
2.5
VRESET(V)
-40 C
25 C
60
IOH (mA)
28.0.7
85 C
40
20
0
0
VOH (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
301
Figure 28-24. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
30
-40 C
25 C
25
85 C
IOH (mA)
20
15
10
0
0
0.5
1.5
2.5
VOH (V)
Figure 28-25. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
100
-40 C
80
25 C
85 C
IOL (mA)
60
40
20
0
0
0.5
1.5
2.5
VOL (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
302
Figure 28-26. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)
40
35
-40 C
30
25 C
IOL (mA)
25
85 C
20
15
10
5
0
0
0.5
1.5
2.5
VOL (V)
85 C
25 C
-40 C
2.5
2
Threshold (V)
28.0.8
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
303
Figure 28-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0')
2.5
25 C
85 C
2
Threshold (V)
-40 C
1.5
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
85 C
25 C
0.5
-40 C
0.45
0.4
0.35
0.3
0.25
0.2
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
304
Figure 28-30. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1')
2.5
Threshold (V)
-40 C
1.5
25 C
85 C
1
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
Figure 28-31. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0')
2.5
Threshold (V)
1.5
85 C
25 C
-40 C
0.5
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
305
0.4
-40 C
0.3
0.2
25 C
0.1
85 C
0
2.5
3.5
4.5
5.5
VCC (V)
Bod Thresholds
Figure 28-33. Bod Thresholds vs. Temperature (Bodlevel is 4.0V)
4.2
4.1
Threshold (V)
28.0.9
Rising VCC
3.9
Falling VCC
3.8
3.7
-60
-40
-20
20
40
60
80
100
Temperature (C)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
306
Threshold (V)
2.9
Rising VCC
2.8
2.7
Falling VCC
2.6
2.5
-60
-40
-20
20
40
60
80
100
Temperature (C)
85 C
1.25
25 C
1.245
1.24
1.235
-40 C
1.23
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
307
-40 C
1300
25 C
1280
F RC (kHz)
1260
85 C
1240
1220
1200
1180
1160
1140
1120
2.5
3.5
4.5
5.5
VCC (V)
8
F RC (MHz)
5.5 V
4.0 V
7
2.7 V
6
-60
-40
-20
20
40
60
80
100
Temperature (C)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
308
-40 C
25 C
8
F RC (MHz)
85 C
6
2.5
3.5
4.5
5.5
V CC (V)
25 C
12
F RC (MHz)
10
8
6
4
2
0
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
309
4.1
F RC (MHz)
5.5 V
3.9
4.0 V
3.8
3.7
2.7 V
3.6
-60
-40
-20
20
40
60
80
100
Temperature (C)
-40 C
4.1
25 C
F RC (MHz)
85 C
3.9
3.8
3.7
3.6
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
310
25 C
7
6
F RC (MHz)
5
4
3
2
1
0
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
2
F RC (MHz)
5.5 V
4.0 V
1.9
2.7 V
1.8
-60
-40
-20
20
40
60
80
100
Temperature (C)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
311
-40 C
25 C
2
F RC (MHz)
85 C
1.9
1.8
1.7
2.5
3.5
4.5
5.5
VCC (V)
25 C
F RC (MHz)
2,5
2
1,5
1
0,5
0
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
312
1
F RC (MHz)
5.5 V
4.0 V
0.95
2.7 V
0.9
-60
-40
-20
20
40
60
80
100
Temperature (C)
-40 C
25 C
1
F RC (MHz)
85 C
0.95
0.9
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
313
25 C
1.6
F RC (MHz)
1.4
1.2
1
0.8
0.6
0.4
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
ICC (uA)
20
-40 C
25 C
85 C
15
10
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
314
85 C
-40 C
25 C
300
ICC (uA)
250
200
150
100
50
0
2.5
3.5
4.5
5.5
VCC (V)
85 C
25 C
-40 C
180
160
140
ICC (uA)
120
100
80
60
40
20
0
2,5
3,5
4,5
5,5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
315
ICC (uA)
90
80
85 C
70
25 C
60
-40 C
50
40
30
20
10
0
2,5
3,5
4,5
5,5
VCC (V)
-40 C
25 C
85 C
16
ICC (uA)
12
0
2.5
3.5
4.5
5.5
VCC (V)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
316
-40 C
6
25 C
ICC (mA)
85 C
4
3
2
1
0
2.5
3.5
4.5
5.5
VCC (V)
5.5 V
2
ICC (mA)
5.0 V
4.5 V
1.5
4.0 V
3.6 V
3.3 V
2.7 V
0.5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (MHz)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
317
ICC (mA)
14
12
5.5 V
10
5.0 V
4.5 V
4.0 V
3.6 V
4
3.3 V
2.7 V
2
0
0
10
12
14
16
Frequency (MHz)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
318
29.
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$3F ($5F)
SREG
$3E ($5E)
SPH
SP10
SP9
SP8
11
SP4
SP3
SP2
SP1
SP0
11
IVSEL
IVCE
46, 67
$3D ($5D)
SPL
$3C ($5C)
OCR0
$3B ($5B)
GICR
SP7
SP6
SP5
Timer/Counter0 Output Compare Register
INT1
INT0
Page
82
INT2
$3A ($5A)
GIFR
INTF1
INTF0
INTF2
68
$39 ($59)
TIMSK
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0
$38 ($58)
TIFR
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0
$37 ($57)
SPMCR
SPMIE
RWWSB
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
242
$36 ($56)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
TWIE
189
$35 ($55)
MCUCR
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
35, 66
$34 ($54)
MCUCSR
JTD
ISC2
JTRF
WDRF
BORF
EXTRF
PORF
$33 ($53)
TCCR0
FOC0
WGM00
COM01
COM00
WGM01
CS02
CS01
CS00
79
$32 ($52)
TCNT0
(1)
$31
(1)
($51)
OSCCAL
OCDR
Timer/Counter0 (8 Bits)
81
30
218
$30 ($50)
SFIOR
ADTS2
ADTS1
ADTS0
ACME
PUD
PSR2
PSR10
64,84,129,194,212
$2F ($4F)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
FOC1A
FOC1B
WGM11
WGM10
105
$2E ($4E)
TCCR1B
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
107
$2D ($4D)
TCNT1H
108
$2C ($4C)
TCNT1L
108
$2B ($4B)
OCR1AH
$2A ($4A)
OCR1AL
109
$29 ($49)
OCR1BH
109
$28 ($48)
OCR1BL
109
$27 ($47)
ICR1H
109
$26 ($46)
ICR1L
$25 ($45)
TCCR2
$24 ($44)
TCNT2
$23 ($43)
OCR2
$22 ($42)
ASSR
$21 ($41)
(2)
$20
(2)
($40)
FOC2
WGM20
COM21
109
109
COM20
WGM21
CS22
CS21
CS20
Timer/Counter2 (8 Bits)
Timer/Counter2 Output Compare Register
125
127
127
AS2
TCN2UB
OCR2UB
TCR2UB
WDTCR
WDTOE
WDE
WDP2
WDP1
WDP0
UBRRH
URSEL
UBRR[11:8]
127
41
162
UCSRC
URSEL
UMSEL
UPM1
UPM0
USBS
UCSZ1
UCSZ0
UCPOL
161
$1F ($3F)
EEARH
EEAR8
20
$1E ($3E)
EEARL
$1D ($3D)
EEDR
$1C ($3C)
EECR
EERIE
EEMWE
EEWE
EERE
$1B ($3B)
PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
64
$1A ($3A)
DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
64
20
20
20
$19 ($39)
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
64
$18 ($38)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
64
$17 ($37)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
64
$16 ($36)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
65
$15 ($35)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
65
$14 ($34)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
65
$13 ($33)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
65
$12 ($32)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
65
$11 ($31)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
65
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
$10 ($30)
PIND
$0F ($2F)
SPDR
65
139
$0E ($2E)
SPSR
SPIF
WCOL
SPI2X
138
$0D ($2D)
SPCR
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
137
$0C ($2C)
UDR
$0B ($2B)
UCSRA
158
$0A ($2A)
UCSRB
$09 ($29)
UBRRL
$08 ($28)
ACSR
ACD
ACBG
$07 ($27)
ADMUX
REFS1
$06 ($26)
ADCSRA
ADEN
$05 ($25)
ADCH
211
$04 ($24)
ADCL
211
$03 ($23)
TWDR
$02 ($22)
TWAR
TWA6
$01 ($21)
TWSR
TWS7
$00 ($20)
TWBR
RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
159
RXCIE
TXCIE
UDRIE
RXEN
TXEN
UCSZ2
RXB8
TXB8
160
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
194
REFS0
ADLAR
MUX4
MUX3
MUX2
MUX1
MUX0
208
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
210
TWA5
TWS6
TWA4
TWS5
162
191
TWA3
TWS4
TWA2
TWS3
TWA1
TWA0
TWPS1
TWGCE
TWPS0
192
191
189
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
319
Notes:
1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the
debugger specific documentation for details on how to use the OCDR Register.
2. Refer to the USART description for details on how to access UBRRH and UCSRC.
3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate
on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
ATmega16A [DATASHEET]
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320
30.
Mnemonics
Flags
Operands
Description
Operation
#Clocks
Rd, Rr
Rd Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Rd Rd + Rr + C
Z,C,N,V,H
1
2
ADIW
Rdl,K
Rdh:Rdl Rdh:Rdl + K
Z,C,N,V,S
SUB
Rd, Rr
Rd Rd - Rr
Z,C,N,V,H
SUBI
Rd, K
Rd Rd - K
Z,C,N,V,H
SBC
Rd, Rr
Rd Rd - Rr - C
Z,C,N,V,H
SBCI
Rd, K
Rd Rd - K - C
Z,C,N,V,H
SBIW
Rdl,K
Rdh:Rdl Rdh:Rdl - K
Z,C,N,V,S
AND
Rd, Rr
Rd Rd Rr
Z,N,V
ANDI
Rd, K
Rd Rd K
Z,N,V
OR
Rd, Rr
Logical OR Registers
Rd Rd v Rr
Z,N,V
ORI
Rd, K
Rd Rd v K
Z,N,V
EOR
Rd, Rr
Exclusive OR Registers
Rd Rd Rr
Z,N,V
COM
Rd
Ones Complement
Rd $FF Rd
Z,C,N,V
1
1
NEG
Rd
Twos Complement
Rd $00 Rd
Z,C,N,V,H
SBR
Rd,K
Rd Rd v K
Z,N,V
CBR
Rd,K
Rd Rd ($FF - K)
Z,N,V
INC
Rd
Increment
Rd Rd + 1
Z,N,V
DEC
Rd
Decrement
Rd Rd 1
Z,N,V
TST
Rd
Rd Rd Rd
Z,N,V
CLR
Rd
Clear Register
Rd Rd Rd
Z,N,V
SER
Rd
Set Register
Rd $FF
None
MUL
Rd, Rr
Multiply Unsigned
R1:R0 Rd x Rr
Z,C
MULS
Rd, Rr
Multiply Signed
R1:R0 Rd x Rr
Z,C
MULSU
Rd, Rr
R1:R0 Rd x Rr
Z,C
FMUL
Rd, Rr
Z,C
FMULS
Rd, Rr
Z,C
FMULSU
Rd, Rr
1
R1:R0 (Rd x Rr) << 1
R1:R0 (Rd x Rr) << 1
Z,C
Relative Jump
PC PC + k + 1
None
PC Z
None
2
3
BRANCH INSTRUCTIONS
RJMP
IJMP
JMP
Direct Jump
PC k
None
RCALL
PC PC + k + 1
None
PC Z
None
ICALL
CALL
RET
PC k
None
Subroutine Return
PC STACK
None
Interrupt Return
PC STACK
CPSE
Rd,Rr
if (Rd = Rr) PC PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd Rr
Z, N,V,C,H
CPC
Rd,Rr
Rd Rr C
Z, N,V,C,H
CPI
Rd,K
Rd K
Z, N,V,C,H
SBRC
Rr, b
if (Rr(b)=0) PC PC + 2 or 3
None
RETI
4
1/2/3
1
1/2/3
SBRS
Rr, b
if (Rr(b)=1) PC PC + 2 or 3
None
1/2/3
SBIC
P, b
if (P(b)=0) PC PC + 2 or 3
None
1/2/3
SBIS
P, b
if (P(b)=1) PC PC + 2 or 3
None
1/2/3
BRBS
s, k
None
1/2
BRBC
s, k
None
1/2
BREQ
Branch if Equal
if (Z = 1) then PC PC + k + 1
None
1/2
BRNE
if (Z = 0) then PC PC + k + 1
None
1/2
BRCS
if (C = 1) then PC PC + k + 1
None
1/2
BRCC
if (C = 0) then PC PC + k + 1
None
1/2
BRSH
if (C = 0) then PC PC + k + 1
None
1/2
BRLO
Branch if Lower
if (C = 1) then PC PC + k + 1
None
1/2
BRMI
Branch if Minus
if (N = 1) then PC PC + k + 1
None
1/2
BRPL
Branch if Plus
if (N = 0) then PC PC + k + 1
None
1/2
BRGE
if (N V= 0) then PC PC + k + 1
None
1/2
BRLT
if (N V= 1) then PC PC + k + 1
None
1/2
BRHS
if (H = 1) then PC PC + k + 1
None
1/2
BRHC
if (H = 0) then PC PC + k + 1
None
1/2
BRTS
if (T = 1) then PC PC + k + 1
None
1/2
BRTC
if (T = 0) then PC PC + k + 1
None
1/2
ATmega16A [DATASHEET]
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321
Mnemonics
Flags
Operands
Description
Operation
#Clocks
BRVS
if (V = 1) then PC PC + k + 1
None
1/2
BRVC
if (V = 0) then PC PC + k + 1
None
1/2
BRIE
if ( I = 1) then PC PC + k + 1
None
1/2
BRID
if ( I = 0) then PC PC + k + 1
None
1/2
Rd Rr
Rd+1:Rd Rr+1:Rr
None
None
Rd, Rr
MOVW
Rd, Rr
LDI
Rd, K
Load Immediate
Rd K
None
LD
Rd, X
Load Indirect
Rd (X)
None
LD
Rd, X+
Rd (X), X X + 1
None
LD
Rd, - X
X X - 1, Rd (X)
None
LD
Rd, Y
Load Indirect
Rd (Y)
None
LD
Rd, Y+
Rd (Y), Y Y + 1
None
LD
Rd, - Y
Y Y - 1, Rd (Y)
None
LDD
Rd,Y+q
Rd (Y + q)
None
LD
Rd, Z
Load Indirect
Rd (Z)
None
LD
Rd, Z+
Rd (Z), Z Z+1
None
LD
Rd, -Z
Z Z - 1, Rd (Z)
None
LDD
Rd, Z+q
Rd (Z + q)
None
LDS
Rd, k
Rd (k)
None
ST
X, Rr
Store Indirect
(X) Rr
None
ST
X+, Rr
(X) Rr, X X + 1
None
2
2
ST
- X, Rr
X X - 1, (X) Rr
None
ST
Y, Rr
Store Indirect
(Y) Rr
None
ST
Y+, Rr
(Y) Rr, Y Y + 1
None
ST
- Y, Rr
Y Y - 1, (Y) Rr
None
STD
Y+q,Rr
(Y + q) Rr
None
ST
Z, Rr
Store Indirect
(Z) Rr
None
ST
Z+, Rr
(Z) Rr, Z Z + 1
None
ST
-Z, Rr
Z Z - 1, (Z) Rr
None
STD
Z+q,Rr
(Z + q) Rr
None
STS
k, Rr
(k) Rr
None
R0 (Z)
None
LPM
LPM
Rd, Z
Rd (Z)
None
LPM
Rd, Z+
Rd (Z), Z Z+1
None
(Z) R1:R0
None
In Port
Rd P
None
1
1
SPM
IN
Rd, P
OUT
P, Rr
Out Port
P Rr
None
PUSH
Rr
STACK Rr
None
POP
Rd
Rd STACK
None
P,b
I/O(P,b) 1
None
CBI
P,b
I/O(P,b) 0
None
LSL
Rd
Z,C,N,V
LSR
Rd
Z,C,N,V
ROL
Rd
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Z,C,N,V
ROR
Rd
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
ASR
Rd
Z,C,N,V
SWAP
Rd
Swap Nibbles
Rd(3:0)Rd(7:4),Rd(7:4)Rd(3:0)
None
BSET
Flag Set
SREG(s) 1
SREG(s)
BCLR
Flag Clear
SREG(s) 0
SREG(s)
BST
Rr, b
T Rr(b)
BLD
Rd, b
Rd(b) T
None
SEC
Set Carry
C1
CLC
Clear Carry
C0
SEN
N1
CLN
N0
SEZ
Z1
CLZ
Z0
SEI
I1
CLI
I0
1
1
SES
S1
CLS
S0
SEV
V1
CLV
SET
V0
T1
V
T
1
1
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
322
Mnemonics
Flags
Operands
CLT
SEH
CLH
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
BREAK
Description
Operation
#Clocks
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
T0
H1
H0
T
H
H
No Operation
Sleep
Watchdog Reset
Break
None
None
None
None
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
1
1
1
1
1
1
N/A
323
31.
Ordering Information
Speed (MHz)
16
Notes:
Power Supply
2.7 - 5.5V
Ordering Code(1)
ATmega16A-AU
ATmega16A-AUR(2)
ATmega16A-PU
ATmega16A-MU
ATmega16A-MUR(2)
Package
Operation Range
44A
44A
40P6
44M1
44M1
Industrial
(-40oC to 85oC)
1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
2. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
324
32.
Packaging Information
32.1
44A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
A1
A2
D1
D
0~7
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
SYMBOL
MIN
NOM
MAX
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
11.75
12.00
12.25
D1
9.90
10.00
10.10
11.75
12.00
12.25
E1
9.90
10.00
10.10
0.30
0.37
0.45
0.09
(0.17)
0.20
0.45
0.60
0.75
NOTE
Note 2
Note 2
0.80 TYP
06/02/2014
44A
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
325
32.2
40P6
D
PIN
1
E1
SEATING PLANE
A1
L
B
B1
e
E
0 ~ 15
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
SYMBOL
MIN
NOM
MAX
4.826
A1
0.381
52.070
52.578
15.240
15.875
E1
13.462
13.970
0.356
0.559
B1
1.041
1.651
3.048
3.556
0.203
0.381
eB
15.494
17.526
NOTE
Note 2
Note 2
2.540 TYP
13/02/2014
40P6
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
326
32.3
44M1
Marked Pin# 1 I D
SE ATING PLAN E
A1
TOP VIE W
A3
A
K
L
Pin #1 Co rner
D2
1
2
3
SIDE VIEW
Pin #1
Triangle
Option A
E2
Option B
Option C
Pin #1
Cham fer
(C 0.30)
Pin #1
Notch
(0.20 R)
B OT TOM VIE W
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
0.80
0.90
1.00
A1
0.02
0.05
A3
0.20 REF
0.18
0.23
0.30
6.90
7.00
7.10
D2
5.00
5.20
5.40
6.90
7.00
7.10
E2
5.00
5.20
5.40
e
Note: JEDEC Standard MO-220, Fig
. 1 (S AW Singulation) VKKD-3 .
NOT E
0.50 BSC
0.59
0.64
0.69
0.20
0.26
0.41
02/13/2014
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
44M1, 44-pad, 7 x 7 x 1.0mm body, lead
pitch 0.50mm, 5.20mm exposed pad, thermally
enhanced plastic very thin quad flat no
lead package (VQFN)
GPC
ZWS
DRAWING NO.
REV.
44M1
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
327
33.
Errata
The revision letter in this section refers to the revision of the ATmega16A device.
33.1
If ATmega16A is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega16A by issuing the IDCODE instruction or by entering
the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register
and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16A while reading the Device ID Registers of preceding devices of the boundary scan chain.
If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the
ATmega16A must be the fist device in the chain.
4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an
unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
328
34.
1.
Atmel brand style guide and datasheet template of 2014-0502 updated in datasheet including
the last page.
2.
Updated the Ordering Code to include Tape & Reel part numbers.
3.
Removed notes 6 and 7 concerning actual low period in Table 27-4 on page 283.
4.
Changed notes 3, 4 and 5, removed note 6 concerning TQFP/MLF packages in Section 27.2
DC Characteristics on page 279
1.
2.
1.
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
329
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.
Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.
6.
AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7.
AVR Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
7.2
7.3
7.4
7.5
7.6
8.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
In-System Reprogrammable Flash Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRAM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
18
19
20
9.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ALU Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General Purpose Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stack Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset and Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
24
25
25
25
27
27
28
29
30
30
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Noise Reduction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
32
32
32
33
ATmega16A [DATASHEET]
Atmel-8154C-8-bit-AVR-ATmega16A_Datasheet-07/2014
9.8
9.9
9.10
36
39
40
41
11. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
11.1
11.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ports as General Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
50
53
64
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer/Counter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compare Match Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer/Counter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
69
70
70
71
72
73
77
79
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prescaler Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
83
83
83
84
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Accessing 16-bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Timer/Counter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Input Capture Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Output Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Compare Match Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timer/Counter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer/Counter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compare Match Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer/Counter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Operation of the Timer/Counter2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer/Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
112
113
113
114
115
116
120
122
124
125
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SS Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
130
134
135
137
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USART Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transmission The USART Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Reception The USART Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-processor Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accessing UBRRH/ UCSRC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examples of Baud Rate Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
140
142
144
145
146
149
153
156
157
158
163
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-wire Serial Interface Bus Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer and Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-master Bus Systems, Arbitration and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview of the TWI Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the TWI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-master Systems and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
167
168
170
172
173
176
188
189
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22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
22.9
22.10
22.11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting a Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prescaling and Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing Channel or Reference Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Noise Canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Conversion Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADLAR = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADLAR = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
196
196
197
198
199
202
203
207
208
211
211
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Boundary-scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the On-chip Debug System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-chip Debug Specific JTAG Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the JTAG Programming Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
213
213
213
215
216
216
217
217
218
218
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-scan Specific JTAG Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-scan Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary-scan Description Language Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
219
219
219
221
222
231
236
236
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application and Boot Loader Flash Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read-While-Write and no Read-While-Write Flash Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Loader Lock Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Entering the Boot Loader Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing the Flash during Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self-Programming the Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
237
237
237
237
240
241
243
244
251
252
253
253
254
254
256
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279
281
281
282
283
283
284
287
288
44A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
40P6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
44M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
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Atmel Corporation
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
www.atmel.com