Xilinx

The OrCAD Capture v9.2.3 (and later) flow for Xilinx FPGA projects is illustrated below:

Xilinx design flow

This document takes the Xilinx A8BITBCD design from the Xilinx sample directory through the
Capture FPGA flow. The Xilinx design flow for OrCAD Capture v9.2.3 (and later) consists of the
following phases:
1. Create an FPGA design in OrCAD Capture.
2. Compile the simulation library.

3. Run pre-route simulation in Cadence NC VHDL Desktop.

4. Synthesize the FPGA design with Synplicity Synplify.
5. Place and route the design with Xilinx Alliance.
6. Run post-route simulation with NC VHDL Desktop.

Create an FPGA design in OrCAD Capture

The following steps take you through FPGA design creation in the example Xilinx flow:
1. In Capture, create a new FPGA project from the File menu. Name this project A8BITBCD.
2. Select Xilinx from the vendor list and XC4000E for the device family.
3. Browse to the location of the device library. By default, the path to the XC4000E
functional simulation library is set to ..\tools\capture\Library\FPGA\Xilinx\sim_lib\unisim.
4. Click Finish. An FPGA project, A8BITBCD, is created and linked to the Xilinx XC4000E
library.
5. Highlight the Design Resource folder in Captures project manager, add A8BITBCD.DSN
and BCD.VHD from the Capture\samples\fpga\Xilinx\sample directory to the project.
6. Save the project.
Once you have completed these steps, you are ready to perform synthesis and pre-routed
simulation.

Compile the pre-route simulation library

The following process takes you through the steps to compile the pre-route simulation
libraries for your Xilinx design.
Note: You need only compile the pre-route simulation libraries for your design once. If the
libraries have already been compiled, you can skip this process. Also, note that you must
recompile the libraries with each new version of the Cadence NC VHDL Desktop.
1. In Capture, select Tools > Compile Vendor Libraries.
2. Select Unisim VHDL libraries under the Xilinx VHDL Libraries folder in the Library
Compilation Manager window.
The Unisim VHDL libraries are functional simulation models for XC4000E, Virtex, VirtexE,
Virtex II, Spartan, Spartan II, and Spartan XL.
3. Click Browse to locate the C_UNISIM.CMD file. By default, the command file is located
at: ..\tools\capture\Library\FPGA\Xilinx.
4. Click Compile. The compiled library will be stored in
..\tools\capture\library\fpga\Xilinx\sim_lib\unisim as it is assigned in C_UNISIM.CMD. It
may take a while to complete the process.

Run pre-route simulation with Cadence NC VHDL

Desktop
Follow this procedure to perform pre-route simulation on your Xilinx design.
1. In Capture, select PICFlow > Simulate.
2. Select Preroute and click OK in the Select Simulation Configuration dialog box.
3. Enable Use Interactive mode and click Setup.
4. Verify that the paths to the HDL.VAR and DETAIL.LOG file are correct. Browse to the
sample preroute directory if necessary. Select the Testbench tab in the NCVHDL
Preroute Simulation Setup dialog box.
5. Enable Include Testbench to send the testbench along with other VHDL files to NC VHDL
Desktop.
6. Click Browse to locate the VHDL testbench, A8BIT_TB.VHD.
7. Click OK to finish the setup.
8. Click Run to launch NC VHDL Desktop.
9. Choose > Select and then Signals from the main menu in the Affirma NC VHDL Desktop
window.
10. Select Tools > Waveform. The Signalscan waveform window appears.
11. Type "run 10000 ns" at the NC VHDL Desktop command line, and press Enter.

The pre-route simulation waveforms are displayed in the Signalscan waveform window.
12. Save the session and close all windows.

Synthesize the design with Synplicity Synplify

The following steps take you through synthesis in the example Xilinx flow.
1. In Capture, select Synthesis from the PICFlow menu.
2. In the Synthesis dialog box, select Create New Synplify Project.
3. Locate the directory where you want to store the Synplify design files. By default, they
are stored in the Synthesis directory within the design directory (for example,
sample/Xilinx).
4. Click Run to launch Synplify.
5. Select Project > Implementation Options.

6. Select XC4005E from the Part list in the Device tab.

7. Click OK to save the selection.

8. If you do not want to create a constraints file, you can jump to Step 12.
9. Create a constraints file by choosing the Constraint File (SCOPE), under the New items
section in the File menu. Assign A8BITBCD as the File Name and check Add To Project
file to add the constraint file to the synthesis project.

10. Choose the Attributes tab, located in the bottom of the constraint spreadsheet. Then set
up the constraint window as follows:

Note that you can also enter constraints via a Xilinx constraint file or the Capture property
editor.
11. Close the constraints file and click Yes to save the constraint file.
12. Choose the RUN button. Synplify creates an optimized EDIF netlist. You may receive the
following warnings, which you can ignore:
@W:"c:\cadence\psd_14.2\tools\capture\samples\xilinx\preroute\a8bitbcd.vh
d":35:10:35:13|Unbound component mapped to black box
@W:"c:\cadence\psd_14.2\tools\capture\samples\xilinx\preroute\a8bitbcd.vh
d":44:10:44:14|Unbound component mapped to black box

13. Save and close the project.

You are now ready to perform place and route with your Xilinx tool set.

Run Place and route with Xilinx Alliance

The following steps take you through place and route in the example Xilinx flow.
1. In Capture, select P&R from the PICFlow menu.
2. Click Browse to locate and select the EDIF netlist generated from Synplify. By default,
Capture will point to the Synthesis directory under the design directory.
3. Click Run to launch Xilinx Design Manager.
4. In the New Version window, verify that the part selected is set to XC4005E-1-PC84. Click
OK.
5. Select Options under the Design menu. Set the Place & Route Effort Level to High Effort.
Set the Simulation field to "Generic VHDL".
6. Click the Edit Options button for Simulation. The XC4000 Simulation Options window
appears. Use the default simulation netlist name, time_sim. This means that the post
routed netlist will be saved as TIME_SIM.VHD and the standard delay file will be saved
as TIME_SIM.SDF.
7. Select the Correlate Simulation Data to Input Design option.
8. Select the VHDL/Verilog tab. Select the Generate Pin File option to create a pin file.
9. Click OK.
10. Click OK.
11. Select Design > Implement. The Flow Engine window displays the complete flow
process.
12. Save the project and exit the tool.
You are now ready for post-route simulation.

Compile the post-route simulation library

Note: You need only compile the pre-route simulation libraries for your design once. If the
libraries have already been compiled, you can skip this process. Also, note that you must
recompile the libraries with each new version of the NC VHDL Desktop.
1. In Capture, select Tools > Compile Vendor Libraries.
2. Select Simprin VHDL libraries under the Xilinx VHDL Libraries folder in the Library
Compilation Manager window.
The Simprim VHDL libraries are timed simulation models for all Xilinx device families
3. Click Browse to locate the C_SIMPRIM.CMD file. By default, the command file is located
at: ..\tools\capture\Library\FPGA\Xilinx.

4. Click Compile. The compiled library will be stored in

..tools\capture\library\fpga\Xilinx\sim_lib\simprim as it is assigned in C_SIMPRIM.CMD. It
may take a while to complete the process.

Run post-route simulation with NC VHDL Desktop

Follow this procedure to perform post-route simulation on your Xilinx design.
1. In Capture, select PICFlow > Simulate.
2. Select Postroute and click OK in the Select Simulation Configuration dialog box.
3. Click OK to accept the default path to the post route VHDL file and the SDF file that were

generated by Xilinx place and route tool. The path should indicate the postroute directory
for your design.
4. Select Use Interactive mode and click Setup in the NCVHDL Postroute Simulation dialog

box. Verify that the paths to the HDL.VAR and DETAIL.LOG file point to the postroute
directory. Verify that the Elaborate option has a path to an SDF.CMD file in the postroute
directory, also. For example:
-message -sdf_cmd_file
E:\PSD_14.2\tools\capture\samples\fpga\xilinx\SampleC\Postroute\sdf.cmd
5. Select the Testbench tab in the NCVHDL Postroute Simulation Setup dialog box.
6. Enable Include Testbench to send the testbench along with other VHDL files to NC VHDL

Desktop.
7. Click Browse to locate the VHDL testbench, A8BITBCD_TB.VHD.
8. Click OK to finish the setup.
9. Click Run to launch NC VHDL Desktop.
10. Choose Select, and then Signals from the main menu in the Affirma NC VHDL Desktop

window.
11. Select Tools > Waveform. The Signalscan waveform window appears.
12. Type "run 10000 ns" at the NC VHDL Desktop command line followed by Enter. NC

VHDL Desktop generates waveforms for the post-route simulation.

13. Save the session and close all windows.