2015

Applied Electronics Engineering

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[VHDL TUTORIAL WITH ACTIVE

HDL VHDL SOFTWARE]
A tutorial showing multiple ways to design multiplexers and encoders using Aldec Software

For more tutorials visit: http://appliedelectronicsengineering.blogspot.com

Multiplexer design using dataflow modelling style in VHDL

In the circuit design using VHDL, one can model the circuit or system in behavioral or dataflow or
structural model. This tutorial shows you how a mutiplexer can be designed using the dataflow style of
modelling.
A multiplexer has many inputs and fewer outputs. Consider two inputs a and b and one output z. An
additional input in the multiplexer is the selector input. For two inputs we have one bit selector which can
be 0 or 1. If selector bit sel is 0 then we have a as output and if the selector bit sel is 0 then we have b as
output.

From the truth table we can write the output y of the 2x1 mux as,
\[y = sel'.a+ sel.b\]
Now this form can be directly implemented in vhdl using the logical operators. The VHDL code illustrates
this simple mux dataflow model.
library ieee;
use ieee.std_logic_1164.all;
entity mux2x1 is
port(
a,b : in std_logic;
y : out std_logic;
sel: in std_logic

);
end mux2x1;
architecture dataflow of mux2x1 is
begin
y <= ((not sel) and (a)) or ((sel) and (b));
end dataflow;
The aldec vhdl software was used to verify the above code. And the simulated waveform is shown below,

Similarly we can have a 4x2 mux. In this case there are four inputs (say a,b,c,d) and the selector is 2 bit
input. When the selector is 00, then output y is a, if selector is 01 then y is b, if selector is 10 then y is c
and when selector is 11 then y is d.
From the truth table one can derive the output y in terms of selector(s1,s0) and inputs a,b,c,d as follows,
\[y = s_0'.s_1'.a+ s_0.s_1'.b+ s_0'.s_1.c+ s_0.s_1.d\]
The following shows the 4x2 mux schematic showing inputs, selector inputs and the output.

The following is the VHDL code for the 4x2 multiplexer using dataflow style of modelling.
library ieee;
use ieee.std_logic_1164.all;
entity mux2x1 is
port(
a,b,c,d : in std_logic;
y : out std_logic;
s0,s1: in std_logic
);
end mux2x1;
architecture dataflow of mux2x1 is
begin
y <= ((not s0) and (not s1) and (a)) or ((s0) and (not s1) and (b)) or ((not s0) and (s1) and (c)) or ((s0)
and (s1) and (d));
end dataflow;
The following is the simulated waveform using VHDL software.

octal to binary encoder VHDL design

Posted: 15 Feb 2015 10:44 PM PST
This VHDL tutorial shows how to model a octal to binary encoder in VHDL and simulation using VHDL
software. The octal to binary encoder is a 8 input 3 output encoder. There are multiple ways we can
implement the octal to binary encoder. First we can choose the level of abstraction- behavioral, dataflow
or structural. Second we can choose whether to use concurrent or sequential assignment statement if we
choose behavioral modelling. Furthermore we can have the ports declared as individual pin or a vector.
In this tutorial we use behavioral modelling and use concurrent and sequential statement to design the
encoder. Also individual pins are used instead of vectored inputs and outputs.
The truth table of a octal to binary encoder is below,

One way to model the octal to binary encoder is to choose individual pins for input and output as shown
below,

This encoder can be implemented using the when-else concurrent signal assignment as follows,
library ieee;
use ieee.std_logic_1164.all;
entity encoder8x3 is
port(
x0,x1,x2,x3,x4,x5,x6,x7 : in std_logic;
y0,y1,y2 : out std_logic
);
end encoder8x3;
architecture when_else of encoder8x3 is
signal y : std_logic_vector(2 downto 0);
begin
y <= "000" when x0&x1&x2&x3&x4&x5&x6&x7 = "10000000" else
"001" when x0&x1&x2&x3&x4&x5&x6&x7 = "01000000" else
"010" when x0&x1&x2&x3&x4&x5&x6&x7 = "00100000" else
"011" when x0&x1&x2&x3&x4&x5&x6&x7 = "00010000" else
"100" when x0&x1&x2&x3&x4&x5&x6&x7 = "00001000" else
"101" when x0&x1&x2&x3&x4&x5&x6&x7 = "00000100" else
"110" when x0&x1&x2&x3&x4&x5&x6&x7 = "00000010" else
"111" when x0&x1&x2&x3&x4&x5&x6&x7 = "00000001" else
"ZZZ";

y0 <= y(0);
y1 <= y(1);
y2 <= y(2);
end when_else;
end when_else;
A vhdl software can be used to simulate the above code and view the simulated waveform. The simulated
waveform is shown below,

Next, the vhdl code for the octal to binary encoder using with-select-when concurrent statement is as
follows:
architecture with_select_when of encoder8x3 is
signal y : std_logic_vector(2 downto 0);
signal x : std_logic_vector(7 downto 0);
begin
x <= x0&x1&x2&x3&x4&x5&x6&x7;
with x select
y <= "000" when "10000000",
"001" when "01000000",
"010" when "00100000",
"011" when "00010000",

"100" when "00001000",

"101" when "00000100",
"110" when "00000010",
"111" when "00000001",
"ZZZ" when others;
y0 <= y(0);
y1 <= y(1);
y2 <= y(2);
end with_select_when;
The simulated waveform for this code using VHDL software is shown below,

Now it is shown how a octal to binary encoder using if sequential assignment can be used to model the
encoder. The following is the vhdl code:
architecture if_elsif_then of encoder8x3 is
signal y : std_logic_vector(2 downto 0);
begin
process(x0,x1,x2,x3,x4,x5,x6,x7)
begin
if (x0&x1&x2&x3&x4&x5&x6&x7 = "10000000") then y <= "000";
elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "01000000") then y <= "001";
elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "00100000") then y <= "010";
elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "00010000") then y <= "011";
elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "00001000") then y <= "100";

elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "00000100") then y <= "101";

elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "00000010") then y <= "110";
elsif (x0&x1&x2&x3&x4&x5&x6&x7 = "00000001") then y <= "111";
else y <= "ZZZ";
end if;
end process;
y0 <= y(0);
y1 <= y(1);
y2 <= y(2);
end if_elsif_then;
The following shows the simulated waveform in VHDL software:

This vhdl tutorial showed how one can model a octal to binary encoder in vhdl using concurrent and
sequential assignment statements an simulated the code with VHDL software aldec.

Posted: 15 Feb 2015 09:37 PM PST

In this article it is shown how a decoder design in vhdl using concurrent and sequential statements and
simulated with VHDL software. A decoder can be described in VHDL using 3 different model abstractionbehavioral, dataflow and structural. In behavioral modelling we can used concurrent or sequential
statements to describe a decoder.
The decoder that will be designed is a 2 to 4 decoder with 2 inputs and 4 outputs. Conditional concurrent
statement includes when-else, with-select-when statements and conditional sequential statements
includes if and case statements.

Furthermore, in vhdl the port can be made as individual ports and as bit vectors.
The following shows the first kind of decoder which has individual pins/port as input and bit vector as
output.

This kind of decoder has VHDL code with when-else statement as follows,
library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;
y: out std_logic_vector(3 downto 0)
);
end decoder2x4;
architecture when_else of decoder2x4 is
begin
y <= "1000" when a&b = "00" else
"0100" when a&b = "01" else
"0010" when a&b = "10" else
"0001";
end when_else;
The digital waveform obtained from VHDL software is as follows,

The 2 to 4 decoder in vhdl using concurrent with-select-when assignment is below,

library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;
y: out std_logic_vector(3 downto 0)
);
end decoder2x4;
architecture with_select_when of decoder2x4 is
signal sel : std_logic_vector(1 downto 0);
begin
sel <= a&b;
with sel select
y <= "1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when others;
end with_select_when;
The simulated waveform using VHDL software is as follows,

Next, the 2 to 4 decoder using sequential assignment statement if-elsif-then is as followslibrary ieee;
use ieee.std_logic_1164.all;

entity decoder2x4 is
port(
a,b: in std_logic;
y: out std_logic_vector(3 downto 0)
);
end decoder2x4;
architecture if_elsif_else of decoder2x4 is
begin
process(a,b)
begin
if (a&b="00") then y <= "1000";
elsif (a&b="01") then y <= "1000";
elsif (a&b="10") then y <= "1000";
else y <= "0001";
end if;
end process;
end if_elsif_else;
The simulated waveform using VHDL software is as follows,

The vhdl code for 2 to 4 decoder using sequential assignment case-when is as follows,
library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;
y: out std_logic_vector(3 downto 0)
);
end decoder2x4;
architecture case_when of decoder2x4 is
begin

process(a,b)
begin
case a&b is
when "00" => y <= "1000";
when "01" => y <= "0100";
when "10" => y <= "0010";
when "11" => y <= "0001";
end case;
end process;
end case_when;
The VHDL software simulated output waveform for this code is as follows,

The following figure illustrates a second kind of 2-to-4 decoder with individual ports/pins for inputs and
outputs.

The decoder vhdl code for this type of ports is provided below with concurrent and sequential assignment.
The following is a vhdl code for 2 to 4 decoder using when-else statement.
library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is

port(
a,b: in std_logic;
y0,y1,y2,y3: out std_logic
);
end decoder2x4;
architecture when_else of decoder2x4 is
signal y : std_logic_vector(3 downto 0);
begin
y <= "1000" when a&b = "00" else
"0100" when a&b = "01" else
"0010" when a&b = "10" else
"0001";
y3 <= y(3);
y2 <= y(2);
y1 <= y(1);
y0 <= y(0);
end when_else;
The VHDL software output of the waveform is shown below,

The vhdl code for 2 to 4 decoder using with-when concurrent statement is as follows,
library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;

y0,y1,y2,y3: out std_logic

);
end decoder2x4;
architecture with_select_when of decoder2x4 is
signal sel : std_logic_vector(1 downto 0);
signal y : std_logic_vector(3 downto 0);
begin
sel <= a&b;
with sel select
y <= "1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when others;
y3 <= y(3);
y2 <= y(2);
y1 <= y(1);
y0 <= y(0);
end with_select_when;
The following is the simulated waveform using vhdl software,

Now we show how the sequential assignment in vhdl can be used to model the 2 to 4 decoder.
Using if statement, the vhdl code is as follows,
architecture if_elsif_else of decoder2x4 is
signal ytemp : std_logic_vector(3 downto 0);
begin

process(a,b)
begin
if (a&b="00") then ytemp <= "1000";
elsif (a&b="00") then ytemp <= "1000";
elsif (a&b="00") then ytemp <= "1000";
else ytemp <= "0001";
end if;
end process;
y0 <= ytemp(0);
y1 <= ytemp(1);
y2 <= ytemp(2);
y3 <= ytemp(3);
end if_elsif_else;
The simulated waveform is shown below,

Another sequential statement is case-when and the decoder design using this sequential assignment is
below,

architecture case_when of decoder2x4 is

signal ytemp : std_logic_vector(3 downto 0);
begin
process(a,b)
begin
case a&b is
when "00" => ytemp <= "1000";
when "01" => ytemp <= "0100";
when "10" => ytemp <= "0010";

when "11" => ytemp <= "0001";

end case;
end process;
y0 <= ytemp(0);
y1 <= ytemp(1);
y2 <= ytemp(2);
y3 <= ytemp(3);
end case_when;
The simulated waveform is shown below.

An actual decoders have enable input which when is asserted the output becomes available otherwise not.
The following shows the same decoder with enable input.

This decoder with enable can also be modelled using concurrent and sequential statements as follows.
Using when-else statement,
library ieee;

use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;
y0,y1,y2,y3: out std_logic;
en : in std_logic
);
end decoder2x4;
architecture when_else of decoder2x4 is
signal y : std_logic_vector(3 downto 0);
begin
y <= "1000" when a&b&en = "001" else
"0100" when a&b&en = "011" else
"0010" when a&b&en = "101" else
"0001" when a&b&en = "111" else
"0000";
y3 <= y(3);
y2 <= y(2);
y1 <= y(1);
y0 <= y(0);
end when_else;
The simulation waveform obtained from vhdl software is shown below,

Using with-select-when concurrent statement,

library ieee;

use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;
y0,y1,y2,y3: out std_logic;
en : in std_logic
);
end decoder2x4;
architecture with_select_when of decoder2x4 is
signal sel : std_logic_vector(2 downto 0);
signal y : std_logic_vector(3 downto 0);
begin
sel <= a&b&en;
with sel select
y <= "1000" when "001",
"0100" when "011",
"0010" when "101",
"0001" when "111",
"0000" when others;
y3 <= y(3);
y2 <= y(2);
y1 <= y(1);
y0 <= y(0);
end with_select_when;
The simulated waveform is shown below,

Using if sequential statements,

library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;
y0,y1,y2,y3: out std_logic;
en : in std_logic
);
end decoder2x4;
architecture if_elsif_else of decoder2x4 is
signal ytemp : std_logic_vector(3 downto 0);
begin
process(a,b,en)
begin
if (en = '1') then
if (a&b="00") then ytemp <= "1000";
elsif (a&b="01") then ytemp <= "0100";
elsif (a&b="10") then ytemp <= "0010";
else ytemp <= "0001";
end if;
else
ytemp <= "0000";
end if;
end process;
y0 <= ytemp(0);
y1 <= ytemp(1);
y2 <= ytemp(2);
y3 <= ytemp(3);
end if_elsif_else;
The simulated waveform is shown below,

And using case sequential statement,

library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is
port(
a,b: in std_logic;
y0,y1,y2,y3: out std_logic;
en : in std_logic
);
end decoder2x4;
architecture case_when of decoder2x4 is
signal ytemp : std_logic_vector(3 downto 0);
begin
process(a,b)
begin
case a&b&en is
when "001" => ytemp <= "1000";
when "011" => ytemp <= "0100";
when "101" => ytemp <= "0010";
when "111" => ytemp <= "0001";
when others => ytemp <= "0000";
end case;
end process;
y0 <= ytemp(0);
y1 <= ytemp(1);
y2 <= ytemp(2);
y3 <= ytemp(3);

end case_when;

This article explained how a decoder can be designed in vhdl using concurrent and sequential statement.

For more tutorials visit: http://appliedelectronicsengineering.blogspot.com