Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

FPGA-based Switched Reluctance Motor Drive and DC-DC Converter

Models for High-Bandwidth HIL Real-Time Simulator
Christian Dufour, Sbastien Cense, Jean Blanger
OPAL-RT Technologies Inc.
1751 Richardson, bureau 2525
Montral, Qubec, Canada, H3K 1G6
{christian.dufour, sebastien.cense, jean.belanger}@opal-rt.com

Keywords
Switched-Reluctance Motor, SRM, DC-DC converter, Buck converter, Boost converter, FPGA, Real-time
simulation, HIL simulation.

Abstract
In this paper, we describe an FPGA implementation of a Switched Reluctance Motor Drive (SRM) and an H-bridge
Buck-Boost converter targeted for Hardware-In-the Loop (HIL) testing of modern SRM controllers. These FPGA
models allow the HIL simulation of SRM drive and boost converter with switching frequencies in the 50-100 kHz
range because of the very high sampling rate of the FPGA. The models are also integrated into the RT-LAB realtime environment and directly linked with the simulator I/Os, providing ultra-low HIL gate-in-to-current-out
latency, suitable for testing modern motor controllers.

Introduction
As of 2012, its a very common industrial practice to validate motor drive control with Hardware-In-the-Loop
(HIL) simulation[1][2]. The advantages of this are numerous: for example, the real-time simulated motor drive can
be tested with borderline conditions that would damage a real motor prototype. With ever decreasing time-tomarket, HIL simulation enables engineers to design the motor and power electronic controls in parallel to the motor
drive and power converter themselves. Hybrid electric vehicle (HEV) OEMs and other motor drive manufacturers
use HIL technology to speed up development time by allowing early error detection before conducting tests on
physical prototypes. At the production stage, HIL simulation can also be used to verify code integrity at controller
software releases with automated correlation tests.
In the field of HEV, permanent magnet synchronous motors (PMSM) are the preferred choice of many
manufacturers, mainly for efficiency reasons. Recently, the interest in switched reluctance motor drive has
increased greatly because the high cost of rare-earth metals used in PMSM. SRM drives also benefit from its low
manufacturing costs, rugged construction and simplicity of controller design. Since the rotor has no windings and
no magnets, it is a good candidate for drive operation at high speed and in adverse environments. As with the
PMSM, a real-time simulator is the ideal tool to conduct research on this relatively new application of the SRM.
Sensorless drive designs and control optimisations, for example, pose challenges that can be tackled efficiently
with a real-time simulator.
Advances in power electronics have made possible the design of very high switching frequency motor drive and
power converters. The SRM drive, with its high speed capability, can require switching frequencies reaching 20
kHz. Modern HEV topologies with voltage boosting stage goes further with DC-DC converters with PWM
frequencies up to 100 kHz.
The HIL testing of such devices therefore requires a real-time simulator with a very high sampling rate, preferably
below 500 nanoseconds in stringent applications, to obtain reasonable accuracy at 100 kHz. FPGA-based SRM
drive and DC-DC converters are an excellent solution to this challenge. In this paper, we detail such a model
implemented on a Virtex-6 FPGA chip within the RT-LAB real-time system.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

Fig. 1. FPGA-based SRM Drive HIL simulator with DC-DC converter

Switched Reluctance Motor drive HIL simulator model components

The FPGA implementation SRM Drive HIL test system in the RT-LAB real-time simulator is depicted in Fig. 1. It
has 6 main components:
SRM motor: currently supported model is the 6/4, 10/8 and 12/10 configurations. 6/4 means a SRM with 6 poles on
the stator and 4 poles on the rotor. It also supports multiple of these (ex: 12/8) with stator phases connected in
parallel.
SRM inverter: an IGBT inverter with 2 IGBTs (with anti-parallel diode) and 2 Diodes per SRM phase. (With the
SRM, each phase has 2 terminals)
H-bridge Buck-Boost converter: an H-bridge with 4 IGBTs (with anti-parallel diode) to boost the battery voltage
before the SRM inverter.
Internal test modulators: to enable stand-alone testing of the different FPGA modules without an external controller
connected to the simulator. The SRM drive modulator is a current-control hysteretic controller while the DC-DC
converter modulator is of PWM type. These modulators are unused when the simulator is running with a controller
connected to the I/Os.
I/O modules: enable the user to connect the simulator to the external control system under test so the control system
under test sends and receives sensor signals at the same speed as in real life.
CPU model interface: allows the user to interface other model subsystems simulated on the CPU to the FPGA
model subsystems. In a complex HEV system, for example, the mechanical equation would be computed on the
CPU from the different model torque contributions: SRM electric torque, ICE torque, transmission, road friction,
etc
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

Model Latencies
Of special importance are the latencies of the different modules. From the controller point of view, the latency from
the gate sampling at the digital input of the simulator to the output of the current at the analog output (SRM or DCDC drive) must be minimal, under 1 s in some applications. Also, the model sampling frequencies should be at
100 times higher than the PWM frequency in use (i.e. for 1 % precision).
ML605 Virtex-6 FPGA boards are used in the current implementation of these models with a 200 MHz clock. On
the RT-LAB simulator, these FPGA boards are directly connected to 16 fast D/A converters with a simultaneous
conversion rate of 1 s.
Table 1: SRM drive and buck-boost converter sampling rate and latencies
Module
Sampling rate/Latency (ns) (not including D/A)
SRM inverter
30/{25-50} ns (gate-to-Vabc)
30/{60-105} (gate-to-Idc)
SRM motor (6/4)
120/{210-300}ns (Vabc-to-Iabc)
H-bridge Buck-Boost converter
120/{85-200} ns (gate-to-Vcapa/Iind)

Table 1 details the various model subsystems sampling rates and latencies. These two are not equal. The sampling
rate is the rate at which each block samples its inputs. Latency is the delay between the input sampling and the
resulting change of the block outputs. The subsystems latency is also variable in the range {minimum, maximum}
in the table, mainly because of the pipelining methods used in coding coupled with the asynchronicity of the gate
inputs (for the inverter and converter).
As it can be seen, the total latency for the controller firing output signal to the motor current output is 235 ns to
350 ns without taking account of the analog output converter conversion delays and the time response of the current
sensors that could also be simulated in the FPGA. The D/A converters installed on the simulator have a conversion
rate of 1 s.

Models configurability
From the industrial users point of view, its important that the models offer some flexibility, especially in terms of
parameterization. However, todays FPGA technology still suffers from a very long compilation time (i.e. Place
and route, and bitstream generation) that can easily take 1 or 2 hours for a large FPGA like the Virtex-6. This
compilation time would result in very long and often unacceptable iteration times for any test engineer.
The models presented in this paper avoid this problem by allowing all their parameters to be loadable as signals to a
fixed bitstream. This way, changes of SRM motor parameters (Stator resistance, SRM flux and torque tables,
number of poles, etc) and Buck-Boost converter (Resistance, capacitance and inductance), can be done easily onthe-fly, without regenerating new bitstreams.
This is an important feature to increase user interactivity with the simulator. This flexibility is increased even more
with the eHS generic FPGA solver [8] and allows users to modify the circuit topology or even create new
converter topologies without generating a new bitstream. This is a great advantage for projects in which the filter
and converter topology must be optimized.

Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

Switched Reluctance Motor modeling

This SRM model integrates its flux at each winding, considered as uncoupled in this model[3][4][5]. The model
working equation is:

(V

abc

Rs I abc ) dt abc

(1)

where Iabc is the stator current inside the winding, Rs is the stator resistance and Vabc is the voltage across the
stator windings. The current is then derived from the machine flux characteristics and stored in tables on the FPGA.

Fig. 2. Left: Three-dimensional relationship between excitation current, rotor position and flux linkages
for 12/8 SRM motor Right: FEA analysis on the 12/8 SRM in MotorSolve.
In the SRM, there is a three-dimensional relationship between excitation current, rotor position and flux linkages.
This flux relationship can be found using commercial FEA software like JSOLs JMAG-Studio[9] or Infolyticas
MotorSolve[10]. Fig. 2 shows this flux relationship and the corresponding FEA analysis using MotorSolve for the
12/8 SRM used for example in this paper.
From this ( I , ) flux relationship, the OPAL-RT model derives the inverse characteristic I ( , ) , using spline
methods[6][7]. This inverted characteristic is shown in Fig. 3. Note the electric angle scale from 0 to 90 in the
figures because a 12/8 SRM is electrically equivalent to a 6/4 SRM.

Fig. 3. Inverse current characteristic (left) and torque characteristic (right).

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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

The produced electrical torque is also derived from the flux-current characteristic, pre-computed and stored in
tables prior to the real-time simulation. The torque is computed by integration and derivation of the machine coenergy Wc using Eq. (2). For the same motor again, Fig. 3 shows the torque characteristic obtained.

Te ( I , )

Wc ( I , )

Wc ( I , )dI

(2)

The SRM motor model uses Time-Domain-Multiplexing (TDM) in the solver design using single precision
floating-point arithmetic. TDM pipelines the equations of the motor (integration, addition, etc) into a serial
sequence of arithmetic operators and results in very low sampling times. Pipelining, however, induces a latency
that is greater than the sampling time.

H-bridge Buck-Boost converter modeling

The DC-DC converter was designed with single precision floating point arithmetic with state-space approach with
2 states (inductance current and capacitor voltage) with pre-calculation of the 16 combinations of the 4 IGBTs
conduction states.
The model consequently supports all normal and faulty operation modes. Also, with the state-space approach, the
model latency is equal to its sample time of 120 ns. This sample time also determines the resolution of the IGBT
gate at the simulator I/Os. With a 120 ns sampling time, for example, the DC-DC converter precision with regards
to gate sampling is 1.2%, assuming the converter runs at 100 kHz.

SRM inverter modeling

The SRM inverter was designed using a switching-function approach with high impedance capability that occurs
when the inverter gates are turned off [1]. The main reason for this choice was to minimize the model sampling
time and time resolution. The model was implemented using the Time-Domain-Multiplexing (TDM) method in the
solver design with the same benefits and limitations that are found in the SRM motor design. It is made with single
precision floating point arithmetic.

Model validations and tests

The FPGA SRM motor drive and DC-DC converter models were developed with SimPowerSystems v5.5
(MATLAB R2011B) as a reference. Static and dynamic tests were performed and showed an excellent match. This
paper shows only the dynamic tests.
The tests were conducted on the HIL system with the internal test modulator and the waveforms were captured at
the simulator analog outputs by an oscilloscope. We compared these results with the ones obtained offline in
SimPowerSystems.

H-bridge Buck-Boost converter model validation

The dynamic response of the FPGA DC-DC converter was tested on-chip and compared with offline simulation
using SimPowerSystems. The on-chip waveforms were captured with an oscilloscope and are shown in Fig. 4
together with the SPS results. All parameters are shown in the figure. The test consisted in charging the load
current from -10A to +40A (with load current defined as going out of the converter). A PWM frequency of 50 kHz
a duty cycle of 20% and a dead-time of 1 s were used. Initial current of ~ -60A final current of ~160A were
found in both on-chip and offline simulations. Capacitor voltage also saturated correctly to 0 V in both case.
Oscillation frequency and damping also matched.
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Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

Fig. 4. DC-DC converter load step. FPGA on-chip results (left) vs. SPS offline simulation (right)

SRM Drive model validation

The SRM drive was also implemented on the ML-605 FPGA chip. The tested SRM motor parameters are described
in the previous sections. The SRM windings have a resistance of 0.63 Ohms. For the purpose of the test, we ran
this 12/8 SRM motor at 2500 RPM. The DC link voltage was set to 300 volts and the FPGA internal current
controller was used with current command stepping from 5 to 10 A and turn on turn off angles of 20 and 43.5
respectively. Again, the model results were captured with an oscilloscope and compared with offline simulation in
Fig. 5. The general behavior of the models is similar: similar band gaps of currents, same current overlap near 0
Amp, switching frequency that decreases after a phase is turned-on as the inductance increases due to the alignment
of rotor and stator poles. Torque also matches but is not shown here.

Fig. 5. SRM Drive current command step: FPGA results (left) vs. SPS offline simulation (right)

Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

HIL latency measurements

In this section, we provide an experimental measurement of the SRM drive latency measured on the OP5600 realtime simulator I/Os. Two measurements were made: the first was the latency from the Digital input, driving the
IGBT on the SRM converter, to the SRM voltage input (Fig. 6, left) while the 2nd one was from the same digital
input to the SRM current (Fig. 6, right). Both SRM terminal voltage and currents are outputted to the simulator
Analog Output and read on an oscilloscope. The oscilloscope time range is 500 nanoseconds per division.

Fig. 6. SRM drive latency: from Digital Input to SRM voltage input ( left) and SRM current (right)

The key aspect of this HIL latency measurement is the non-synchronicity of the Analog Output converter, running
at 1 s rate, and the digital inputs of the drive. This results in a dispersion of the latency of about 1 s, easily
observable on the voltage latency measurement but also present on the current one. The latency of the SRM drive
model on FPGA is consequently equal to 1.75s 0.5 s from Digital Input to Voltage Output and 2s 0.5 s
from Digital Input to motor winding current. The latter measurement is more important because it can influence the
hysteretic current control of the SRM drive. The use of a faster digital to analog converter with a 100 or 200
nanosecond conversion time would decrease the total latency to values closer to the model calculation time of
about 350 ns.

Conclusion
This paper presented an ultra-low latency HIL model and SRM drive and DC-DC boost converter, designed on an
FPGA chip. The paper explained the various feature of the models along with validation tests. The tests confirmed
that the models are accurate in steady-state and dynamic response. The latency of the SRM drive, from the digital
inputs to the motor currents at the analog outputs was measured to be equal to 2s 0.5 s. Such a low latency, the
lowest ever reported for an SRM HIL system, can help to achieve high accuracy simulation with an real hysteretic
controller in the loop.
One key aspect of the presented models is that they do not require the user to regenerate a bitstream if some
parameters change, including the SRM flux-current FEA data or boost converter RLC values for example. This is
important for the industrial usability of the models because bitstream generation of such complex model can take
hours to complete. We are currently waiting to obtain HIL results with the client controllers connected to the realtime simulator.

Paper presented at the EPE'13 ECCE Europe conference, September 3-5, 2013, Lille, France

References
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Iannelli (Eds.), Springer, 2012. ISBN 978-1-4471-2885-4
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Models with Variable-DQ and Spatial Harmonic Finite-Element Analysis Solvers, 15th Int. Power Electronics and
Motion Control Conference, EPE-PEMC 2012, Novi Sad, Serbia, Sept. 4-6, 2012
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