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Chapter 1
PREAMBLE
1.1 Introduction:
The MCB1700 evaluation board allows us to generate and test application programs for
the NXP LPC1768 device family. With this hands-on process, we can determine the
hardware and software requirements for current and future product development. The
LPC1768 is a Cortex-M3 microcontroller for embedded applications featuring a high
level of integration and low power consumption at frequencies of 100 MHz. Features
include 512 KB of flash memory, 64 KB of data memory, Ethernet MAC, USB
Device/Host/OTG, 8-channel DMA controller, 4 UARTs, 2 CAN channels, 3 SSP/SPI, 3
I2C, I2S, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder
interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power
Real-Time Clock with separate battery supply, and up to 70 general purpose I/O pins. The
LPC1768 is pin-compatible to the 100-pin LPC2368 ARM7 MCU.

1.2 Problem definition:

As we all know, there are some of the readily available boards in the market. The problem
with these boards are that, some of the boards may not have the peripherals which are in
need to some users. Every developer need some development board to develop and test
their application before they actually design and manufacture the custom board. This
development board should be low cost and should have all the peripherals to test on it.
Some developers work on ethernet some on CAN and some USB and so on, in order
meet developer requirement a general purpose development board is highly in need at
embedded world.

1.3 Solution:
Every developer needs some development board to develop and test their application
before they actually design and manufacture the custom board. This development board
should be of low cost and should have all the peripherals to test on it. Hence it can also be
called as a general purpose development board. So our project is to design a general
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purpose development board which is of low cost and includes many peripherals in it, the
board MCB1700 allows us to programming different ports for different purposes.

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Chapter 2
THE ARM CORTEX- M3 PROCESSOR
2.1 History
System-on-chip solutions based on ARM embedded processors address many different
market segments including enterprise applications, automotive systems, home networking
and wireless technologies. The ARM Cortex family of processors provides a standard
architecture to address the broad performance spectrum required by these diverse
technologies. The ARM Cortex family includes processors based on the three distinct
profiles of the ARMv7 architecture; the A profile for sophisticated, high-end applications
running open and complex operating systems; the R profile for real-time systems; and the
M profile optimized for cost-sensitive and microcontroller applications. The Cortex-M3
processor is the first ARM processor based on the ARMv7-M architecture and has been
specifically designed to achieve high system performance in power- and cost-sensitive
embedded applications, such as microcontrollers, automotive body systems, industrial
control systems and wireless networking, while significantly simplifying programmability
to make the ARM architecture an option for even the simplest applications.
2.1.1 Higher performance through better efficiency
In order to achieve higher performance, processors can either work hard or work smart.
Pushing higher clock frequencies may increase performance but is also accompanied by
higher power consumption and design complexity. On the other hand, higher compute
efficiency at slower clock speeds results in simpler and lower power designs that can
perform the same tasks. At the heart of the Cortex-M3 processor is an advanced 3-stage
pipeline core, based on the Harvard architecture, that incorporates many new powerful
features such as branch speculation, single cycle multiply and hardware divide to deliver
an exceptional Dhrystone benchmark performance of 1.25 DMIPS/MHz. The Cortex-M3
processor also implements the new Thumb-2 instruction set architecture, helping it to be
70% more efficient per MHz than an ARM7TDMI-S processor executing Thumb
instructions, and 35% more efficient than the ARM7TDMI-S processor executing ARM
instructions, for the Dhrystone benchmark.
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2.1.2 Ease of use for quick and efficient application development

Reducing time-to-market and lowering development costs are critical criteria in the
choice of microcontrollers, and the ability to quickly and easily develop software is key to
these requirements. The Cortex-M3 processor has been designed to be fast and easy to
program, with the users not required to write any assembler code or have deep knowledge
of the architecture to create simple applications. The processor has a simplified stackbased programmers model which still maintains compatibility with the traditional ARM
architecture but is analogous to the systems employed by legacy 8- and 16-bit
architectures, making the transition to 32-bit easier. Additionally a hardware-based
interrupt scheme means that writing interrupt service routines (handlers) becomes trivial,
and that start-up code is now significantly simplified as no assembler code register
manipulation is required. Key new features in the underlying Thumb-2 Instruction Set
Architecture (ISA) implement C code more naturally, with native bitfield manipulation,
hardware division and If/Then instructions.
Further, from a development perspective, Thumb-2 instructions speed up development
and simplify long term maintenance and support of compiled objects through automatic
optimization for both performance and code density, without the need for complex
interworking between code compiled for ARM or Thumb modes. The effect of this is that
users can maintain their code in C and not have to create libraries of pre-compiled object
code, allowing for far greater code reuse.
2.1.3 Reduced costs and lower power for sensitive markets
A constant barrier to the adoption of higher performance microcontrollers has always
been cost. Advanced manufacturing technologies are expensive and therefore smaller
silicon area requirements can reduce costs significantly. The Cortex-M3 processor
reduces system area by implementing the smallest ARM core to date, with just 33,000
gates in the central core (0.18um G) and by efficiently incorporating tightly coupled
system components in the processor. Memory requirements are minimized by
implementing unaligned data storage, atomic bit manipulation and the Thumb-2
instruction set that reduces instruction memory requirements for the Dhrystone
benchmark by more than 25% compared to ARM instructions. In order to address the
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increasing need for energy conservation in markets like white goods and wireless
networking, the Cortex-M3 processor supports extensive clock gating and integrated
sleep modes. Enabled by these features, the processor delivers a power consumption of
just 4.5mW and a silicon footprint of 0.30mm2 when implemented at a target frequency
of 50MHz on the TSMC 0.13G process using ARM Metro standard cells.
2.1.4 Migration from the ARM7 processor family for better performance and power
efficiency
Over the last decade, the ARM7 family of processors has been widely adopted for many
applications. The Cortex-M3 processor builds on this success to present the logical
migration path for ARM7 processor-based systems.

Figure 2.1. Relative performance for ARM7TDMI-S (ARM) and Cortex-M3 (Thumb-2)

The central core offers higher efficiency, a simpler programming model and excellent
deterministic interrupt behaviour, while the integrated peripherals offer enhanced
performance at low cost. Table 1 shows the comparison of ARM over the Cortex- M3
processor.

Figure2.2 Relative code size for ARM7TDMI-S (ARM) and Cortex-M3 (Thumb-2)
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Table2.1. ARM7TDMI-S and Cortex-M3 comparison (100MHz frequency on TSMC 0.18G)

2.2 Cortex-M3 processor architecture and features

2.2.1 Cortex-M3 core
The Cortex-M3 processor, based on the ARMv7-M architecture, has a hierarchical
structure. It integrates the central processor core, called the CM3Core, with advanced
system peripherals to enable integrated capabilities like interrupt control, memory
protection and system debug and trace. These peripherals are highly configurable to allow
the Cortex-M3 processor to address a wide range of applications and be more closely
aligned with the system requirements. The Cortex-M3 core and the integrated
components (Figure 3) have been specifically designed to meet the requirements of
minimal memory implementation, reduced pin count and low power consumption. The
core pipeline has 3 stages: Instruction Fetch, Instruction Decode and Instruction Execute.
When a branch instruction is encountered, the decode stage also includes a speculative
instruction fetch that could lead to faster execution.
The processor fetches the branch destination instruction during the decode stage itself.
Later, during the execute stage, the branch is resolved and it is known which instruction is
to be executed next. If the branch is not to be taken, the next sequential instruction is
already available. If the branch is to be taken, the branch instruction is made available at
the same time as the decision is made, restricting idle time to just one cycle. The CortexM3 core contains a decoder for traditional Thumb and new Thumb-2 instructions, an
advanced ALU with support for hardware multiply and divide, control logic, and
interfaces to the other components of the processor.
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Figure 2.3. The Cortex-M3 processor

The Cortex-M3 processor supports two operating modes, Thread and Handler and two
levels of access for the code, privileged and unprivileged, enabling the implementation of
complex and open systems without sacrificing the security of the application.
Unprivileged code execution limits or excludes access to some resources like certain
instructions and specific memory locations. The Thread mode is the typical operating
mode and supports both privileged and unprivileged code. The Handler mode is entered
when an exception occurs and all code is privileged during this mode. In addition, all
operation is categorized under two operating states, Thumb for normal execution and
Debug for debug activities. The Cortex-M3 processor is a memory mapped system with a
simple, fixed memory map for up to 4 gigabytes of addressable memory space with
predefined, dedicated addresses for code (code space), SRAM(memory space), external
memories/devices and internal/external peripherals. There is also a special region to
provide for vendor specific addressability.
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Figure 2.4 The Memory Map

The Cortex-M3 processor enables direct access to single bits of data in simple systems by
implementing a technique called bit-banding (Figure 5). The memory map includes two
1MB bit-band regions in the SRAM and peripheral space that map on to 32MB of alias
regions. Load/store operations on an address in the alias region directly get translated to
an operation on the bit aliased by that address. Writing to an address in the alias region
with the least-significant bit set writes a 1 to the bit-band bit and writing with the leastsignificant bit cleared writes a 0 to the bit. Reading the aliased address directly returns the
value in the appropriate bit-band bit. Additionally, this operation is atomic and cannot be
interrupted by other bus activities.
Traditional ARM7 processor-based systems support only aligned data access, allowing
data to be stored and accessed only along aligned word boundaries. The Cortex-M3
processor implements unaligned data access that enables unaligned data transfers in a
single core access. When unaligned transfers are used, they are converted into multiple
aligned transfers and remain transparent to application programmers. In addition the
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Cortex-M3 processor supports 32-bit multiply operations in a single cycle and also
supports signed and unsigned divide operations with the SDIV and UDIV instructions
that take between 2 and 12 cycles depending upon the size of the operands. The division
operation is completed faster if the dividend and the divisor are closer in size. These
improvements in the mathematical capabilities make the Cortex-M3 processor ideal for
many numerically intensive applications such as sensor reading and scaling or hardwarein-the-loop simulation systems.

Figure 2.5. Comparison of traditional bit manipulation with Cortex-M3 bit banding

2.2.2 Thumb-2 Instruction Set Architecture:

The ARMv7-M is the microcontroller profile of the ARMV7 architecture and is different
from earlier ARM architectures in that it supports Thumb-2 instructions alone. Thumb-2
technology is a blend of 16 and 32-bit instructions that delivers the performance of 32-bit
ARM instructions, matches the code density of and is backwards compatible with, the
original 16-bit Thumb instruction set. Figure 6 shows indicative Dhrystone benchmark
results that illustrate that Thumb-2 technology indeed achieves this objective. In an
ARM7 processor-based system, switching the processor core between the Thumb state for
code density and ARM state for high performance would be necessary for certain
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applications. However, the Cortex-M3 processor does not need to interwork instructions
since both 16-bit and 32-bit instructions co-exist in the same mode, enabling higher code
density and performance with far less complexity.

Figure 2.6. Relative Dhrystone performance and code size for ARM, Thumb and Thumb2.
As the Thumb-2 instructions are a superset of 16-bit Thumb instructions, the Cortex-M3
processor can execute any previously written Thumb code. By implementing Thumb-2
instructions, the Cortex-M3 processor also delivers compatibility with other members of
the ARM Cortex processor family. The Thumb-2 instruction set includes instructions that
make it easier to write compact code for many different applications. The BFI and BFC
instructions are bit-field instructions that are useful in applications like network packet
processing. The SBFX and UBFX instructions improve the ability to insert or extract a
number of bits to or from a register, a capability particularly useful in automotive
applications. The RBIT instruction reverses the bits in a word and is useful in DSP
algorithms such as DFT. The table branch instructions TBB and TBH enable a balance of
code compaction and high performance. Thumb-2 instructions also introduce a new IfThen construct that predicates the conditional execution of up to four subsequent
instructions.
2.2.3 The Nested Vectored Interrupt Controller (NVIC)
The highly configurable NVIC is an integral part of the Cortex-M3 processor and
provides the processors outstanding interrupt handling abilities. In its standard
implementation it supplies a Non-Maskable Interrupt (NMI) and 32 general purpose
physical interrupts with 8 levels of pre-emption priority. It can be configured to anywhere
between 1 and 240 physical interrupts with up to 256 levels of priority though simple
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synthesis choices. The Cortex-M3 processor uses a re-locatable vector table that contains
the address of the function to be executed for a particular interrupt handler. On accepting
an interrupt, the processor fetches the address from the vector table through the
instruction bus interface. The vector table is located at address zero at reset, but can be
relocated by programming a control register. To reduce gate count and enhance system
flexibility the Cortex-M3 has migrated from the banked shadow register exception model
of the ARM7 processor to a stack based exception model. When an exception takes place,
the Program Counter, Program Status Register, Link Register and the R0-R3,R12 general
purpose registers are pushed on to the stack. The data bus stacks the registers whilst the
instruction bus identifies the exception vector from the vector table and fetches the first
instruction of the exception code.
Once the stacking and instruction fetch are completed, the interrupt service routine or
fault handler is executed, followed by the automatic restoration of the registers to enable
the interrupted program to resume normal execution. By handling the stack operations in
hardware, the Cortex-M3 processor removes the need to write assembler wrappers that
are required to perform stack manipulation for traditional C-based interrupt service
routines, making application development significantly easier. The NVIC supports
nesting (stacking) of interrupts, allowing an interrupt to be serviced earlier by exerting
higher priority. It also supports dynamic reprioritisation of interrupts. Priority levels can
be changed by software during run time. Interrupts that are being serviced are blocked
from further activation until the interrupt service routine is completed, so their priority
can be changed without risk of accidental re entry.
2.2.4 The Memory Protection Unit (MPU)
The MPU is an optional component of the Cortex-M3 processor that can improve the
reliability of an embedded system by protecting critical data used by the operating system
from user applications, separating processing tasks by disallowing access to each other's
data, disabling access to memory regions, allowing memory regions to be defined as readonly and detecting unexpected memory accesses that could potentially break the system.
The MPU enables the application to be broken down into a set of processes. Each process
owns specific memory (code, data, stack, and heap) and devices, as well as having access
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to shared memory and devices. The MPU also enforces user and privilege access rules.
This includes executing code from the right privilege level as well as enforcing ownership
of memory and devices by privileged and user code. The MPU separates the memory
into distinct regions and implements protection by preventing disallowed accesses. The
MPU supports up to 8 regions each of which can be divided into 8 sub regions. The
region sizes supported start from 32 bytes and increase by factors of 2 to all of the
addressable memory of 4 gigabytes. Each region is associated with a region number that
is an index starting at 0, used to address the region. It is also possible to define a default
background memory map for privileged accesses. Accesses to memory locations that are
not defined in the MPU regions, or not permitted by the region setting, will cause the
Memory Management Fault exception to take place. The protection for the regions is
implemented with rules that are based on the type of transaction (read, write or execute)
and privilege of code performing the access. Each region includes a set of bits which
affect what kinds of accesses are permitted, as well as bits that affect what kind of bus
action is allowed. The MPU also supports overlapping regions, which are regions that
cover the same address. Since sizes are in multiples of 2, overlap means that one may be
fully enclosed within another. It is therefore possible to have multiple regions enclosed by
a single region and it is also possible to have nested overlapping. In the case of address
lookups to locations within overlapping regions, the region with the highest region
number is returned.
2.2.5 Debug and Trace

Figure2.7 The Cortex-M3 Trace System

The debug access into a Cortex-M3 processor based system is through the Debug
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Access Port (DAP) that can be implemented as either a Serial Wire Debug Port (SW-DP)
for a two-pin (clock and data) Interface or a Serial Wire JTAG Debug Port (SWJ-DP) that
enables either JTAG or SW protocol to be used. The SWJ-DP defaults to JTAG mode on
power reset and can be made to switch protocols with a specific control sequence
provided by the external debug hardware.
Debug actions can be triggered by various events like breakpoints, watchpoints, fault
conditions, or external debug requests. When a debug event takes place, the Cortex-M3
processor can either enter the halt mode or the debug monitor mode. During the halt
mode, the processor stops program execution completely. The halt mode supports single
step operations. Interrupts can be pended, and can get invoked during single stepping, or
be masked so external interrupts get ignored during stepping. During the debug monitor
mode, the processor executes an exception handler to carry out the debug tasks, while still
allowing higher priority exceptions to take place. This mode also supports single
stepping.
The Flash Patch and Breakpoint (FPB) unit implements six program breakpoints and two
literal data fetch breakpoints, or alternatively patches instruction or literal data from code
memory space to system memory space. The unit contains six instruction comparators for
matching against instruction fetches from code space. Each comparator can be enabled to
either remap code to an area in system space, or implement a hardware breakpoint, by
returning a breakpoint instruction to the processor. It also contains two literal
comparators, for matching against literal loads from code space and remapping to an area
in system space. The Data Watchpoint and Trace (DWT) unit contains four comparators,
each of which can be configured as hardware watchpoints. When used in this
configuration, the comparators can be programmed to compare either the data address or
program counter. The DWT comparators can also be configured to trigger PC sampler
events, data address sampler events and to cause the Embedded Trace Macrocell (ETM)
to emit trigger packets in the instruction trace stream. The ETM is an optional component
designed to support instruction trace alone to ensure that the reconstruction of program
execution is possible with minimal area impact. The ETM enables high-performance realtime trace of instruction execution and data transfers by compressing trace information
from the processor core to minimize bandwidth requirements. The Cortex-M3 processor
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implements data trace with the DWT and the Instrumentation Trace Macrocell (ITM).
The DWT provides instruction execution statistics and can generate watchpoint events to
invoke debug or trigger the ETM on specific system events. The ITM is an application
driven trace source that supports printf style debugging to trace OS and application
events. It accepts hardware trace packets from the DWT and software trace stimuli from
the processor core and emits diagnostic system information with timestamps. The Trace
Port Interface Unit (TPIU) accepts tracing information from the ETM and ITM; and then
merges, formats and emits it via the Serial Wire Viewer (SWV) to external trace analyzer
units. The SWV allows simple and cost effective profiling of system events by exporting
streams of data through a single pin. Manchester encoded and UART are supported
formats for the SWV.

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Chapter 3
HARDWARE DESCRIPTION
3.1 Block diagram

Figure3.1 Simplified block diagram of MCB1700

USB 2.0 Full Speed Interface
Standard USB connectors for USB Device, USB-OTG, USB Host and UART via USB on
the MCB1700 board for applications requiring USB communications.
Dual Serial Ports
Standard DB9 connectors are on the MCB1700 for both of the LPC1700's serial ports.
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Your application may use either of these ports.

Dual CAN Ports
Standard DB9 connectors are on the MCB1700 board for applications requiring CAN
communications. Our application may use either or both of these ports, or they may be
disabled with a configuration jumper.
100/10M Ethernet Port
A standard RJ45 connector on the MCB1700 board connects to an on-board Ethernet
transceiver for applications requiring Ethernet communications.
LCD Display
A detachable, 240x320 TFT, color LCD display. You may use this graphic display device
to show real-time debug and program status messages.
Micro SD Card Connector
A Micro SD Card connector for developing applications requiring access to Micro SD
Cards.
LF Amplifier
An LF Amplifier on the MCB1700 connects the D/A output of the LPC1700 device to a
speaker. You may use this LF Amplifier to generate sound.
Analog Voltage Control for ADC Input
An adjustable analog voltage source is on the MCB1700 board for testing the Analog to
Digital output feature of the LPC1700. A configuration jumper enables and disables this
feature.
JTAG and Cortex/ETM Download and Debug
The MCB1700 board incorporates both a JTAG interface and a Cortex Debug + ETM
interface. When coupled with the ULINK2 USB-JTAG adapter, the Serial Wire JTAG
interface allows flash programming and debugging. With the ULINK Pro adapter, the
Cortex Debug/ETM interface allows flash programming and instruction trace debugging.
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3.2 Architecture of LPC1768 Microcontroller

Figure 3.2 The LPC 1768 architecture

Features

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz.

ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

Up to 512 KB on-chip flash programming memory.

Up to 64 KB On-chip SRAM.

In-System Programming (ISP) and In-Application Programming (IAP).

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Eight channel General Purpose DMA controller (GPDMA).

Ethernet MAC with RMII interface and dedicated DMA controller.

USB 2.0 full-speed device/Host/OTG controller.

Four UARTs with fractional baud rate generation, internal FIFO, and DMA
support.

CAN 2.0B controller with two channels.

SPI controller with synchronous, serial, full duplex communication.

Two SSP controllers with FIFO and multi-protocol capabilities.

Three enhanced I2C bus interfaces.

I2S (Inter-IC Sound) interface.

70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors.

12-bit/8-ch Analog/Digital Converter (ADC) with conversion rates up to 200 kHz.

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Chapter-4

SOFTWARE DESCRIPTION
4.1 Altium designer for PCB designing
Altium Designer Viewer provides quick, easy, and secure read-only exploration of design
projects and documents that have been created using Altium Designer. Users can view,
print and interrogate all aspects of a design created by Altium Designer making design
data more accessible to the entire design-chain. The Altium Designer Viewer not only
enhances collaboration within an organization, but also between the design teams and
external parties, greatly improving design work flow and project productivity.
Altium Designer combines Schematic, ECAD Libraries, Rules & Constraints, BoM,
Supply Chain Management, ECO Processes and World-Class PCB Design tools in one
easy to use, Native 3D enhanced, Unified Environment, increasing your entire teams
productivity, efficiency and reducing your overall costs and time to market.
The Summer 09 release of Altium Designer continues the process of keeping you plugged
into a continuous stream of new features and technologies. They are designed to make it
easier for you to create your next generation electronics designs. And we continue to
make Altium Designer available to as many electronics designers as possible. Altium's
unified design architecture brings together hardware, software and programmable
hardware into a single application. This gives you the freedom to explore new design
ideas across a project, across a whole team. Everyone has a single view of the design
across the entire design process.
The Summer 09 release addresses a number of features and legacy issues requested by
you. These include the addition of more mechanical layers for board layout, and enhanced
definition of Net Classes on the schematic. This new release focuses on improving the
assignment and management of testpoints, refining embedded software development, and
taking debugging of the embedded intelligence in your soft designs to a whole new level,
and streamlining license management which will help you to get Altium Designer into the
hands of more of your engineers.

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4.1.1 PCB designing

A modern PCB can be compact, dense and small in size, making it difficult to present
important design information in the documentation. To help in this process the PCB
Editor supports placing a specific view of a PCB design within the workspace, which can
then be included in documentation output. This view is called a Design View, allowing
the designer to place a snapshot of any rectangular shaped region of the current board, or
another board. The Design View can be placed anywhere in the workspace and scaled to
any size. The following are the steps that need to perform in Altium designer for
designing a development board.

Draw schematics.

Attach footprints for all components.

Compile design.

Assign design rules.

Place components.

Check design rules.

Route PCB.

Check design rules.

Generate manufacturing files.

The below shown diagrams are the manufacturing files that are sent to manufacturer.
Since there is lack of equipment and experience we cannot manufacture and drill the
board hence we need to send some routed design files to the manufacturer and here are
some of them.

Top layer

Bottom layer

Heat dissipation layer

Drilling view

Top overlay

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Figure 4.1 Top layer of MCB1700 board

Figure 4.2 Bottom layer of MCB1700

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Figure 4.3 Top and Bottom layer of MCB1700 with copper heat dissipation layer applied

Figure 4.4 Drilling view of MCB1700

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Figure 4.5 Top overlay of MCB1700

4.2 Keil Vision 4

Keil Vision is a window-based software development platform that combines a robust
and modern editor with a project manager and make facility tool. It integrates all the tools
needed to develop embedded applications including a C/C++ compiler, macro assembler,
linker/locator, and a HEX file generator. Vision helps expedite the development process
of embedded applications by providing the following:

Full-featured source code editor.

Device Database for configuring the development tool.

Project Manager for creating and maintaining your projects.

Integrated Make Utility functionality for assembling, compiling, and linking your
embedded applications.

Dialogs for all development environment settings.

True integrated source-level and assembler-level Debugger with high-speed CPU

and peripheral Simulator.

Advanced GDI interface for software debugging on target hardware and for
connecting to a Keil ULINK Debug Adapter.

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Flash programming utility for downloading the application program into Flash
ROM.

Links to manuals, on-line help, device datasheets, and user guides.

Figure 4.6 Program execution process

Figure 4.7 An example of coding.

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4.3 Flash Magic

Flash Magic is a tool which used to program hex code in EEPROM of micro-controller. it
is a freeware tool. It only supports the micro-controller of Philips and NXP. You can burn
a hex code into those controller which supports ISP (in system programming) feature. To
check whether your micro-controller supports ISP or not take look at its datasheet. So if
your device supports ISP then you can easily burn a hex code into EEPROM of your
device. Flash magic supports several chips like ARM Cortex M0, M3, M4, ARM7 and
8051. The procedure to program code memory is very easy and needs only five steps to
configure Flash magic for better operation. Flash magic use Serial or Ethernet protocol to
program the flash of device.

Figure 4.8 Screen shot of flash magic tool

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4.4 Tera term

Tera Term is one of the more popular Windows terminal programs. Its been
around for years, its open source, and its simple to use. For Windows users, its one of
the best options out there.

Figure 4.9 Tera term connection

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Chapter 5
CIRCUIT DIAGRAM
5.1 LPC1768 Microcontroller

Figure 5.1 LPC1768 Micro controller

The embedded Microcontroller in particular is designed for prototyping all sorts of
devices, especially those including Ethernet, USB, and the flexibility of lots of peripheral
interfaces and FLASH memory. It is packaged as a small DIP form-factor for prototyping
with through-hole PCBs, strip board and breadboard, and includes a built-in USB FLASH
programmer.
Features

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz on high

speed

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Ethernet, USB Host/Device, 2xSPI, 2xI2C, 3xUART, CAN, 6xPWM, 6xADC,

GPIO.

Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options. Emulation trace module supports real-time trace.

Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep powerdown.

Single 3.3 V power supplies (2.4 to 3.6 V). Temperature range of -40C to 85
C.

Four external interrupt inputs configurable as edge/level sensitive. All pins on

PORT0 and PORT2 can be used as edge sensitive interrupt sources. Non-mask
able Interrupt (NMI) input.

Clock output function that can reflect the main oscillator clock, IRC clock, RTC
clock, CPU clock, or the USB clock.

The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake
up from any priority interrupt that can occur while the clocks are stopped in deep
sleep, Power-down, and Deep power-down modes.

5.2 Power Supply

The MCB1700 board contains a standard USB "B" connector that supplies power to the
board and allows the board to be configured as a USB device.The MCB1700 boards also
include two additional USB connectors:a USB "mini-B" connector for USB-OTG (OnThe-Go) applications. a USB Micro AB connector for USB hosting applications. The D+
and D- Jumpers configure the connectors for for OTG, Device or Host applicationsWhen
the board is powered from an external power supply at VIN and the USB connector is
needed for data exchange, the VBUS jumper should be removed.
IC LD1117S33 is a LOW DROP Voltage Regulator able to provide up to 800mA of
Output Current, available even in adjustable version (Vref=1.25V). Concerning fixed
versions are offered the following Output Voltages: 1.2V, 1.8V, 2.5V, 2.85V, 3.0V 3.3V
and 5.0V. In this board LD1117S33. IC is used to convert 5v form USB to 3.3v in which
microcontroller works.
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Figure 5.2 Power supply

5.3.Ethernet
Ethernet is a family of computer networking technologies for local area networks
(LANs). Ethernet was commercially introduced in 1980 and standardized in 1983 as
IEEE 802.3. The Ethernet standards comprise several wiring and signaling variants of the
OSI physical layer in use with Ethernet. The original 10BASE5 Ethernet used coaxial
cable as a shared medium. Later the coaxial cables were replaced with twisted pair and
fiber optic links in conjunction with hubs or switches. Data rates were periodically
increased from the original 10 megabits per second to 100 gigabits per second. The
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Ethernet Interface on the MCB1700 board uses the 10/100 Fast Ethernet 3.3V National
Semiconductor DP83848 (IC12).

Figure 5.3 Ethernet Schematic

5.4 CAN
The dual CAN Interfaces use the TJA1040 CAN driver (IC3 for CAN1 and IC4 for
CAN2) and termination resistors (R4 and R6 for CAN1 and R13 and R15 for CAN2) on
the MCB1700 board. The driver settings may be changed by the configuration
jumpers.The CAN1 and CAN2 DB9 connectors are wired identically (Pin 2 provides the
CANL signal and Pin 7 provides the CANH signal) and each is connected to a TJA1040
CAN driver IC.
TJA1040 is a high speed transreceiver.it is interface between CAN protocal and controller
and physical bus. It is primarily intended to high speed applications upto 1MBaud, in
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passenger cars. The device provides differential transmit capability to the bus and
differential recevie capability to can controller.

Figure 5.4 CAN Schematic and Pin diagram of TJA1040

TJA1040 is a high speed transreceiver.it is interface between CAN protocal and controller
and physical bus. It is primarily intended to high speed applications upto 1MBaud, in
passenger cars. The device provides differential transmit capability to the bus and
differential recevie capability to can controller.

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5.5 Speaker
The MCB1700 board includes a speaker controlled by the output of the on-chip D/A
converter. The LM386M low voltage power amplifier (IC13) amplifies the D/A output to
drive the speaker. Jumper SPK connects the D/A output (Port 0, pin 26, P0.26/AOUT) to
the input of the LM386M amplifier. Removing this jumper disables the speaker. PJ2: D/A
Output for loudspeaker: connects the AOUT output to the LF amplifier.

Figure 5.5 Schematic of Speaker

5.6 LED
The 8 Port LEDs marked P1.28, P1.29, P1.31 and P2.2 - P2.6 connect to their respective
port pins when jumper LED is installed. These LEDs are useful for indicating program
status while testing your applications. Removing Jumper LED disables the LED driver
chip.

5.7 LCD TFT Panel

The LCD-TFT colour graphics display panel contains a 240x320 pixel screen and
connects using a 16-bit interface. The LCD panel connects to MCB1700 board via 30-pin
header.

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Figure 5.6 Schematic of LED

Figure 5.7 Schematic of LCD TFT panel

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5.8 JTAG Interface

The JTAG Interface connector provides debugging and emulator support for the NXP
LPC17xx device. The JTAG Interface allows application debugging and programming of
on-chip and off-chip Flash devices.

Figure 5.8 Schematic of JTAG connector

The Cortex Debug connector provides support for Serial Wire JTAG feature of the
Cortex-M3 device. Serial Wire JTAG is capable of Serial Wire Output for target
debugging in addition to allowing application programming and debugging of on-chip
and off-chip Flash devices as in standard JTAG.

5.9 Serial port

The MCB1700 board connects the ASC0 on-chip serial UART to the ST3232 (IC6),
which converts the logic signals to RS-232 voltage levels. The ASC0 UART may be used
in bootstrap mode to download other utilities for debugging or downloading flash. In
addition to the standard 3-wire interface, the COM0 DB9 connector is wired to allow a
board RESET via the DTR pin, and to enable In-System Programming (ISP) via the RTS
pin as shown in the figure. The COM1 DB9 connector uses the standard 3-wire interface
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and does not connect the DTR or RTS pins to any board component as shown in the
figure.

Figure 5.9 Schematic of Serial port and Pin description of DB9

The MCB1700 board connects the ASC0 on-chip serial UART to the ST3232 (IC6),
which converts the logic signals to RS-232 voltage levels. The ASC0 UART may be used
in bootstrap mode to download other utilities for debugging or downloading flash. In
addition to the standard 3-wire interface, the COM0 DB9 connector is wired to allow a
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board RESET via the DTR pin, and to enable In-System Programming (ISP) via the RTS
pin as shown in the figure. The COM1 DB9 connector uses the standard 3-wire interface
and does not connect the DTR or RTS pins to any board component as shown in the
figure.

5.10 Ports

Figure 5.10 Schematic of different ports

The prototyping area provides blocks for adding components and connecting the address,
data, and I/O ports. All microcontroller signals are brought out to pins and are driven
directly by the microcontroller.

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Chapter 6
FLOW CHART OF DEVELOPMENT BOARD

Start

Specification/input .Hand drawn schematics or

other form BOM (bill of materials) with part
number PDF of data sheet of all non-routing parts

Schematic library generation for new parts

Schematic entry

Electric rule check

Specification for board size number of layers,

shapes, layer, layer management, power plane/
split plane

Component placement

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Design rule setup

Routing

Polygon

Design verification

Design rule check

CAM file generation

Gerber NC drill PDF, pic and place assembly file

Manufacture

End

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Chapter 7

CONCLUSION AND FUTURE WORKS

7.1 Conclusion
The board that we have designed is of low cost and it contains many peripherals in it.
Resources Systems internal LPC1768 are quite perfect and suitable for learning and
testing the operations. If user learns and understands all resources internal MCU well,
user is able to adapt and apply or develop many additional applications as well. The board
also supports group of customers and engineers who actually want to study, test, adapt or
apply application by self. This boards structure consists of necessary devices that are
suitable for basic test and study.

7.2 Future works

The MCB1700 board has many peripherals slots that can be built in future days. The
peripherals like Ethernet can be used for future development in applications like home
automation, LAN based techniques etc. The CAN ports are used in automatic locking
system in vehicles, it can be also used for ABS gearing system, airbags etc. The board can
also be used for applications such as automatic lighting, e-metering etc. This board is a
general purpose board and can be used for different purpose in different fields.

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REFERENCES

Aruna Kommu, Raghavendra Rao Kanchi. Design and Development of a ProjectBased Embedded System Laboratory Using LPC1768. American Journal of
Embedded Systems and Applications. Vol. 1, No. 2, 2013, pp. 46-53. doi:
10.11648/j.ajesa.20130102.13

Jiang Xiaoluo and Li Han, CDIO Based Embedded systems training mode in
graduate teaching, 2011 5th International conference on distance learning and
education, vol. 12, pp. 78-82.

Silik. C, Nagvaara, P. Taskin. B, A Microcontroller based embedded system

design course with PSoC3, IEEE International conference on Microelectronic
Systems Education (MSE), June. 2-3, 2013, pp.28-31.

LPC 1768 User manual.

Websites

http://www.keil.com

http://www.digikey.com

http://www.arm.com

Draw schematics
2. Attach footprints for all
components
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3. Compile design
4. Assign design rules
5. Place compo
rus

7. Route PCB
8. Check design rules
9. Generate manufacturing files

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