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uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
3 Description
Short-Circuit Protection
Offset-Voltage Null Capability
Large Common-Mode and Differential Voltage
Ranges
No Frequency Compensation Required
No Latch-Up
2 Applications
PACKAGE (PIN)
SOIC (8)
4.90 mm 3.91 mm
PDIP (8)
9.81 mm 6.35 mm
SO (8)
6.20 mm 5.30 mm
4 Simplified Schematic
OFFSET N1
IN +
IN
OUT
OFFSET N2
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
5
6
6
6
7
8.2
8.3
8.4
8.5
5 Revision History
Changes from Revision D (February 2014) to Revision E
Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
Page
Page
uA741
www.ti.com
14
13
12
11
10
NC
NC
NC
VCC +
OUT
OFFSET N2
NC
OFFSET N1
IN
IN +
VCC
10
NC
VCC+
OUT
OFFSET N2
NC
OFFSET N1
NC
NC
NC
A741M . . . FK PACKAGE
(TOP VIEW)
A741M . . . U PACKAGE
(TOP VIEW)
NC
OFFSET N1
IN
IN +
VCC
NC
NC
VCC +
OUT
OFFSET N2
4
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
NC
NC
IN
NC
IN +
NC
NC
VCC +
NC
OUT
NC
VCC
NC
OFFSET N2
NC
NC
NC
OFFSET N1
IN
IN +
VCC
NC
A741M . . . JG PACKAGE
A741C, A741I . . . D, P, OR PW PACKAGE
(TOP VIEW)
NC No internal connection
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
JG, D, P, or
PW
FK
IN+
Noninverting input
IN
Inverting input
NC
1, 2, 8,
12, 13,
14
1, 9, 10
1,3,4,6,8,9,11,13,1
4,16,18,19,20
Do not connect
OFFSET
N1
OFFSET
N2
12
OUT
10
15
Output
VCC+
11
17
Positive supply
VCC
10
Negative supply
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over virtual junction temperature range (unless otherwise noted) (1)
A741C
A741M
MIN
MAX
MIN
MAX
UNIT
VCC
18
18
22
22
VID
15
15
30
30
VI
15
15
15
15
Voltage between offset null (either OFFSET N1 or OFFSET N2) and VCC
15
15
0.5
0.5
Unlimited
Tstg
(1)
(2)
(3)
(4)
(5)
See Table 1
125
FK package
N/A
N/A
260
J, JG, or U package
N/A
N/A
300
D, P, or PS package
70
65
55
260
N/A
N/A
150
65
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC.
Differential voltages are at IN+ with respect to IN .
The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
The output may be shorted to ground or either power supply. For the A741M only, the unlimited duration of the short circuit applies at
(or below) 125C case temperature or 75C free-air temperature.
15
15
A741C
70
A741M
55
125
Supply voltage
VCC
TA
MAX
UNIT
V
C
PACKAGE
TA 25C
POWER
RATING
DERATING
FACTOR
DERATE
ABOVE TA
TA = 70C
POWER
RATING
TA = 85C
POWER RATING
TA = 125C
POWER RATING
500 mW
5.8 mW/C
64C
464 mW
377 mW
N/A
FK
500 mW
11.0 mW/C
105C
500 mW
500 mW
275 mW
500 mW
11.0 mW/C
105C
500 mW
500 mW
275 mW
JG
500 mW
8.4 mW/C
90C
500 mW
500 mW
210 mW
500 mW
N/A
N/A
500 mW
500 mW
N/A
PS
525 mW
4.2 mW/C
25C
336 mW
N/A
N/A
500 mW
5.4 mW/C
57C
432 mW
351 mW
135 mW
uA741
www.ti.com
TEST CONDITIONS
VIO
VO = 0
VIO(adj)
VO = 0
IIO
VO = 0
IIB
VO = 0
VICR
25C
TYP
1
25C
15
25C
20
Full range
25C
80
Full range
A741M
MAX
MIN
TYP
MAX
7.5
15
20
200
200
500
300
500
500
80
800
25C
12
12
RL = 10 k
25C
12
RL 10 k
Full range
12
12
RL = 2 k
25C
10
10
RL 2k
Full range
10
RL 2k
25C
20
Full range
15
25C
0.3
AVD
ri
Input resistance
ro
Output resistance
Ci
Input capacitance
CMRR
kSVS
IOS
VO = 10 V
VO = 0, See (2)
VIC = VICRmin
ICC
Supply current
VO = 0, No load
PD
VO = 0, No load
13
UNIT
mV
mV
nA
500
nA
1500
Full range
(2)
A741C
MIN
Full range
VOM
(1)
TA (1)
12
13
12
14
12
14
V
13
10
200
50
200
V/mV
25
2
0.3
25C
75
75
25C
1.4
1.4
pF
25C
70
Full range
70
25C
90
70
90
dB
70
30
Full range
150
30
150
150
150
25C
25
40
25
40
25C
1.7
2.8
1.7
2.8
Full range
25C
Full range
3.3
50
85
100
V/V
mA
mA
3.3
50
85
100
mW
All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full
range for the A741C is 0C to 70C and the A741M is 55C to 125C.
This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
www.ti.com
A741Y
TEST CONDITIONS
MIN
TYP
MAX
5
UNIT
VIO
VO = 0
VIO(adj)
VO = 0
15
IIO
VO = 0
20
200
nA
IIB
VO = 0
80
500
nA
VICR
VOM
AVD
ri
Input resistance
12
13
RL = 10 k
12
14
RL = 2 k
10
13
20
200
0.3
RL 2k
ro
Output resistance
Ci
Input capacitance
CMRR
VIC = VICRmin
kSVS
VCC = 9 V to 15 V
IOS
ICC
Supply current
VO = 0, No load
PD
VO = 0, No load
(1)
VO = 0, See
(1)
mV
mV
V
V
V/mV
M
75
1.4
pF
70
90
dB
30
150
V/V
25
40
mA
1.7
2.8
mA
50
85
mW
This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.
Rise time
Overshoot factor
SR
TEST CONDITIONS
A741C
MIN
VI = 20 mV, RL = 2 k,
CL = 100 pF, See Figure 1
VI = 10 V, RL = 2 k,
CL = 100 pF, See Figure 1
TYP
A741M
MAX
MIN
TYP
MAX
UNIT
0.3
0.3
5%
5%
0.5
0.5
V/s
Rise time
Overshoot factor
SR
TEST CONDITIONS
VI = 20 mV, RL = 2 k,
CL = 100 pF, See Figure 1
VI = 10 V, RL = 2 k,
CL = 100 pF, See Figure 1
A741Y
MIN
TYP
MAX
UNIT
0.3
5%
0.5
V/s
uA741
www.ti.com
VI
OUT
IN
+
0V
INPUT VOLTAGE
WAVEFDORM
CL = 100 pF
RL = 2 k
TEST CIRCUIT
400
VCC+ = 15 V
VCC = 15 V
350
90
80
70
60
50
40
30
VCC+ = 15 V
VCC = 15 V
300
250
200
150
100
20
50
10
0
60 40 20
20
40
60
0
60 40 20
TA Free-Air Temperature C
60
20
VCC+ = 15 V
VCC = 15 V
TA = 25C
40
14
12
20
TA Free-Air Temperature C
13
11
10
9
8
7
6
5
4
0.1
0.2
0.4
0.7 1
18
16
VCC+ = 15 V
VCC = 15 V
RL = 10 k
TA = 25C
14
12
10
8
6
4
2
0
100
10
RL Load Resistance k
1k
10k
100k
1M
f Frequency Hz
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
www.ti.com
VO = 10 V
RL = 2 k
TA = 25C
200
VCC+ = 15 V
VCC = 15 V
VO = 10 V
RL = 2 k
TA = 25C
100
400
100
40
20
90
80
70
60
50
40
30
20
10
0
10
0
10
12
14
16
18
10
1
20
10
100
1M
100k
10M
100
VCC+ = 15 V
VCC = 15 V
BS = 10 k
TA = 25C
90
80
24
20
VO Output Voltage mV
10k
1k
f Frequency Hz
70
60
50
40
30
20
90%
16
12
8
VCC+ = 15 V
VCC = 15 V
RL = 2 k
CL = 100 pF
TA = 25C
4
10%
0
10
tr
4
0
1
100
10k
1M
100M
f Frequency Hz
0.5
1.5
2.5
t Time - s
8
VCC+ = 15 V
VCC = 15 V
RL = 2 k
CL = 100 pF
TA = 25C
6
4
VO
2
0
VI
2
4
6
8
0
10
20
30
40
50
60
70
80
90
t Time ms
uA741
www.ti.com
8 Detailed Description
8.1 Overview
The A741 device is a general-purpose operational amplifier featuring offset-voltage null capability.
The high common-mode input voltage range and the absence of latch-up make the amplifier ideal for voltagefollower applications. The device is short-circuit protected and the internal frequency compensation ensures
stability without external components. A low value potentiometer may be connected between the offset null
inputs to null out the offset voltage as shown in Figure 11.
The A741C device is characterized for operation from 0C to 70C. The A741M device (obsolete) is
characterized for operation over the full military temperature range of 55C to 125C.
IN
OUT
IN+
OFFSET N1
OFFSET N2
VCC
Component Count
Transistors
Resistors
Diode
Capacitor
22
11
1
1
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
www.ti.com
(7)
(6)
IN +
IN
OFFSET N1
(8)
OFFSET N2
(3)
(2)
(1)
(5)
VCC+
(7)
+
(6)
OUT
(4)
VCC
45
(5)
(1)
(4)
(2)
(3)
36
10
uA741
www.ti.com
IN +
OUT
IN
OFFSET N2
OFFSET N1
10 k
To VCC
10 k
12 V
VOUT
+
VIN
11
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
www.ti.com
0.045
0.040
10
0.035
0.030
0.025
IIO (mA)
VOUT (V)
8
6
0.020
0.015
0.010
0.005
0.000
0
0.005
0
10
VIN (V)
12
6
VIN (V)
C001
10
12
C002
0.45
0.40
0.35
ICC (mA)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
10
VIN (V)
12
C003
12
uA741
www.ti.com
Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, SLOA089.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
RIN
RG
VOUT
RF
13
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
www.ti.com
RF
NC
NC
GND
IN1
VCC+
VIN
IN1+
OUT
VCC
NC
VS+
Use low-ESR, ceramic
bypass capacitor
RG
RIN
GND
VOUT
14
uA741
www.ti.com
12.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
UA741CD
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
UA741C
UA741CDG4
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
UA741C
UA741CDR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
UA741C
UA741CDRG4
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
UA741C
UA741CJG
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
0 to 70
UA741CJG4
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
0 to 70
UA741CP
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
UA741CP
UA741CPE4
ACTIVE
PDIP
50
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
UA741CP
UA741CPSR
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
U741
UA741CPSRE4
ACTIVE
SO
PS
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
U741
UA741MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
UA741MJ
OBSOLETE
CDIP
14
TBD
Call TI
Call TI
-55 to 125
UA741MJB
OBSOLETE
CDIP
14
TBD
Call TI
Call TI
-55 to 125
UA741MJG
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
-55 to 125
UA741MJGB
OBSOLETE
CDIP
JG
TBD
Call TI
Call TI
-55 to 125
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
www.ti.com
10-Jun-2014
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
17-Feb-2014
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UA741CDR
SOIC
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UA741CPSR
SO
PS
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
Pack Materials-Page 1
17-Feb-2014
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UA741CDR
UA741CPSR
SOIC
2500
340.5
338.1
20.6
SO
PS
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
0.280 (7,11)
0.245 (6,22)
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.023 (0,58)
0.015 (0,38)
015
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
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Applications
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