CY6

PRELIMINARY

8K x 8
Static
RAM

Features

55, 70 ns access

times

over 70% when

2
CMOS for optimumdeselected.
The
CY6264 is packaged
speed/power
3
Easy
memory in a 450-mil (300-mil
expansion with CE , body) SOIC.
1

CE2, and OE fea-tures

4
TTL-compatible
inputs and outputs

An active LOW write

enable signal (WE)
controls
the
writing/reading operation
of the memory. When
1 and WE in-puts
5
Automatic power-CE
are both LOW and
down when deselected CE2 is HIGH, data on
the
eight
data
Functional Description input/output pins (I/O0
through
I/O7)
is
written
into
the
The CY6264 is a high-memory
location
performance CMOS static RAMaddressed by the
address present on
orga-nized as 8192 words by 8
bits. Easy memory expansion isthe address pins (A0
A12).
provided by an active LOW chip through
Reading the device is
accomplished
by
enable (CE1), an active HIGH

these conditions, the

contents
of
the
location ad-dressed
by the information on
address
pins
is
present on the eight
data
input/output
pins.
The input/output pins
remain in a highimpedance
state
unless the chip is
selected, outputs are
enabled, and write
enable (WE) is HIGH.
A die coat is used to
insure alpha immunity.

selecting the device and

the outputs, CE1

chip enable (CE2), and activeenabling
LOW output enable (OE) andand OE
three-state
drivers.
Both
devices have an automaticactive LOW, CE2
active HIGH, while
pow-er-down feature (CE1),WE remains inactive
reducing
the
power
or HIGH. Under
consumption by

Logic

Block

OE

SOIC
Top View
NC

I/O2

1
2
3
4
5
6
7
8
9
10
11
12
13

GND

14

A4
A

A6
A7
A

A9

10

A1
A2
A3
A4

A5
A6
A7

CE1
CE2

WE

11

12

I/O0
I/O1

CY6264-2

Diagram
Pin
Configuration

Maximum
Ratings
Maximum Access Time (ns)

Output Current into Outputs (LOW) CY6264-55

Static Discharge Voltage ..........................................
55
(per MIL-STD-883, Method 3015)

Latch-Up Current ....................................................

Maximum
Operating
Current
(mA)
100
(Above
which
the useful
life may
be impaired. For user guide-lines,
Maximum Standby Current (mA)
20/15
not tested.)
Operating
Shaded area contains advanced information.

Storage Temperature .................................

Range
Ambient Temperature with
Power Applied.............................................
Cypress Semiconductor Corporation
Supply Voltage to Ground Potential ...............
DC Voltage Applied to Outputs
[1]
in High Z State ............................................
[1]

DC Input Voltage .........................................

PRELIMINARY

Electrical Characteristics
Over the Operating Range

3901 North First Street San Jose

CY6264

Range

Ambient
Temperature

Commercial

0C to +70C
I

Parameter
V

m voltage is equal to -3.0V for

pulse durations less than 30
ns.

advanced
information.

Output HIGH Voltage

Capacita 2.

OL

Output ILOW
Voltage
SB1

nce

CC

IH

Input HIGH Voltage

IL

Input LOW
SB2 Voltage

Input Load Current

V
I

Description
I

CC

5V 10%

OH

OS

IX

Output Shaded
Leakage
Currentarea
contains

OZ

5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE

[3]

Not more than 1 output

should be shorted at one
time. Duration of the short
circuit should not exceed 30
seconds.

Parameter
3. Tested

IN

OUT

Notes:

1.

Minimu

initially and after any

design or process changes
that
may
affect
these
parameters.

AC Test Loads and

Waveforms

R1 481

5V
OUTPUT

ALL INPUT PULSES

3.0V
5 pF

INCLUDING
JIG AND
SCOPE (b)
Equivalent to:
THVENIN
EQUIVALENT
167
O
U
T
P
U
T
1
.
7
3
V

R2
255

CY6264-3

10%
GND
< 5 ns

90%

90%
10%
< 5 ns
CY6264-4

P
R
E
L
I
M
I
N
A
R
Y
Switching Characteristics Over the Operating Range

[4]

6264-55
Parameter

Description

READ CYCLE
t

Max.

RC

Read Cycle Time

AA

Address to Data Valid

OHA

Data Hold from Address Change

ACE1

CE 1 LOW to Data Valid

55

ACE2

CE2 HIGH to Data Valid

40

DOE

OE LOW to Data Valid

LZOE

OE LOW to Low Z

HZOE

OE HIGH to High Z

LZCE1

CE 1 LOW to Low Z

LZCE2

CE2 HIGH to Low Z

HZCE

CE 1 HIGH to High Z
CE2 LOW to High Z

t
t
t
t
t
t
t
t
t
t

Min.

t
t

55

[5]

[6]
[5, 6]

PU

CE 1 LOW to Power-Up

PD

CE 1 HIGH to Power-Down

[7]

WRITE CYCLE
t

55
5

25
3
20
5
3
20
0
25

WC

Write Cycle Time

50

SCE1

CE 1 LOW to Write End

40

SCE2

CE2 HIGH to Write End

30

AW

Address Set-Up to Write End

40

HA

Address Hold from Write End

SA

Address Set-Up to Write Start

t
t
t
t
t
t
t
t
t

Pulse Width

0
25

PWE

WE

SD

Data Set-Up to Write End

25

HD

Data Hold from Write End

HZWE

[5]

LOW to High Z

20

WE

WE

LZWE

HIGH to Low Z

Shaded area contains advanced information.

Notes:

4.
5.
6.
7.

Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I OL/IOH and 30-pF load
capacitance.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured
500 mV from steady-state voltage.
At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.

The internal write time of the memory is defined by the overlap of CE 1 LOW, CE2 HIGH, and WE
LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going
HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal
that terminates the write.

PRELIMINARY
Switching Waveforms
[8, 9]

Read Cycle No.1

RC

ADDRESS

AA

OHA

DATA OUT

Read Cycle No. 2

PREVIOUS DATA VALID

[10, 11]

CE1

RC

CE2

ACE

OE

t
t

DOE

LZOE

DATA OUT
V

CC

HIGH IMPEDANCE

t
t

PU

LZCE

DATA VALID

SUPPLY
CURRENT

50%

Write Cycle No. 1 (WE Controlled)

[9, 11]

WC

ADDRESS

SCE1

CE1

CE2

SCE2

OE
t
AW
t
t

WE

HA

SA

PWE

tSD

t
DATA IN

HD

DATAIN VALID

HZWE

DATA I/O

LZWE

HI
G
H
I
M
P
E
D
A
N
C
E

DATA UNDEFINED
CY6264-7

Notes:

8. Device is continuously selected. OE, CE = VIL. CE2 = VIH.

9. Address valid prior to or coincident with CE transition LOW.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = VIH, CE1 = VIH, or WE = VIL.
4

PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)

[9, 11, 12]

WC

ADDRESS

CE1

SCE1

SA

CE

SCE2

AW

PWE

WE

SD

DATAIN VALID

DATA IN

HZWE

DATA I/O

HIGH IMPE

DATA UNDEFINED

Note:
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Typical DC and AC Characteristics

NORMALIZED SUPPLY CURRENT vs.
SUPPLY VOLTAGE

1.4
1.2

CC

1.0
0.8
0.6
0.4
0.2
0.0
4.0

I
4.5

5.0

NORMALI
ZED
SUPPLY
CURRENT
vs.
AMBI
ENT
TEMP
ERAT
URE
1.2

1.0
SB

0.8
5.5

6.0

NORMALIZED ACCESS TIME vs.

SUPPLY VOLTAGE
1.4

0.6

0.2

0.0
55

1.3

TA =25C

1.0
0.9
0.8
4.0

4.5

5.0

5.5

SB

AM
BIE
NT
TE
MP
ER
AT
UR
E
(C)

1.2
1.1

1.6

A
C
C
E
S
S

1.2

T
I
M
E

0.4

SUPPLY VOLTAGE (V)

M
A
L
I
Z
E
D

6.0

SUPPLY VOLTAGE (V)

N
O
R

v
s
.
A
M
B
I
E
N
T
T
E
M
P
E
R
A
T

U
R
E

1.4

1.0

VCC

0.8
0.6
25

55
AMB
IEN
T
TEM
PER
ATU
RE
(C)

OUTPUT SOURCE CURRENT vs.

OUTPUT VOLTAGE

OUTP
UT
VOLT
AGE
(V)

120
100
80

O
U
T

VCC =5.0V

60

TA =25C

40

P
U
T

20
0
0.0

1.0

2.0

3.0

4.0

I
N

U
T

C
U

P
U

R
R

E
N

V
O

L
T

v
s

A
G

140
120
100

VCC =5.0V
TA =25C

80
60
40
20
0
0.0

1.0

2.0

3.0

OUTPUT VOLTAGE (V)

4.0

PRELIMINARY
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT vs.
SUPPLY VOLTAGE
3.0

2.5

2.0

1.5

TYPI
CAL
ACC
ESS
TIME
CHA
NGE
vs.
OUT
PUT
LOA
DING
30.0

NORMAL
IZED ICC

vs.
CYCLE
TIME
1.25
VCC =5.0V
TA =25C

1.00

25.0

0.75

20.0

1.0

0.50
10

15.0
0.5
0.0

VCC =0.5V

10.0
5.0
0.0

1.0

2.0

3.0

4.0

SUPPLY VOLTAGE(V)

5.0

0.0

200

C
Y
C
L
E
F
R
E
Q
U
E
N
C
Y
(
M
H
z
)

Truth Table
CE1
H

CE2
X

WE
X

OE
X

High Z

High Z

Data Out

Data In

High Z

Address Designators
Address
Name

Address
Function

A4

X3

A5

X4

A6

X5

A7

X6

A8

X7

A9

Y1

A10

Y4

A11

Y3

A12

Y0

A0

Y2

A1

X0

A2

X1

A3

X2

PREL
IMIN
ARY
Ordering Information
Speed
(ns)

Ordering Code

Package
Name

Package Type

[13]

Ope
Ra

55

CY6264-55SC

S23

28-Lead 330-Mil SOIC

Comme

70

CY6264-70SC

S23

28-Lead 330-Mil SOIC

Comme

55
70

CY6264-55SNC
CY6264-70SNC

S22
S22

28-Lead 300-Mil SOIC

28-Lead 300-Mil SOIC

Comme
Comme

Shaded area contains advanced information.

Note:
13. Not recommended for new designs.

Document #: 38-00425-A

Package Diagrams
28-Lead 450-Mil (300-Mil Body Width)
SOIC S22

[13]

PRELIMINARY
Package Diagrams

(continued)

28-Lead (330-Mil) SOIC

S23

 Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress
Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress
Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not
authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be
expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor
against all charges.