Digital System Design

Lecture 16

Parallel Adders

Barrel Shifters

Parallel Adders

Barrel Shifters

A barrel shifter is a digital circuit that can shift a data word

by a specified number of bits in one clock cycle.

For example, take a four-bit barrel shifter, with inputs A, B,

C and D. The shifter can cycle the order of the bits ABCD as
DABC, CDAB, or BCDA; in this case, no bits are lost. That is, it
can shift all of the outputs up to three positions to the right
(and thus make any cyclic combination of A, B, C and D). The
barrel shifter has a variety of applications, including being a
useful component in microprocessors(alongside the ALU).

Parallel Adders

Barrel Shifters

Uses
A common usage of a barrel shifter is in the hardware
implementation of floating-point arithmetic. For a floatingpoint add or subtract operation, the significands of the two
numbers must be aligned, which requires shifting the smaller
number to the right, increasing its exponent, until it matches
the exponent of the larger number. This is done by
subtracting the exponents, and using the barrel shifter to shift
the smaller number to the right by the difference, in one
cycle. If a simple shifter were used, shifting by n bit positions
would require n clock cycles.
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Barrel Shifters
A single cycle N bit logic shifter implementing x>>s ,where s is a

signed integer number, can be implemented by hardwiring all the

possible shift results as input to a multiplexer and then using s to select
the appropriate option at the output.
The shifter performs a shift left operation for negative values of s. For
example, x2 implies a shift left by 2. The design of the shifter is shown in
Figure(a), where x is the input operand and all possible shifts are pre
performed as input to the MUX and s is used as a select line to the
MUX. The figure clearly shows that, for negative values of s, its
equivalent positive number will be used by the MUX for selecting
appropriate output to perform a shift left operation.
The design can be trivially extended to take care of arithmetic along
with the logic shifts. This requires first selecting either the sign bit or 0
for appropriately appending to the left of the operand for shift right
operation. For shift left operation, the design for both arithmetic and
logic shift is same.
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CPA-Carry Propagate Adder

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 Read :
Section 5.6, 5.7,5.8 Digital Design of Signal Processing

Systems by Shoab Ahmed khan

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Best way to learn DSD is to do it!

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