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Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with
permission.
Nathan Ickes
Rex Min
Positive
Latch
D Q
Clk
D Q
Positive
Register
Clk
Latches are used to build Registers (using the Master-Slave Configuration), but
are almost NEVER used by itself in a standard digital design flow.
Quite often, latches are inserted in the design by mistake (e.g., an error in your
Verilog code). Make sure you understand the difference between the two.
Several types of memory elements (SR, JK, T, D). We will most commonly use
the D-Register, though you should understand how the different types are built
and their functionality.
In
D Q
Combinational
Logic
Clk
Clk
D Q
Combinational
Logic
D Q
D Q
Clk
Clk
CLK
Th
Th
IN
Tsu
Tsu
Tcq
Tcq
FF1
Tcq,cd
Tlogic
Tcq,cd
CLout
Tl,cd
Tsu2
Combinational
Logic
D Q
D Q
Clk
Clk
CLK
Th
Th
IN
Tsu
FF1
Tcq,cd
CLout
Tl,cd
Sequential
1
D Q
out
b
0
sel
out
0
sel
clk
6
tc-q
Clear happens on
falling edge of clearb
@ (a or b or c)
a | b;
a ^ b ^ c;
b & ~c;
Flip-Flop Based
Digital Delay
Line
in
D Q
q1
D Q
q2
D Q
out
clk
10
q1
in
D Q
clk
q2
D Q
D Q
in
out
q1 q2
D Q
out
clk
11
Simulation
Non-blocking Simulation
Blocking Simulation
12
x = a & b;
y = x | c;
abc xy
110
010
010
010
11
11
01
00
a
b
module blocking(a,b,c,x,y);
input a,b,c;
output x,y;
reg x,y;
always @ (a or b or c)
begin
x = a & b;
y = x | c;
end
endmodule
Nonblocking Behavior
(Given) Initial Condition
a changes;
always block triggered
x <= a & b;
y <= x | c;
Assignment completion
abc xy
110
010
010
010
010
11
11
11
11
01
Deferred
x<=0
x<=0, y<=1
module nonblocking(a,b,c,x,y);
input a,b,c;
output x,y;
reg x,y;
always @ (a or b or c)
begin
x <= a & b;
y <= x | c;
end
endmodule
13
Count[0]
D Q
Q
D Q
Q
Count[1]
D Q
Q
Count[2]
Count[3]
D Q
Q
Clock
D register set up to
always toggle: i.e., T
Register with T=1
Skew
Count [3]
Count [2]
Count [1]
Count [0]
Clock
14
Count [3:0]
Count[0]
Count[1]
Count[2]
D Q
D Q
D Q
D Q
Count[3]
Countbar[3]
clk
Countbar[0]
Countbar[1]
Countbar[2]
15
16
C2
0
0
1
1
0
0
1
1
C1
0
1
0
1
0
1
0
1
N3
0
0
0
1
1
1
1
0
N2
0
1
1
0
0
1
1
0
N1
1
0
1
0
1
0
1
0
C3
N1
C1 0
N2
C1 1
C2
C2
C3
N3
C1 0
C2
C1
N1 := C1
D Q
N2 := C1 C2 + C1 C2
:= C1 xor C2
C3
C2
D Q
C3
D Q
CLK
N3 := C1 C2 C3 + C1 C3 + C2 C3
:= C1 C2 C3 + (C1 + C2 ) C3
:= (C1 C2) xor C3
From [Katz05]
L5: 6.111 Spring 2006
17
7 P
10 T 163
15
2 CLK RCO
6
5
4
3
D
C
B
A
LOAD
CLR
QD
QC
QB
QA
11
12
13
14
74163 Synchronous
4-Bit Upcounter
18
6
5
4
3
D
C
B
A
LOAD
CLR
QD
QC
QB
QA
11
12
13
14
assign count = Q;
assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T;
endmodule
7 P
10 T 163
15
2 CLK RCO
RCO gated
by T input
19
Simulation
20
Output Transitions
21
VDD
T
QA QB QC QD
163
bits 4-7
CL LD
RCO
DA DB DC DD
bits 8-11
T
QA QB QC QD
163
CL LD
RCO
DA DB DC DD
QA QB QC QD
163
CL LD
RCO
DA DB DC DD
VDD
CLK
22
1 1 1 1
T
QA QB QC QD
163
CL LD
RCO
0 0 0 0
0 1 1 1
T
QA QB QC QD
163
CL LD
DA DB DC DD
RCO
QA QB QC QD
163
CL LD
DA DB DC DD
RCO
DA DB DC DD
VDD
CLK
Problem at 8b11110000: one of the RCOs is now stuck high for 16 cycles!
VDD
0 0 0 0
T
QA QB QC QD
163
CL LD
RCO
DA DB DC DD
0 0 0 0
1 1 1 1
T
0
P
QA QB QC QD
163
CL LD
RCO
DA DB DC DD
QA QB QC QD
163
CL LD
RCO
DA DB DC DD
VDD
CLK
L5: 6.111 Spring 2006
23
Master enable
P
RCO
T
CL LD
QA QB QC QD
DA DB DC DD
QA QB QC QD
RCO
T
CL LD
DA DB DC DD
assign RCO = Q[3] & Q[2] & Q[1] & Q[0] & T;
24
Summary
25