Professional Documents
Culture Documents
High-Frequency Laminate
Instead of FR-4?
by John Coonrod
16
22
38
June 2011
PCB MATERIALS
10
Electronics Materials
olv
ent-fre
Production
Technology
ADEPT
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June2011
2011The
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3
June
introduction
new advanced
PCB MATERIALS
June 2011
contents
Volume 1
Number 2
the definitive
interactive magazine
dedicated to the
global PCb industry
www.pcb007.com
10
Featurespcb materials
articles
46 Repeat Defects
by Steven Williams
by Karl H. Dietz
56 Microvia Separation
by Paul Reid
66 China
by Barry Matties
Extras
News
64 Events Calendar
summary
the way i see it
column
Onshoring
Can We Bring PCBs
Back from China?
by Ray Rasmussen
I-Connect007
TI
TE
TA
PA
ONS
NY
CHNOLOGY
www.christopherweb.com
714.979.7500
short
Should You
Be Using a
High-Frequency
Laminate
Instead of FR-4?
by John Coonrod
Market Development Engineer
Advanced Circuit Materials Division
Rogers Corp.
summary
They may be reliable and affordable, but
there are several reasons why epoxy-based
FR-4 circuit board materials are not the
answer for every circuit, especially for a wide
range of high-frequency designs.
Figure 1. Insertion loss comparisons for microstrip circuits using different materials.
Figure 1 shows a comparison of insertion loss
for simple microstrip circuits made on different
materials of the same thickness.
Stable impedance is important to many
designs, and this is another area where FR-4
and high-frequency laminates can deliver
much different results. Stable impedance
depends on maintaining a stable dielectric
constant (Dk) across the length and width of
a substrate, including as temperature changes.
While they are low in cost, FR-4 materials can
suffer relatively wide variations in Dk across
the length and width of a circuit board, and
with temperature. This can make it impossible,
for example, to achieve flat amplitude response
with frequency in an amplifier. High-frequency
laminates, on the other hand, provide a
Dk that remains constant across the length
11
Figure 2. TCDk curves for several high-frequency laminates as well as FR-4 (Epoxy/WG).
it to about 40 ppm/C for high-frequency
laminates, a much smaller number resulting
in much less variations with temperature. If
a circuit must work with little variation over
a wide temperature range, a high-frequency
laminate is probably a better choice than
FR-4. Comparisons of different circuit
materials are shown in Figure 2, regarding
TCDk.
Sometimes, the very value of a circuit
boards Dk can play an important part
in choosing a particular material. In a
wavelength-dependent circuit, such as an
RF or microwave design, the value of the
dielectric constant will impact the size of
the circuits transmission lines, and thus
the size of the circuit. Simply put, circuitboard materials with higher Dk values can
yield smaller circuits. If the size of a circuit is
important, then the value of the Dk should
be part of the decision process in choosing
a circuit-board material. FR-4 typically has
12
Figure 3. Example of possible circuit size reduction due to using a substrate with a higher dielectric
constant.
What is the best way to decide if your
project might work better with a highfrequency laminate than with FR-4? Size up
the electrical and mechanical requirements
for the job, and see how they might be
handled, first by FR-4 and then using a highfrequency laminate. For ease of comparison,
data sheets are readily available for both
types of circuit board materials and provide
the key facts on electrical and mechanical
parameters and tolerances. If the mechanical
and electrical variations of FR-4 are too wide
for your application, consider paying a bit
more for a high-frequency laminate, but with
much improved performance and reliability.
In the end, the higher yields from using a
dielectric material with tighter manufacturing
tolerances, such as RO4000 thermoset
substrates, might even mean lower production
costs than when using FR-4. PCB
14
www.realtimewith.com
15
short
Thin
Laminates:
Buried Capacitance
or What?
by Istvan Novak
Oracle
summary
After the heated debate about the proper
selection of bypass capacitors, probably
the next-most controversial topic is thin
laminates. Are they really beneficial? Do we
really need them? Can thin laminates help
us eliminate many of the high-frequency
bypass capacitors were accustomed to
using? Lets look at the electrical properties
of thin laminates.
Figure 2: We can get more static capacitance between power and ground planes by placing them
next to each other, without a signal layer in between.
ground layer pair gives us capacitance buried
in the stackup; we get more capacitance as we
use thinner laminates and/or higher dielectric
constants. A one-inch square power-ground
pair of the popular 50 um (2-mil) buried
capacitance laminate produces approximately
450 pF of capacitance. If we double the
dielectric thickness, the capacitance goes down
by a factor of two; if we cut the dielectric
thickness in half, the capacitance doubles.
A simple stackup choice, as shown in
Figure 2, gives us the opportunity to increase
the amount of capacitance: by placing the
power and ground layers next to each other,
without a signal layer in between, we can place
the plane layers much closer and we get more
capacitance. When we have a signal layer
between power and ground, the minimum
separation is limited by how narrow traces we
can etch reliably. The closer we put the planes,
the narrower traces we would need to use to
maintain our impedance target.
For 50-ohm traces and assuming regular
materials and processes, the plane-to-plane
separation is limited to about 10 mils (250 um)
or more. In contrast, if we pair up the power
and ground layers, we can put the layers much
closer, limited only by the risk of shorting due
to finite surface roughness. Note that Figure 2
shows only part of a multi-layer stackup and
during the definition of a full stackup we need
to take into account various additional factors,
such as symmetry, thickness limitation of the
board, etc.
So if we use thin laminates for power-
17
PCB007.com
For more information on this subject visit us online at: pcb007.com
18
www.realtimewith.com
20
summary
When discussing high-reliability materials
for printed circuit board applications, the
conversation typically gears towards opinions
of reliability: is one material system versus
another better? Other times, its materials
properties that are stressed to imply reliability.
Materials Callouts
One commonly cited document is the
IPC-4101C Specification for Base Materials
for Rigid and Multilayer Printed Boards. This
standard creates slash sheets, or silos, to
combine like materials based on meeting
product or performance characteristics such
as resin type or a minimum Glass Transition
(Tg) rating. In recent years, new slash sheets
have been created to address materials capable
for lead-free assembly that incorporates Glass
Decomposition Temperature (Td).
For purposes of this discussion, we will
focus on these lead-free capable materials.
22
23
www.usamicrocraft.com
Test results
As the charts display (Figure 2), there is a
significant change in performance by changing
video interview
www.realtimewith.com
27
summary
In technology advancement, timing is
everything. If you wait to balance your
investment against a perceived advantage
of being on the cutting edge, you may
miss out. Time never stands still. Is there
a perfect time to jump, or, are the only
choices early or late?
30
video interview
www.realtimewith.com
31
article
by Barry Olney
In-Circuit Design Pty Ltd, Australia
summary
This second and last part in a series examining
PCB Design Techniques will look at the
comparison of DDR2 to DDR3; DDR3 design
guidelines; pre-layout analysis; critical
placement; an example of design rules; and
finally, the post-layout analysis.
DDR2/DDR3 Comparison
DDR2
DDR3
Max Clock Frequency
533/1066
800/1600
ODT Static Dynamic
VDD
1.8V
1.5V (may also be 1.35V)
VTT
0.9V
0.75V
Vref
0.9V
0.75V
Input thresholds
0.9V
0.75V
Match Addr/CMD/CTRL to CLK tightly
yes
yes
Match DQ/DMO/DSQ tightly
yes
yes
Match DQS to clock loosely
yes
not required
Table 1.
32
In general, try to keep the SDRAM as close as possible to the controller, but bear in
mind that sometimes it will not be not possible because of other physical constraints.
arriving at components on the DIMM/PCB,
and must meet the timing parameter between
the memory clock and DQS defined as tDQSS
of 0.25 tCK.
The design process can be simplified
using the new levelling feature of DDR3 and
controller ICs. The fly-by daisy chain topology
increases the complexity of the data path and
controller design to achieve levelling, but also
greatly improves performance and eases board
layout for DDR3.
DDR3 Design Guidelines
Critical Constraints:
Clock nets, DQ (data) and DQS (strobes)
are routed differentially. 4.5 max length
+/- 25MIL
Net length from driver to first DIMM or
chip: between 2 to 3 max depending
on load
Net length between DIMMs or chips:
0.5
Net length from last DIMM or Chip to
the VTT Termination: 0.2 to 0.55
All DSQ/DQ (data and data strobe) should
be minimized to reduce the skew within
groups (or lanes) and across groups. 50
MIL within groups and 800 MIL across
groups.
Skew between address nets should be
200MIL. Address and command nets
are daisy chained with a VTT pull-up for
termination.
Other constraints to consider:
DDR3 data nets have dynamic On-Die
Pre-layout Analysis
I cant emphasize enough the importance
of pre-layout analysis. Without which, you
are just relying on luckwhich is not a design
parameter. The pre-layout simulation is used
to predict and eliminate signal integrity issues
early, proactively constraining routing and
optimizing clock, critical signal topologies and
terminations prior to board layout.
As previously mentioned, the value and
placement of the series resistors and VTT pullups for data, address and command signals
depends on the distances between the loads,
number of loads and the stackup of the board
and are best determined by simulation. The
series terminator may not be required if a
single SDRAM is used and the trace length
is shortbut how do you know if you dont
simulate the proposed layout?
In general, try to keep the SDRAM as close
as possible to the controller, but bear in mind
that sometimes it will not be not possible
because of other physical constraints. Also,
if there are two or more SDRAM chips, this
becomes more difficult and requires extended
signal lengths terminators. Now the question
becomes, where should they be placed and
what values should be used?
The series terminator would normally
be placed close to the driver. Surprisingly,
however, in the above case, the signal integrity
33
PCB Design Techniques for DDR, DDR2 & DDR3 (Part 2) continues
order to get a tighter match, although the
JEDEC Spec is 50 MIL. These special high-speed
design rules should be given top priority in the
design rule hierarchy.
Final Post-Layout Analysis
The final post-layout analysis includes a
batch mode simulation of all the nets. This flags
signal integrity, crosstalk and EMI hot spots.
Basically, look carefully through this report to
see any issues that may have to be dealt with.
Figure 2: In this design, signal integrity will be
better if the series terminator is placed 4.5 away
from the driver.
was much better with a long distance (4.5
inches) away from the driver, and then the
signal split through two series resistors and into
each bank of DDR2 SDRAM. This is unusual,
but demonstrates the importance of simulation
in order to achieve the best possible outcome.
By the way, this design ran at full rate with no
rework required.
Placement
If you have completed the pre-layout
analysis, then placement is a matter of following
the constraints determined for length and
placement rules. Series terminators are normally
placed in RESNET 1206 (4 resistor packages) or
0402 on the bottom of the board, as the top is
typically taken up by large active devices.
Decaps should be placed directly beneath
the devices where possible, using 20 MIL
traces connected to the supply pins to reduce
inductance. It is sometimes possible to use the
vias coming down from fine pitch BGA supply
pins as one pin for the 0402 Decap and routing
the other to ground.
Matched Length and Differential
Pair Routing
Setting up the design rules is a little tedious in
any PCB tool, but, once done on the first design,
you can export them into the next design to save
time. Below (Table 2) is an example of DDR2
High-Speed Design Rules for Altium Designer.
When possible, I normally reduce the
tolerance within Data Lanes 0-3 to 25 MIL in
34
PCB Design Techniques for DDR, DDR2 & DDR3 (Part 2) continues
Rule Name
Rule Type
Scope
Atttribute
Length Length
(InNetClass(Lane0) AND Min Length = 500mil
InNetClass(Lane1) AND Max Length = 1000mil
InNetClass(Lane2) AND
InNetClass(Lane3))
Parallel Segment Parallel Segment All - All
Gap = 4mil
Limit = 500mil
Layer = Same Layer
USB Data and Control Matched Net Lengths InNetClass(USB_length) Tolerance = 100mil
Diff Pair USB Matched Lengths Matched Net Lengths InDifferentialPair (USB) Tolerance = 25mil
Diff Pair Matched Lengths Matched Net Lengths (InDifferentialPairClass Tolerance = 25mil
(All Differential Pairs))
DDR CLK Matched Lengths Matched Net Lengths InDifferentialPair Tolerance = 25mil
(DDR_MCK)
DDR2 CTL Matched Net Lengths InNetClass(DDR2_CTL) Tolerance = 200mil
DDR2 Addr Matched Net Lengths InNetClass(DDR2_Addr) Tolerance = 200mil
Lane3 Matched Net Lengths InNetClass(Lane3) Tolerance = 50mil
Lane2 Matched Net Lengths InNetClass(Lane2) Tolerance = 50mil
Lane1 Matched Net Lengths InNetClass(Lane1) Tolerance = 50mil
Lane0 Matched Net Lengths InNetClass(Lane0) Tolerance = 50mil
All Lanes Matched Net Lengths (InNetClass(Lane0) AND Tolerance = 500mil
InNetClass(Lane1) AND
InNetClass(Lane2) AND
InNetClass(Lane3))
Table 2.
issue then different routing strategies can be
tried to eliminate the problem. EMC can be
measured, during the design process, to FCC,
CISPR, VCCI Class A & B standardthis alone
saves multiple iterations of a design.
All critical high-speed signals should be
individually checked. Signal flight times need
to be within spec, and eye diagrams need to
have eyes wide open.
By simulating during the design process,
you can be assured that your PCB layout will
be of the highest quality and will pass the
relevant EMC testssaving you time, money
and frustration for a fraction of the cost of
board iterations and multiple compliancy
testing. Plus, the simulation can be done
before the design is finalized (before Gerber
output or even earlier in the design process) to
further reduce production time and costs. PCB
36
References:
1. Advanced Design for SMT Barry Olney,
In-Circuit Design Pty Ltd.
2. JEDEC Specifications JESD 79F, JESD792E & JESD79-3D.
3. Altera Board Layout Guidelines, EMI_
Plan_Board.
summary
point of view
column
Re-shoring Drivers
Increasing transportation and fuel costs
Higher foreign wages
IP/counterfeiting concerns
Reduction of pipeline inventory for JIT
Localizing manufacturing near R&D
facilities
Regulatory compliance risk
Design and delivery flexibility
Political and infrastructure stability
Improved U.S. competitiveness through
Lean
Higher reject rates/quality
Product liability
Is There Hope?
Some encouraging trends do give us hope.
The U.S. has dropped from number one to
number three in the world ranking of GDP
from services over the last decade, and we have
seen a 26% drop from 2008 to 2009 in dollars
imported (2008 was a staggering $2.1 trillion).
The key to both preserving the manufacturing
business that we still have (on-shoring), and
bringing lost manufacturing jobs back to
America (re-shoring), is going to hinge on the
ability of domestic suppliers to become, and
remain, globally competitive.
So, does America need manufacturing?
Hell, yeah! It is my hope that, as a nation,
we can collectively take the steps to preserve
manufacturing in America. However, in what
may very well be our last chance, will America
once again regain its manufacturing homefield advantage in todays global environment?
I dont know, but to use another sports
metaphor, the ball is clearly in our court. PCB
Steven Williams is a 35-year
veteran in the electronics
industry and an authority on
manufacturing and management.
He is currently the commodity
manager for a large global EMS
provider, a distinguished faculty
member at several Universities and author of
the book Survival Is Not Mandatory: 10 Things
Every CEO Should Know About Lean
(www.survivalisnotmandatory.com).
r
ei
nf
or
ced,Ful
l
yFor
mabl
e
article
43
44
summary
tech talk
column
Repeat Defects
by Karl H. Dietz
In printed wiring
board fabrication,
random defects and
so-called repeat (or
repetitive) defects may
be seen on several
panels or plague an
entire production run.
These repeat defects
are characterized by
a distinct pattern. In
some cases, the defects
are always in the
same location on the
panel. In other cases,
the defects may be
noticed on a narrow
strip on the panel in
machine direction
of the conveyorized
spray process
modules. Or, the
repeat defect pattern
is one where two defects always appear at the
same distance from each other in machine
direction; however, the absolute position of
the two defects on the panel may vary, while
the transverse direction location of the two
defects pretty much stays the same. Then there
are repeat defects that we would refer to as
pseudo repeat defects, not because they did
not fit the description of repeating defects that
originate from the same problem source, but
because they might appear on some panels,
but not on all; or, they might show up for a
while and then disappear.
To identify repeat defects by location, we
used a clear polyester foil overlaid on top of
the AOI inspected defective panel that bore
the defect ink identification marks of the
AOI. We then circled the defect locations on
46
48
49
short
summary
the lean mean pcb specialist
column
Part 2:
Common Questions
by Dale Smith
Here are a few common reasons cited by companies who do not implement Lean:
In General:
1. We are a small company. We dont have the resources that bigger companies have and we cant
afford it.
2. Were too busy. We dont have time to make changes or to train.
3. We dont have highly skilled factory operators. We have a hard time just getting them to follow
procedures, and you want us to empower them?
4. Fear factor. We are afraid to make changes; we dont want to make things worse.
5. We dont know how to implement. Where do we begin?
6. We would consider asking for help, but outside instructors dont understand our business.
Specific to the PCB industry:
1. We manufacture a custom product. Its different all the time.
2. We manufacture many different product types, with varying numbers of process steps.
3. Our product is highly complex and technical.
4. We have product that requires a flow back to a previous operation.
5. We only build prototypes. A part number may only be manufactured one time.
6. We have many new part numbers that we have never built before.
7. We build prototypes and volume production quantities in the same facility; therefore, there is a
demand conflict. The prototype work needs to be processed immediately, causing the
production work to suffer delivery issues (or vice-versa).
8. We do not have much automated equipment.
There are more, but quite frankly, they too
are just excuses. Lean Manufacturing is about
removing waste. Removing waste is a good
thing no matter what is being produced! You
can Lean Out your garage or basement. Have
you ever looked for tools that you know you
own, but cant find? A half-hour job ends up
taking all afternoon because you couldnt find
the tools. What a waste of time! You probably
could have completed several more tasks in
50
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55
short
summary
reid on reliability
column
Microvia
Separation
by Paul Reid
PWB Interconnect Solutions
Microvias are
Microvias are
best described as
very small. As a
small blind vias.
means of comparison
They usually have
I have fine hair
a diameter of .004
which is rather thin,
to .006 or less,
measuring about
and aspect ratios
.002. Two or three
are frequently in
of my hairs would
the range of, but by
fit side by side inside
no means limited
a microvia. Surface
to, between 1:1
tension, viscosity,
and 3:1. Although
wetting and the small
the microvia has a
size of the opening
relatively modest
makes it difficult for
aspect ratio, as
fresh chemistries to
compared to HDI
get into a microvia
Figure 1: Anatomy of a microvia.
boards with plated
and for spent
through vias, they are a challenge to fabricate,
chemistries to be replaced.
mostly due their small size.
For the purpose of this article, and
Of all the interconnect structures, wellbased on reliability testing, we can place
made microvias consistently outperform all
microvias into two distinct groups: simple and
other interconnect types based on thermal
compound. Simple structures are microvias
cycle testing. At the same time, poorly
that are not stacked on top of either other
fabricated microvias fail catastrophically in
microvias or buried vias. Compound microvias
assembly and in the end-use environment.
are defined as those microvias that are directly
Conventional test methods like solder float
stacked on top of other microvias or buried
and thermal cycle testing at 150C have been
vias. Simple microvias may span one or more
known to produce false-positive results on
dielectric layers, but tend to be floating with
marginal microvias that subsequently failed in
dielectric material directly below. Stacked
assembly.
microvia connect directly on top of other
The anatomy of a microvia includes a
copper interconnections.
capture pad through which a hole is drilled
Usually, we find a simple microvia between
or ablated, the target pad at which the hole
other interconnect structures like plated
terminates and the sides of the hole walls, or
through holes (PTHs). During a thermal
barrel of the microvia. The microvia may be
excursion, if a microvia is between two
open or filled with epoxy or copper, and may
adjacent PTHs, the PTHs will act like rivets,
or may not have a copper cap. Usually the
constraining the z-axis expansion. Dielectric
microvia is penetrating approximately .003
material will expand, bulging out between
or .004 of the dielectric. Microvias are
PTHs, pushing the microvia structure upward
frequently found in sequential lamination
(or down) as it floats on a bed of expanding
applications.
dielectric. The microvia, because of its
56
IPC international
conference on Flexible CircuiTs
Workshops June 21
Technical Conference June 2223
Minneapolis, Minn.
Participate in the growth of the flex circuit industry!
Discover flex opportunities and challenges as seen by Prismark Partners
Hear from RIM, Delphi, Mayo Clinic and Lockheed Martin on their requirements for flex boards
Learn the latest developments in flex materials from DuPont, Arlon and Tapco
Discover best methods for solving processing issues
Receive performance reliability data from Rockwell Collins
Learn what the latest IPC studies reveals about the flex market
Special Considerations in Flex/Rigid Flex,instructor Greg Bartlett, general manager, Vulcan Flex
Circuit Corp.
Design for Manufacture: Options for Optimum Manufacturing Reliability, instructor Tom
Gardeski, president, Gemini Sciences, LLC
Test Temperature
150C
170C
190C
210C
220C
1000
789
464
76
44
news
Top
Ten
Most-Read News Highlights
from PCB007 this Month
Black Pad & Brittle
APEX Honors Best
a
c
Fracture: Controlling the
Industry Posters,
ENIG Process
Ground?
62
Competition Winners
Celebrating the best of electronic interconnection research being conducted by both industry
leaders and academia, IPC announced the 2011
Best Industry Posters, and the winners of the
IPC Academic Poster Competition at IPC APEX
Expo, held April 12-14, 2011, in Las Vegas,
Nevada.
and Safety
I-Connect007 Launches
g
Free Flex Video Series
I-Connect007 has launched the Flexible
Circuit Technology Online Training Video
Series. Divided into nine sessions, this firstof-its-kind video series is a companion to Joe
Fjelstads exhaustive book, Flexible Circuits
Technology. Welcome to learning on demand,
on your schedule!
EIPC Seminar
Famous
63
calendar
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Competitiveness
June 15 - 16, 2011
Washington, D.C.
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June 21 - 23, 2011
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RTLS Europe 2011
June 21 - 22, 2011
Munich, Germany
64
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IPC Summit on
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Combining Capitol Hill Day with a conference
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Washington, D.C. | June 1516, 2011
THE IPC SUMMIT ON AMERICAN COMPETITIVENESS combines informative presentations, legislative and regulatory briefings and key
lobbying visits with members of Congress to discuss critical issues that impact the U.S. electronics industrys ability to compete globally.
summary
the sales cycle
column
China
by Barry Matties
66
china continues
EDITORIAL:
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cover: Mike Radogna, BRYSON MATTIES
The PCB Magazine is published by BR Publishing, Inc., PO Box 50, Seaside, OR 97138
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Ad Index
atg Luther & Maelzer GmbH..... 53
Atotech.................................. 1, 2
Brkle North America................ 47
CA Picard.................................. 37
Christopher Associates............... 7
Fein-Line Assoc......................... 51
I-Connect007..................... 59, 61
Integral Technologies............... 29
IPC..................................... 57, 65
Maskless Lithography................ 21
Microcraft................................. 25
Microtek Labs........................... 67
OEM Press Systems................... 45
OMG Electronic Chemicals....... 19
Rogers Corp............................. 13
Semblant................................... 5
Taiyo-America........................... 39
Technica, USA.......................... 35
Ventec...................................... 41
Next Month in
The PCB Magazine
Its all about imaging in the July issue of
The PCB Magazine, with feature articles and
video from industry insiders including Gordon
Quinn, writing on LED imaging technology;
Maskless Lithography; and Karl Dietzs Tech
Talk, presenting an introduction to PCB
Imaging.
Our monthly columnists have plenty to
say, about imaging and a few other things, too.
Dale Smith, of DAS Flex Circuit Consultant,
continues with his column, The Lean Mean PCB
Specialist, focusing on how to implement Lean
in a printed circuit board shop. In July, Smith
will address the question of how to understand
customer values in part three of his five-part
series. Well have 35-year electronics industry
veteran, Steven Williams, and his Point of View
column that takes on the impact of unions
on American manufacturing. Of course, Ray
Rasmussen and Barry Matties bookend the issue
with their unique perspectives in The Way I See
It and The Sales Cycle.
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See you in July!
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