ECE 431 Digital Circuit Design

Chapter 6 MOS Inverters: Switching

Characteristics and Interconnect
Effects
Lecture given by Qiliang Li

6.1 Introduction

Cload =C gd ,n +C gd , p +C db,n +C db, p +C int +C g

Simplified first-stage CMOS inverter

6.2 Delay-Time Definitions

Input-to-output signal delay times

V50%

1
= (VOL + VOH )
2

PHL = t1 t0
PLH = t3 t2
Average propagation delay

P =

PHL + PLH
2

Output signal fall and rise times

fall = tB t A

rise = tD tC

V10% = VOL + 0.1 (VOH VOL )

V90% = VOL + 0.9 (VOH VOL )

6.3 Calculation of Delay Times

Using current X time = Charges = capacitance X voltage

PHL

Cload VHL Cload (VOH V50% )

=
=
I avg ,HL
I avg ,HL

PLH

Cload VLH Cload (V50% VOL )

=
=
I avg ,LH
I avg ,LH

I avg ,HL

1
= [iC (Vin = VOH ,Vout = VOH ) + iC (Vin = VOH ,Vout = V50% )]
2

I avg ,HL

1
= [iC (Vin = VOL ,Vout = V50% ) + iC (Vin = VOL ,Vout = VOL )]
2

For rising-input case

i.e., falling output -> tPHL

dVout
Cload
= iC = iD , p iD ,n
dt
dVout
For Vin = VOH
Cload
= iD , n
dt
iD , n

kn
2
= (VOH VT ,n )
2

Time between t0 and t1

t =t1'

t = t0

Vout =VOH VT , n

dt = Cload

Vout =VOH

2Cload
=
kn (VOH VT ,n ) 2

Vout =VOH VT , n

Vout =VOH

2CloadVT ,n
t t0 =
2
kn (VOH VT ,n )
'
1

1
dVout

i
D ,n
dVout

(6.17)

nMOS is in saturation

Time between t1 and t1

iD , n

kn
2
2(VOH VT ,n )Vout Vout
=
2

nMOS is in linear region

1
t =t1' dt = Cload Vout =VOH VT ,n iD,n dVout

t =t1

Vout =V50%

= 2Cload
2
Vout =VOH VT , n k 2(V
V
V
V
)

OH
T ,n
out
out
n
Vout =V50%

dVout

2(VOH VT ,n ) V50%
Cload
ln(
)
t1 t =
kn (VOH VT ,n )
V50%
'
1

(6.21)

(6.3 Calculation of Delay Times continue )

In summary:
PHL

2VT ,n
4(VOH VT ,n )
Cload
=
+ ln(
1)]
[
kn (VOH VT ,n ) VOH VT ,n
VOH + VT ,n

PHL

2VT ,n
4(VDD VT ,n )
Cload
=
+ ln(
1)]
[
kn (VDD VT ,n ) VDD VT ,n
VDD

(6.3 Calculation of Delay Times continue )

Example 6.1 in page 225

Example 6.2 fall time in page 226

(use VT,n = 1 V)

(6.3 Calculation of Delay Times continue )

Similarly for Charging-up: Vin from VOH -> VOL

nMOS is cut off and pMOS is turned on.

PLH

2 | VT , p |
4(VDD | VT , p |)
Cload
=
+ ln(
1)]
[
k p (VDD | VT , p |) VDD | VT , p |
VDD

To achieve balanced propagation delays:

VT,n = VT,p

What about the delays in other type

inverter, e.g., depletion load inverter?
If the input is not ideal: tr and tf are not
zero

PHL ( actual ) =

2
PHL ( step _ input )

PLH ( actual ) =

2
PLH ( step _ input )

+( )
2

+(

f
2

6.4 Inverter Design with Delay Constraints

Constraints: Delay, noise margins, logic threshold, area and power dissipation

2VT ,n
4(V V )
W
Cload
)n = *
[
+ ln( DD T ,n 1)]
L
PHL nCox (VDD VT ,n ) VDD VT ,n
VDD

2 | VT , p |
4(V | VT , p |)
W
Cload
)p = *
[
+ ln( DD
1)]
PLH pCox (VDD | VT , p |) VDD | VT , p |
L
VDD

Example 6.3 in page 232

Limit of delay

Cload = Cgd ,n (Wn ) + C gd , p (W p ) + Cdb,n (Wn ) + Cdb, p (W p ) + Cint + C g

Cload = 0 + nWn + pW p
0 = 2 Ddrain (C jsw,n K eq ,n + C jsw, p K eq , p ) + Cint + Cg

n = K eq ,n (C j 0,n Ddrain + 2C jsw,n )

p = K eq , p (C j 0, p Ddrain + 2C jsw, p )

 PHL

PLH

2VT ,n
4(VDD VT ,n )
0 + nWn + pW p
Ln
[

ln(
+
1)]
=
C (V V ) V V
W
V
n
DD
T ,n
DD
n ox DD T ,n

0 + nWn + pW p

2 | VT , p |
4(VDD | VT , p |)
Lp

[
+ ln(
1)]

C (V | V |) V | V |
W
V
p
T ,p
DD
T ,p
DD

p ox DD

+ ( n + R p )Wn
0 + nWn + pW p

= n 0
W
W
n
n

PHL = n

PHL

Limits of delay: as W and W are

increasing (while R is kept unchanged)

0 + ( n + p )W p
R

= n
Wp

, where

Wp

R =
Wn

lim it
PHL
= n ( n + R p )
n
lim it
PLH = p ( + p )

Example 6.4 in page 237 effect of channel width

Limit of delay

CMOS Ring Oscillator Circuit

Identical CMOS inverters

T = 6 P
1
1
f = =
T 2 n P
1
P =
2n f

6.5 Estimation of Interconnect Parasitics

Different models to estimate
depending on the length of
interconnection lines

rise ( fall ) < 2.5 ( )

Transmission-line modeling

either Transmission-line
2.5 ( ) < rise ( fall ) < 5 ( ) modeling or lumped

modeling
l
rise ( fall ) > 5 ( )
lumped modeling

L: length of interconnect, v: propagation speed

Capacitive or RC modeling

Variation of the fringing field factor with the interconnect geometry

Interconnect Capacitance Estimation

w t
2

2
C =
+

2h
2h 2h

ln1 +
2
+
+

t
t
t

1 0.0543

w
2h

C = +
+ 1.47
h

2h
2
2
h
h

ln1 +
+
+ 2

t
t
t

For w>= t/2

For w< t/2

where p: material resistivity, l, w and t: length, width and thickness

Capacitance of an interconnect
line with is coupled with two
other parallel lines on both sides.

Cross-sectional view of a double-metal CMOS structure,

showing capacitances between various layers

Interconnect Resistance Estimation

total resistance

Sheet resistivity

Rwire

l
l
=
= Rsheet ( )
wt
w

Rsheet =

where p: material resistivity, l, w and t: length, width and thickness

6.6 Calculation of Interconnect Delay

RC Delay Models

Vout (t ) = VDD (1 exp(

t
))
RC

V50% = VDD (1 exp(

PLH 0.69 RC

PLH
RC

))

The Elmore Delay

Di = C j
j =1

for _ all
kPij

Example 6.5
Poly-Si interconnect with length 1000 m, width 4 m, what is the delay due to this interconnect?
R
C

10: R/10, C/10

R=7.5 k ohm, C = 356 fF
Use Lumped RC model: tPLH = tPHL = 0.69 * RC = 1.9 ns
Use Distrubuted RC model:
j
10

DN = C j Rk = RC (
j =1

k =1

N +1
) RC / 2
2N

500 um
500 um
2 um

6 um

6.7 Switching Power Dissipation of CMOS Inverters

Pavg

1
=
T

2
v (t ) i (t )dt = Cload VDD
f