Fault Simulation

Fault Simulation Techniques

y Basics
y Faultsimulationalgorithms
Serial
Parallel
Deductive
Concurrent
Differential

y RandomFaultSampling

Wh t iis ffault
What
lt simulation?
i l ti ?
Circuit
Ci
i
Testpatterns
Faultmodel

FFault
lt
Simulator

Faultyoutputs
Faulty
outputs
Undetectedfaults
Faultcoverage

Time Complexity
Proportional to
n: Circuit size, number of logic gates
p: Number of test patterns
f : Number of modeled faults

Complexity=P*F*G~O(G3)withsinglesafaults
Complexityishigherthanlogicsimulation,O(G2),butismuchlower
thantestpatterngeneration.
h
Inreality,thecomplexityismuchlowerduetofaultdroppingand
advancedtechniques.

Definitions
y FaultSpecification
y FaultDropping

y FaultInsertion

Definingasetofmodeledfaultsand
performing fault collapsing
performingfaultcollapsing
The removal of detected, hyperactive and
hypertrophic faults during the run (Inverseof
fault insertion)
faultinsertion)
Selectingasubsetoffaultstobesimulated
andcreatinganetlistwiththesefaults

Propagationoffaulteffects
Afaultcanbetermeddetectediff:
y Itisactivatedbythetestvector
y Itsfaultyvalueistransferredfromtheeffectednet(internal)ontothe

p
primaryoutputpins
y
p p

F lt Dropping
Fault
D
i g
y Numberoffaultsrequiringsimulationdecreasesastherunproceeds

becausethemaingoalistodeterminethefaultcoverageofagiven
because
the main goal is to determine the fault coverage of a given
testpattern
y Detectedfaultscanbeimmediatelyremoved,drasticallyreducingthe

averagelistlengthandthusthecomputingload
average
list length and thus the computing load
y Some faults must be removed in any case for the sake of efficiency. These belong
to two main classes: hyperactive and hypertrophic faults
y Hypertrophic
H
t
hi ffault
lt causes the
h networkk to remain
i iin an unknown
k
status on almost
l

all the nodes

e.g., a fault on a reset line
It cannott bbe ddetected,
t t d andd wastes
t CPU ti
time andd memory.
y Hyperactive fault produces very high activity, e.g., a group of elements starts to
oscillate. It, too, is undetectable and very CPU-time consuming

Referred from S.Gai, P.L.Montessoro, Fabio Somenzi, MOZART, a Concurrent Multilevel Simulator, IEEE Transactions on Computer-Aided Design,
vol. 7, no. 9, September 1988, pp. 1005-1016

Fault Injection

Fault Simulator Flow

Logic simulation on both

good
d (fault-free)
(f lt f ) and
d
faulty circuits

Need for Fault Simulation

NeedforFaultSimulation
y Toevaluatethequalityoftestset;intermsoffaultcoverage
y ToincorporateintoATPGfortestgeneration
y Toconstructfaultdictionary

Serial Fault Simulation

y First,performfaultfreelogicsimulationontheoriginalcircuit
Good(faultfree)response
G d (f lt f )
y Foreachfault,performfaultinjectionandsimulatetheerrornetlist
Faultycircuitresponse
Test vectors

Fault-free circuit

Comparator

f1 detected?

Comparator

f2 detected?

Comparator

fn detected?

Circuit with fault f1

Circuit with fault f2

Circuit with fault fn

Each one of these computations are done one by one sequentially

Example

Parallel Fault Simulation

y Goodandfaultyckts,say
Good and faulty ckts say W
W aresimulatedtogether
are simulated together
y AsetofFfaultsrequire[F/W]passes
y Compiledcodemethod;bestwithtwostates(0,1)
l d d
h d b
h
( )
y Exploitsinherentbitparallelismoflogicoperationsoncomputer
y
y
y
y

words
S
Storage:onewordperlinefortwostatesimulation
d
li f
i l i
Multipasssimulation:Eachpasssimulatesw1 newfaults,wherew is
themachinewordlength
S
Speedupoverserialmethod~w1
d
i l
h d
1
NotsuitableforcircuitswithtimingcriticalandnonBooleanlogic

Parallel Fault Sim.

Sim Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 22: circuit
i it with
ith f s-a-11
1

1 1
1

a
b

1 1 1

1 0 1

c s-a-0 detected

ss-a-0
a0

g
0

0
s-a-1

Deductive Fault Simulation

y Onepasssimulation
y Eachlinek
Each line k containsalistL
contains a list Lk offaultsdetectableonk
of faults detectable on k
y POfaultlistsprovidedetectiondata

Some Simple Gates

Gate

AND

OR

Input

output

o/p fault list

o/pfaultlist

{La Lb }UZ1

{La Lb' }UZ1

{ La' Lb }UZ
{L
} U Z1

{La ULb } Z0

{LaULb } Z1

{La' Lb }UZ0

{ La Lb' }UZ
{L
} U Z0

{La Lb }UZ0

Deductive Fault Sim. Example

p
Notation

a
b

1
1
{b0}

Lk is fault list for line k

kn is s-a-n fault on line k
Le = La U Lc U {e0}
= {a0 , b0 , c0 , e0}

{ 0}
{a
{b0 , c0}
c
d
{b0 , d0}

{b0 , d0 , f1}

Lg = (Le Lf ) U {g0}
= {a0 , c0 , e0 , g0}
Faults detected by
the input vector

Concurrent Fault Simulation

y Eventdrivensimulationoffaultfreecircuitandonlythosepartsofthe
y

y
y
y

faultycircuitthatdifferinsignalstatesfromthefault
faulty
circuit that differ in signal states from the faultfree
freecircuit.
circuit.
Alistpergatecontainingcopiesofthegatefromallfaultycircuitsin
whichthisgatediffers.ListelementcontainsfaultID,gateinputand
outputvaluesandinternalstates,ifany.
Alleventsoffaultfreeandallfaultycircuitsareimplicitlysimulated.
Faultscanbesimulatedinanymodelingstyleordetailsupportedin
truevaluesimulation(offersmostflexibility.)
Fasterthanothermethods,butusesmostmemory.

Some Basic Definitions

y Goodevent
Eventsthathappeningoodcircuit
Events that happen in good circuit
Affectbothgoodgatesandbadgates

y Badevent
Eventsthatoccurinthefaultycircuitofcorrespondingfault
Affectonlybadgates

y Diverge
Additionofnewbadgates
g

y Converge
RemovalofbadgateswhoseI/Osignalsarethesameascorresponding
Removal of bad gates whose I/O signals are the same as corresponding

goodgates

Conc Fault Sim.

Conc.
Sim Example
a0

0
1

a
b

c0

b0

e0

1
0

1
1
1

c
d

1
0

1 0

0
0

a0

1
1

b0

0 1

d0

0 1

f1

1 1

g0

b0

0
1
1

f1

c0

0
1
1

d0

e0
0