Professional Documents
Culture Documents
Preliminary
Features
z
z
z
RT9420 calculates and determines the Li+ battery Stateof-Charge (SOC) according to battery OCV information
and a sophisticated battery voltaic model. The dynamic
voltaic information can effectively emulate the Li+ battery
behavior and determines the SOC.
z
z
z
z
z
z
z
z
Applications
z
z
z
z
z
Smartphones
MP3 Players
Digital Still Cameras
Digital Video Cameras
Handheld and Portable Applications
RT9420
R1
VBAT
R2
R3
System
Processor
VDD
IRQ
ALERT
C1
Li +
Protection
Circuit
QS
TEST
GND
DS9420-P01
October 2012
SDA
SCL
SDA
SCL
C2
www.richtek.com
1
RT9420
Preliminary
Ordering Information
Marking Information
RT9420
06 : Product Code
Package Type
QW : WDFN-8L 2x3 (W-Type)
W : Date Code
06W
Pin Configurations
(TOP VIEW)
1
2
3
4
GND
8
7
6
5
SDA
SCL
QS
ALERT
WDFN-8L 2x3
Pin Name
Pin Function
TEST
VBAT
VDD
4,
9 (Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
ALERT
QS
Quick Sensing Input. Active high to restart the calculation. Pull low to GND
during normal operation.
SCL
SDA
www.richtek.com
2
DS9420-P01
October 2012
RT9420
Preliminary
Function Block Diagram
VDD
I C
Interface
SDA
SCL
Voltaic Gauge
Algorithm
Controller
QS
ALERT
TEST
GND
VBAT
12-bit
ADC
Battery
OCV Model
Operation
12-bit ADC
Controller
I2C Interface
The fuel gauge registers can be accessed through the I2C
Interface.
DS9420-P01
October 2012
www.richtek.com
3
RT9420
Preliminary
z
z
z
(Note 1)
Voltage on TEST Pin Relative to GND -------------------------------------------------------------------------------Voltage on VBAT Pin Relative to GND ------------------------------------------------------------------------------Voltage on All Other Pins Relative to GND -------------------------------------------------------------------------SCL, SDA, QS, ALERT to GND --------------------------------------------------------------------------------------VBAT to GND --------------------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25C
WDFN-8L 2x3 -------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WDFN-8L 2x3, JA --------------------------------------------------------------------------------------------------------WDFN-8L 2x3, JC --------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------
0.3V to 5.5V
0.3V to 5.5V
0.3V to 6V
0.3V to 5.5V
0.3V to 5V
3.17W
31.5C/W
7.5C/W
260C
150C
65C to 150C
(Note 3)
Electrical Characteristics
(2.5V VDD 4.5V, TA = 25C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
22
40
--
0.5
--
--
TA = 0C to 70C
--
TA = 20C to 70C
--
12.5
--
12.5
25
--
25
15
--
--
DC Section
Active Current
IACTIVE
Time-Base Accuracy
tERR
VGERR
RVBAT
SCL, SDA,
QS Input
VDD = 2.5V
Logic-High
1.4
--
--
Logic-Low
--
--
0.5
mV
M
V
VOL_SDA
--
--
0.4
VOL_ALERT
--
--
0.4
IPD
--
0.2
0.4
tSLEEP
(Note 5)
1.75
--
2.5
www.richtek.com
4
DS9420-P01
October 2012
RT9420
Preliminary
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
10
--
400
kHz
1.3
--
--
0.6
--
--
I C Interface
Clock Operating Frequency
fSCL
tBUF
tHD_STA
tLOW
1.3
--
--
0.6
--
--
tSU_STA
0.6
--
--
tHD_DAT
(Note 7, Note 8)
0.2
--
0.9
ms
tSU_DAT
(Note 7)
100
--
tR
20
--
300
ns
tF
20
--
300
ns
tSU_STO
0.6
--
--
tSP
(Note 9)
--
50
ns
(Note 10)
400
--
--
pF
--
--
60
pF
(Note 6)
(Note 6)
CBIN
ns
Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. SDA, SCL = GND; QS, ALERT idle.
Note 5. The RT9420 enter Sleep mode 1.75s to 2.5s after (SCL < VIL) AND (SDA < VIL).
Note 6. fSCL must meet the minimum clock low time plus the rise/fall times.
Note 7. The maximum tHD_DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 8. This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 9. Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 10. CB total capacitance of one bus line in pF.
DS9420-P01
October 2012
www.richtek.com
5
RT9420
Preliminary
C1
1F
Li +
Protection
Circuit
R2
150
RT9420
2 VBAT
VDD 3
5
ALERT
6
QS
1 TEST
R3
4.7k
System
Processor
IRQ
8
SDA
SCL 7
SDA
SCL
GND
4, 9 (Exposed Pad)
C2
10nF
Timing Diagram
SDA
tLOW
tF
tR
tSU_DAT
tF
tHD_STA
tSP
tBUF
tR
SCL
tHD_STA
tHD_DAT
tHIGH
www.richtek.com
6
tSU_STA
tSU_STO
Sr
DS9420-P01
October 2012
RT9420
Preliminary
Typical Operating Characteristics
(TA = 25C, battery is Sanyo UF534553F, unless otherwise specified.)
40
20
30
25
20
70C
25C
20C
15
10
5
15
VBAT = 3V
VBAT = 3.6V
VBAT = 4.3V
10
5
0
-5
-10
-15
-20
VOUT = 3.3V
0
-25
2.5
2.75
3.25
3.5
3.75
4.25
-20
4.5
-5
10
40
55
70
100
10
90
90
80
80
70
70
60
60
50
50
40
-2
40
-2
30
-4
Reference SOC
RT9420 SOC
Error
20
10
0
0
10
12
14
16
18
20
-8
10
-10
-6
-8
-10
10
12
14
Time (h)
80
70
60
50
40
-2
-4
Reference SOC
RT9420 SOC
Error
10
-4
Reference SOC
RT9420 SOC
Error
20
100
20
30
-6
Time (h)
30
SOC (%)
100
SOC (%)
SOC (%)
25
Temperature (C)
-6
-8
-10
0
10
12
Time (h)
Copyright 2012 Richtek Technology Corporation. All rights reserved.
DS9420-P01
October 2012
www.richtek.com
7
35
RT9420
Preliminary
Application Information
Voltaic Gauge Theory and Performance
ALERT Interrupt
www.richtek.com
8
When alert condition occurs, the RT9420 outputs logiclow to the ALERT pin and sets 1 to the [Alert] bit in the
Config register. The only two ways to recover the alert
condition is either writing 0 to clear [Alert] bit or power on
reset. Before the recovery, the [Alert] bit will keep 1 and
the ALERT pin will keep logic-low. It can't recover the alert
condition by entering sleep mode.
Please note that the alert detection function is enable
when power on.
Sleep Mode
RT9420 will enter sleep mode if host pulls low both SDA
and SCL to logic-low at least 2.5s. All operation such as
voltage measurement and SOC calculation are halted and
power consumption is reduced under 3A in sleep mode.
Any rising edge of SDA or SCL will transfer IC back to
active mode immediately.
The other way to enter sleep mode is write [Sleep] bit in
the Config register to 1 through I2C communication, and
the only way to exit sleep mode is to write [Sleep] bit to
logic 0 or power on reset the IC.
Initialization
The RT9420 can be reset by writing an initialization
command to MFA resister. The behavior of initialization is
the same as power on reset.
I2C Register
The RT9420 supports the following 16-bit I2C registers:
VBAT, SOC, Control, Device ID, Config and MFA.
The register writing is valid when all of 16 bits data are
transferred; otherwise, the write data will be ignored. The
valid register addresses are defined in Table 1. Other
remaining addresses are reserved.
DS9420-P01
October 2012
RT9420
Preliminary
Table 1. I2C Register
Address
(Hex)
Register
Read/
Write
Default
(Hex)
02h-03h
VBAT
--
04h-05h
SOC
--
06h-07h
Control
--
08h-09h
Device ID
--
0Ch-0Dh
Config
R/W
AB1Ch
FEh-FFh
MFA
--
Description
VBAT
The VBAT register is a read only register that reports the
measured voltage at VBAT pin. The VBAT is reported in
units of 1.25mV. The first report is made after chip POR
with 250ms delay and then updates 1s periodically. Figure
1 shows the VBAT register format.
MSB-Address 04h
11
2 2
MSB
10
LSB-Address 03h
5
2
2 2
LSB MSB
2 2
MSB
LSB-Address 05h
1
-1
2
2 2
LSB MSB
-2
-3
-4
-5
-6
-7
-8
Unit : 1%
Control
The Control register allows the host processor to send
special commands to the IC (Table2). Valid Control register
write values are listed as follows. All other Control register
values are reserved.
Copyright 2012 Richtek Technology Corporation. All rights reserved.
October 2012
Description
4000h
Quick
Sensing
Device ID
The Device ID register is a read only register that contains
a value indicating the production ID of the RT9420.
Config
The Config register includes the parameter of
compensation, setting of sleep mode and SOCLow
threshold. It also indicates the alert status. The format of
Config is shown in Figure 3.
VGCOMP is the setting to optimize IC performance for
different cell chemistries or temperatures. Contact Richtek
for instructions for optimization. The power on reset value
for VGCOMP is ABh.
Register
0x0C
2
LSB
DS9420-P01
Command
LSB
MSB-Address 04h
Value
0x0D
Bit
7:0
7
6
5
4:0
Description
VGCOMP
Sleep
X (Dont Care)
Alert
SOCLow
www.richtek.com
9
RT9420
Preliminary
[Sleep]
MFA
[Alert]
The [Alert] bit is set by the IC when the alert condition
occurs. The [Alert] bit is cleared by either host writing 0
to clear or a reset condition occurs.
Value
Command
Description
5400h
Initialization
Reset the IC
[SOCLow]
Application Examples
System Configuration
VDD
ALERT
QS
System-Side Location
Connect to GND
Connect to GND
System-Side Location
SOCLow Interrupt
Connect to GND
Connect to GND
Connect to rising-edge
Reset signal
System-Side Location
Power directly from battery
Hardware Quick Sensing
VBAT
Battery
System VDD
Pack+
R1
1k
+
RT9420
2 VBAT
VDD 3
ALERT 5
R2
150
6 QS
1 TEST
SDA 8
SCL 7
GND
4, 9 (Exposed Pad)
System
Processor
IRQ
C1
1F
Protection IC
(Li+/Polymer)
R3
4.7k
SDA
SCL
C2
10nF
Pack-
System GND
www.richtek.com
10
DS9420-P01
October 2012
RT9420
Preliminary
Figure 4 presents a single cell battery-powered system
application. The RT9420 is used on system side and direct
powered from the battery.
The RC filter saves the noise for IC power supply and
voltage measurement on VBAT pin.
To reduce the I-R drop effect, make the connection of VBAT
as close as possible to the battery pack.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
SAddr
W A
CAddr
Data0
Data1
A P
Write Protocol
S
SAddr
A
W A
Data1
CAddr
A Sr SAddr
R A
Data0
N P
Read Protocol
Symbol
S
Description
START bit
SAddr
CAddr
Data
Symbol
Sr
Description
Repeated START
R/W
P
Data
DS9420-P01
October 2012
www.richtek.com
11
RT9420
Preliminary
3.6
Four-Layer PCB
3.0
2.4
1.8
1.2
0.6
0.0
0
25
50
75
100
125
B+
R1
BC2
TEST
VBAT
VDD
GND
1
2
3
4
GND
C1
7
6
5
Connect to GND,
SDA
if not used.
SCL
QS
R3
B+
ALERT
R2
B-
www.richtek.com
12
DS9420-P01
October 2012
RT9420
Preliminary
Outline Dimension
D
D2
E2
SEE DETAIL A
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
0.200
0.300
0.008
0.012
1.900
2.100
0.075
0.083
D2
1.550
1.650
0.061
0.065
2.900
3.100
0.114
0.122
E2
1.650
1.750
0.065
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
DS9420-P01
October 2012
www.richtek.com
13
RT9420
Preliminary
Data
P00
2011/11/21
P01
2012/10/15
Page No.
Item
First edition
All
www.richtek.com
14
Description
Modify
DS9420-P01
October 2012