Bale

ELSEVIER

Electric

Power

Systems

Research

36 (1996)

SYSTEf7lS
RESERRCH

45-55

A digital technique for stator winding protection

synchronous generators

of

T.S. Sidhu, B. Sunga, M.S. Sachdev

Received

27 July

1995

Abstract
This paper describes a digital technique for detecting internal faults in stator windings of synchronous generators. The technique
uses positive- and negative-sequence models of the synchronous generator, and voltages and currents measured at the generator
terminals. It does not need information concerning the machine parameters and is applicable to all types of generators, irrespective
of their size. Fault discrimination
characteristics and a digital algorithm based on the proposed technique are described. The
performance of the proposed technique was evaluated using fault data generated by simulations using an electromagnetic transient
program. EMTDC.
Fault data were also acquired by subjecting a laboratory generator to internal and external faults. Results of
the studies using simulated and experimental data are included in the paper. The results indicate that the proposed technique can
detect faults including open circuits and faults that short-circuit windings of one phase.
Digital

Keywords:

techniques;

Fault

detection;

Synchronous

generators;

1. Introduction
Electric

power

utilities

and

industrial

plants

tradi-

tionally use electromechanical and solid-state relays for

protecting synchronous generators. With the advent of
digital technology, researchersand designershave made
significant progress in developing protection systems
using microprocessors [ 11.Several microprocessor based
algorithms for detecting stator winding faults have been
proposed. Sachdev and Wind [2] developed an algorithm that usesinstantaneous differences between line
and neutral-end

currents

for detecting

phase faults.

The

sum of the instantaneous currents was used to provide

a restraint,

Hope

et al. [3] also used differential

protec-

tion for stator windings. Cross-correlation was used to

compute fundamental frequency phasors of the line-side
and neutral-end currents. The sums and products of
these currents were used in the fault detection algorithm.
Tao and Morrison [4] used the discrete Fourier transform and Walsh functions to calculate the phasors of
the fundamental frequency and third-harmonic volt037%7796:961515.00
SSDf

C 1996 Elsevier

0378-7796(95)01013-D

Science

S.A. All rights

reserved

Stator

winding

protection

ages. They also computed the currents at the neutral

and line sides of the stator windings, A combination of
biased differential protection and ground fault protection

was used to achieve

100% stator

winding

protec-

tion. Dash et al. [5] presented a method which

monitored the presence of the second harmonic in the
field winding to detect system faults. The direction of
negative-sequence power flow at the generator terminal
was used to discriminate internal faults from external
faults. Recently, a number of integrated generator protection systems have been reported in the literature
[668]. These systems USCdigital filters to compute the
phasors of voltages and currents, and apply appropriate
digital algorithms for providing a variety of protection
functions including stator winding protection.
The majority of the previously proposed algorithms
are based on fault detection principles used in their
electromechanical counterparts. These schemes are
known to have poor sensitivity for turn-to-turn faults.
This

paper

describes

the development

of a digital

tech-

nique for detecting internal faults in the windings of

synchronous

generators.

The

technique

uses a simple

generator model and voltages and currents measured at

the generator terminals. Some test results showing the
performance of the technique are included in the paper.

2. The technique
The two-machine
system of Fig. 1 is used to describe
the technique. In Fig. 1, Gx is the generator being
protected and the external network is represented by a
transmission
line. Z,, and an equivalent source Gy.

shown in Fig. 2(a) and (b), respectively. The generator

in this network is represented by a simple model consisting of its positive-sequence
impedance Zgx,, and the
positive-sequence
internal voltage E,, . The Thkvenin
equivalent circuit is shown in Fig. 2(c). The impedance
Z,., shown in Fig. 2(b) and (c), represents the fault
impedance and, depending on the type of fault, the
other sequence network(s).
The incremental voltage
AV,., and the current AZ,, can be expressed as follows:
A Vx, = ( Vx&mmt

- ( YJprc,iu,t

ALI = Vdposrrau,t - UxJprefau,t

2.1. E.xternul fuults
For an external fault at bus Y, The resulting prefault
and postfault positive-sequence
networks
would be as
Relay

(1)
(2)

where ( Vx,)prrf:ault and (Zxl)prefau,t are the positivesequence voltage and current
at bus X prior to
the occurrence
of the fault, and ( Vx,)postf.u,t and
(4 I )postfault are the positive-sequence voltage and current
at bus X after the occurrence of the fault.
Consider an impedance-measuring
relay, installed at
bus X, which looks into the generator and uses the
incremental positive-sequence
voltage and current. The
relay voltage and current are given, respectively, by
Vre,ay = A Vx, = - Z,,,AZ,,

(3)

and
Fig. I. Single-line
diagram
of a two-machine,
three-phase
power
system. Z,, and Z,, are the neutral grounding
impedances
of generators Gx and Gy, respectively.
Reference

Bus

N1

(4)

Lay = - AL,
Substituting

Eq. (4) into Eq. (3) provides

Vrrlay = -qdelay

(5)

where Zs,, is the positive-sequence impedance of generator Gx.

It can be observed from Fig. 2(c), or by rearranging
Eq. (5), that the impedance seen by the relay, for an
external fault, can be expressed as
(Ix 1 be-fault

Reference

Bus

N1

(IX I)post-fault

Bus Y
(b)

Vrrlay
L?lar

sxl

(6)

Using the procedure described above, it can be

shown that if the impedance-measuring
relay uses the
incremental negative-sequence voltage A Vxz and current
AZK2, measured at bus X, the relay voltage and current
can be expressed, respectively, by
Vrr,ay = A Vx, = - Z,,,AL,

(7)

and
hay = - 42

(8)

where Zsxz is the negative-sequence impedance of generator Gx. Substituting

Eq. (8) into Eq. (7) provides

Bus Y

Bus X
w

Fig. 2. Positive-sequence
networks
for the power system of Fig. I
(external
fault): (a) prefault,
(b) postfault,
and (c) Tht-venins
equivalent circuit.

V&y = Z&lay

(9)

The impedance seen by the relay is, therefore,

negative-sequence impedance of generator Gx:

the

~relav z
I,,I,, = 5X2

(10)

T.S. Sidhu ei al.

Electric

Power

S~~.siems Rtwarch

Vrd iv
L_=
I

-a,

16 (1996)

45-55

41

+Z,,,)

Similarly, the incremental

negative-sequence
voltage
and current computed by the relay are given, respectively, by
Vrelq = - (Z,, + Z&L

(15)

and
Jrc,ay = AI,,

(16)

where Z,, is the negative-sequence impedance of the line

impedance of the
and Z,,? is the negative-sequence
equivalent source Gy.
Substituting Eq. (16) into Eq. (15) provides

By rearranging Eq. (17). the impedance seen by the

relay. for an internal fault, can be expressed as

3. Fault discrimination
Fig. 3. Positive-sequence
networks
for the power system of Fig. I
(internal
fault): (a) prefault.
(b) postfault.
and (c) Thkvenins
equivalent circuit. (Note 1: this is a crude machine representation
which is
used only for the purpose of developing
the proposed
technique.)

2.2. Internal faults

For a fault internal to generator Gx, the prefault and
postfault positive-sequence
networks are shown in Fig.
3(a) and (b), respectively.
The Thevenin equivalent
circuit is shown in Fig. 3(c). The impedance Z,, shown
in Fig. 3(b) and (c), represents the fault impedance and,
depending on the type of fault, the other sequence
network(s).
The impedance-measuring
relay uses incremental
positive-sequence
voltage and current which are given,
respectively, by
I/relay = AV,, = - (4, + .&,)AI\,

(11)

and

Lay = Ai,,

(12)

where Z,, is the positive-sequence impedance of the line

impedance of the
and Z,,, is the positive-sequence
equivalent source Gy.
Substituting Eq. (12) into Eq. (11) provides

By rearranging Eq. (13), the impedance seen by the

relay, for an internal fault, can be expressed as

The following observations can be made from Eqs.

(6), (lo), (14), and (18).
For a fault external to the generator, the positive-sequence impedance seen by the relay is the positive-sequence impedance of the generator being protected.
Similarly, the negative-sequence impedance seen by the
relay during an external fault is the negative-sequence
impedance of the generator being protected.
This
means that the machine model is verified for faults
external to the generator. However, for a fault in the
generator windings,
the positive-sequence
impedance
seen by the relay is not equal to the positive-sequence
impedance of the generator. Similarly. the negative-sequence impedance seen by the relay is not equal to the
negative-sequence impedance of the generator. The machine model, therefore, is not verified for faults internal
to the protected generator.
Inspection of Eqs. (6), (lo), (14), and (18) also indicates that the impedance seen by the relay is negative
for faults internal to the generator and positive for
faults external to the generator.
The sign of the
impedance seen by the relay can, therefore, be used to
discriminate between faults internal and external to the
protected machine and, therefore, the values of the
positive- and negative-sequence impedances of the generator need not be known. This eliminates the need for
any specific generator data and makes the technique
suitable for all generators, irrespective of their type and
ratings.
Values of the resistive component of the positive- and
negative-sequence impedances of the generator are typi-

T.S. Sidhu rt al. : Elrcrrrc

48

Power

Re[Zl

Fig.

4. Fault

discrimination

characteristics.

tally very small compared with their reactive components and, as a result, large errors can be encountered
in the estimation
of the resistive portion
of the
impedance. Only the reactive portion of the impedance,
therefore, is used for fault discrimination.
Fig. 4 depicts
the zones of discrimination
in the impedance plane for
internal and external faults.

4. The algorithm
The fault detection technique outlined in the previous
section was used to develop a digital algorithm for AC
generator stator winding protection. Generator terminal voltages and currents, sampled simultaneously at a
predefined rate, are used by the algorithm. Specifically,
the following steps are performed.
Step 1. Initialize the trigger signal, TRIGGER,
and
the two trip counters, TCOUNTl
and TCOUNT2,
to
zero.
Step 2. Test if TRIGGER
is one. If if has been one
for two consecutive sampling intervals, save the most
recent cycle of prefault phasors to a holding buffer and
proceed to Step 7. Otherwise proceed to Step 3.
Step 3. Obtain the next set of three phase voltages
and three phase currents at the machine terminals.
Step 4. Calculate the 60 Hz voltage and current
phasors for the three phases.
Step 5. Compute the positive- and negative-sequence
phasors and store them in the processors memory.
Step 6. Compare the most recent voltage and current
samples with voltage and current samples from the
previous cycle. If the change is greater than a predefined threshold,
V PMARG
for voltage and C
PMARG
for current, then set the trigger indicator,
TRIGGER,
to one. Otherwise, set TRIGGER
to zero.
Revert to Step 2.
Step 7. Compute the positive- and negative-sequence
incremental voltages and currents.
Step 8. Compute the impedances seen by the relay
using the incremental voltages and currents.
Step 9. Test if the positive-sequence
reactance is
positive.
If it is, decrement
the trip counter,

S.ystrrz.s

Research

36 (1996)

45 55

TCOUNTl,
by one. If TCOUNTl
becomes negative,
then set it to zero.
Step IO. Test if the positive-sequence
reactance is
negative. Also, test if the magnitudes of both the positive-sequence voltage and current are greater than a
predetined minimum value, EPSILON.
If these two
conditions
are met, increment
the trip counter,
TCOUNTI.
by one; otherwise, TCOUNTl
retains its
previous value.
Step 11. Test if the negative-sequence reactance is
positive.
If it is, decrement
the trip counter,
TCOUNT2,
by one. If TCOUNT2
becomes negative,
then set it to zero.
Step 12. Check if the negative-sequence reactance is
negative. Also, test if the magnitudes of both the negative-sequence voltage and current are greater than a
predefined minimum value, EPSILON.
If these two
the trip counter,
conditions
are met, increment
TCOUNT2.
by one; otherwise, TCOUNT2
retains its
previous value.
Step 13. Test if either TCOUNTl
or TCOUNT2
has
exceeded a prespecified value, THRESHD.
If either has
exceeded THRESHD,
then issue a trip command; otherwise, proceed to Step 14.
Step 14. Wait for the next set of samples and acquire
them. Calculate the 60 Hz voltage and current phasors
for the three phases. Calculate the positive- and negative-sequence phasors. Return to Step 7.

5. Generation

of test data

The performance
of the proposed algorithm
was
tested using fault data. Data needed for testing were
generated by simulations
as well as by subjecting a
laboratory generator to different types of faults.

5.1. Simuluted

dutu

Simulated transient voltages and currents, for the

purpose of testing the technique, were generated on a
Sun SPARC workstation
using the EMTDC
[9]. A
block diagram of the circuit for simulating the power
system and generating the fault data is given in Fig. 5.
Two machine models are available within the EMTDC.
One of them is a simple model of a machine in the form
of a Thevenin voltage source and its impedance. This
was used to simulate the infinite bus on the highvoltage side of a transformer.
A more detailed machine
model is also available within the EMTDC. This model
simulates a salient-pole synchronous machine complete
with a multistage turbine, exciter, and governor. The
complete model of the synchronous
machine was connected to the infinite bus via a step-up transformer
and
a transmission
line. The basic parameters of the machine that were used are listed in Fig. 5. An R-L load,

T.S. Sidhu rt al. : Electric

Powrr

S~mms

Research

._..............

Emtdc

Data

Ra
1x3
: xd
1 xd

=
s
=
=

: xq

=0.31

Generator

0.003
1.46
0.48
0.36

49

ohms (0.002pu)
ohms

(0.92~~)

duns (0.3opu)
obmn (0.22pu)
ohms

Tdo= 0.029
Tqo= 0.034

- -

(O.Slpu)

ohms (0.29pu)
eawnds
~eeonds
wzond~

Location

of Applied

Internal

Location

of Applied

External

( Close-in

Faulta

File

Unit Service Bus

Unit

( Step-up

) Transformer

Transmission
(lOOkIn)

Lie

13.3kV,

rms, line-line

23OkV,

mw, line-line

Bus

Fig.

3-phase

model

Faulta

Generation

5COMVA

8ource.

5. System

External

Fault

Bulk
equivalent

of Applied
( Distant

TransmissianL.iie
(lOokIn)

Faults

:
I
Location

Fault

Thevetis

45-55

xs = 0.46
1 Tdo=5.2

120 MVA
Unit

36 (1996)

for simulating

representing the unit service bus load, was connected

between the unit generator and unit transformer. Various types of faults were staged at three locations on the
system: at the machine terminals on the machine side of
the relay to simulate faults internal to the machine, on
the unit bus to simulate close-in faults, and on the
high-voltage side of the unit transformer, at the midpoint of the transmission line, to simulate disturbances
on the external system.
The simulated data were generated using a calculation step of 23 040 Hz in EMTDC. This allowed the
generation of spectral components up to 11 520 Hz and
provided a closer approximation
of the continuous
power system voltages and currents that would exist
during a fault. The EMTDC
output data were then
preprocessed by a digital equivalent of an anti-aliasing
filter which was implemented in Microsoft FORTRAN.
The filtered data were then resampled at a rate of 720

data using

EMTDC.

Hz and stored in a file for use by the relay algorithm.

The data contained both prefault and during-fault
voltage and current samples.
5.2. E.xperirnental

duta

A 208 V, 5 kVA, three-phase laboratory generator

was connected via a three-phase variac to the University of Saskatchewans 208 V, three-phase power supply
that provided a constant-voltage bus, as shown in Fig.
6. The prime mover for the generator was a DC motor
which was mounted on a steel skid along with the
generator. The generator was wound with split windings which allowed the stator windings to be connected
in either series or parallel. As a result, the middle of
each stator winding was also brought out to a termination box on the side of the machine. This allowed the
creation of an internal fault by shorting one half of a

50

T.S. Sidhu et ul. j Electric

Power

Systems

Research

36 (1996)

45-55

stator winding. Faults external and internal to the

generator were also applied. To limit the fault currents
for single phase-to-ground and phase-to-phase faults, a
fault resistance of 1.5 R was used between the phases
and a resistance of 2.3 s1 between the fault point and
ground. The transducer ratios were 400:5 A for the
current transformers and 100:2.45 V for the potential
transformers.
The data were acquired by using the microprocessor
based general-purpose hardware for designing relays
that is available at the University of Saskatchewan [lo].
This hardware is capable of simultaneously sampling
sixteen channels through four data acquisition modules.
However, for this work, only two data acquisition
modules were required, which allowed up to eight
channels to be sampled simultaneously. Seven of the
eight channels were ultimately used since only the three
phase voltages and currents at the generator terminals
and one current at the neutral end of a generator stator
winding needed to be recorded. The data acquisition
software was written so that voltages and current for
prefault and during-fault periods could be recorded.
The data were acquired at a rate of 3600 Hz. A
digitally simulated anti-aliasing filter, designed for a
sampling frequency of 3600 Hz and a cutoff frequency
of 270 Hz, was applied to the sampled data to remove
any frequency components between 270 and 1800 Hz.
The output of the filter was then resampled at a rate of
720 Hz and the data were stored in a file for use by the
relay algorithm.

6. Test results
(e)

A computer program that implemented the proposed

algorithm was provided with a 13-sample least-errorsquare filter [l l] for estimating the 60 Hz phasors of the
voltages and currents. The values of the predefined
phase voltage and current thresholds, VPMARG
for

Trip

voltage
bus

Fig. 6. An experimental
set-up for acquiring
on a laboratory
generator.

data during

staged faults

lO=Orr,

l=on)

$11
0

10

20

30

40

Sample

50

M)

10

Number

0-J

Fig. 7. Performance
circuit on phase A.
eonrunt

Signal

of the proposed

technique

for an internal

open

voltages and CPMARG

for currents, were set, respectively, at 3.5% and 10% changes in the most recent
voltage and current samples relative to the values of
voltage and current samples from one cycle earlier.
These parameters were used to detect a disturbance in
the system. The value of EPSILON,
which is the predefined minimum magnitude of the positive- and negative-sequence incremental voltages and currents relative
to the prefault positive-sequence voltages and currents,
respectively, was set at lo/o. Below this value the calculated impedances may yield erroneous results, and therefore the algorithm uses this minimum as a restraint for
counters TCOUNTl
or
incrementing
the trip
TCOUNT2.
The value of the trip counter threshold,

7,s. Sidhu et (11. / Elecrric~ Pmrr

-keR

1::

10

sipnd

20

to-off,

l-on)

30
40
Samph Number

50

60

70

(a)
Poaitire

ssqus.ce

Imped.oes

~Ra121

Ei
-s -0.3

-1ImlZl

-0.6
0

10

20

30
Sample

40

60

so

70

Number

(b)
-saFare03
I

-3,:

MZI

JmIZl

SO

60

70

50

60

70

tc)

Positive
1

Sequence

Trip

Count

!I]
0

10

20

30
40
Sample Number
Cd)

Negative

SequenceTrip

Count

%I-M
10

20

so
Sample

40
Number

w
Trip signal

CO=&,

l=cm,

i?:i
0

10

20

30

40

50

60

70

SampleNumber
(0

Fig. 8. Performance of the proposed technique for an internal single

phase-to-ground fault on phase A.

THRESHD, was set at 15 and this ensured security

against false trips.
6.1. Resultsfrom simuluted dutu
Fig. 7 depicts the results showing the performance of
the algorithm for an open circuit occurring in phase A
within the generator. The fault occurred at sample
number 35. Two sampling intervals elapsed before the
disturbance was detected and a trigger signal was issued, as shown in Fig. 7(a). The sequenceimpedances

S!~stnns

Resrurch

36 (1996)

45.-55

51

were calculated and are shown in Fig. 7(b) and (c),

respectively. The counts of the negative values of the
positive- and negative-sequence reactances were tallied
and their profiles are depicted in Fig. 7(d) and (e). For
this particular fault, both the positive- and negative-sequence reactances remained negative and forced both
the positive- and negative-sequence trip counters,
TCOUNTl and TCOUNT2, to exceed the predefined
threshold of 15 in 18 samples, causing a trip signal to
be issued at sample number 54. A total of 20 samples,
corresponding to a total elapsed time of approximately
28 ms, was required to issue a trip signal.
A single phase-to-ground fault on phase A was simulated at the machine terminals with the fault occurring
at sample number 35. Fig. 8 depicts the performance of
the algorithm for this case. The fault was verified at
sample number 37 and, as shown in Fig. 8(a), the
algorithm issued a trigger signal. Impedances were calculated, as shown in Fig. 8(b) and (c). immediately after
the trigger signal was set. The profiles of the trip
counters are shown in Fig. 8(d) and (e). Fig. S(f) shows
that a trip signal was issued at sample number 54. The
total elapsed time from fault inception to the setting of
the trip signal was approximately 29 ms.
A close-in single phase-to-ground fault was simulated
on phase A and the results are shown in Fig. 9. The
fault occurred at sample number 35. A trigger signal,
shown in Fig. 9(a), was issued at sample number 37.
From Fig. 9(b) and (c) it can be seen that neither
positive- nor negative-sequence reactances become negative and therefore both trip counters remain zero,
resulting in the trip signal remaining inactive, as shown
in Fig. 9(d), (e) and (f).
The performance of the proposed technique was
studied for a variety of external and internal faults.
Results from simulation studies demonstrated that the
proposed technique performed satisfactorily for internal
and external faults. The algorithm correctly discriminated between internal and external shunt and series
faults. It required approximately 29 ms to issue a trip
signal for internal faults.
6.2. Resultsfrom exprrimental dutu
The laboratory generator was subjected to an internal fault by applying a short-circuit across half of the
stator winding, from the terminal of the machine to the
50% mark of the stator winding of phase C. The fault
occurred at sample number 30. A trigger signal. shown
in Fig. 10(a), indicates that the disturbance was detected at sample number 32. Positive- and negative-sequence impedances were calculated and their profiles
are shown in Fig. 10(b) and (c). In both cases, the
reactance remained negative, both sequence trip counters were incremented, and a trip signal was issued.
This is shown in Fig. 10(d), (e) and (f). The positive-se-

52

T.S. Sidhu et al. / Electric,

Power

quence trip counter remained zero for the first five

samples since the magnitudes of either the positive-sequence voltage or the current were below a predefined
minimum threshold. The total time to trip from fault
inception, including filter delay, was approximately 29
ms or 1; cycles at 60 Hz.
A single phase-to-ground fault was applied to the
middle of the phase A stator winding. Fig. 11 shows the
results from this test. The fault occurred at sample
number 33 and a trigger signal was issued at sample
number 35, shown in Fig. 1 l(a). The trip signal was
issued at sample number 54, shown in Fig. 1 l(f), due to
Trigger

k:l:

_.

signd

(0=&r,

System

Research

36 (1996)

45-55
Trigger

signal

(O=off,

1=on)

f]
0

10

20

30

40

Sample

50

60

70

Number

(a)
Pceitive

Sequence

Impedance

0
I 4.15

-ReRe[z1

d=

-IIm[Zl

4.3
-0.45
0

10

20

30
Sample

40
Number

Izoo)

50

60

70

(b)
Negative

Sequence

Impedance

10

20

30
40
Sample Nnmber

60

50

70

(a)

1 4.2

Re[Zl

% -0.4

ImIZl

a.6
0

10

30

--Re[Zl
--+--

30
Sample

40

Im[Zl

20

30
Sample

40
Number

60

60

Sequence

70

Sequence

Trip

30

40

Count

70
j

tjp/
0

(b)
Negative

60

w
Positive

10

50

Number

10

30

Sample

Impedance

50

60

70

50

60

70

50

60

70

a fault

that

Number

63
Negative

Trip

Count

i EJp-

-ReRez1
-----b

Sequence

Im[Zl

10

20

30
Sample

40
Number

(e)
0

10

20

30

40
Number

Sample

50

60

70

Trip

w
Positive

Trip

Count

10

~
10

20

30
Sample

Sequence

yj;1

50

60

10

20

Fig. 10. Performance

short-circuits
windings

Trip

30

50

60

70

50

60

70

Number

(d
Trip

Signal

(O=off,

l=on)

iq
0

10

20

30
Sample

40
Number

(6

Fig. 9. Performance
of the algorithm
phase-to-ground
fault on phase A.

30
Sample

40
Number

for

of the proposed
of phase C.

technique

for

Count

40

Sample

al

70

~
0

l=on)

0-J

40
Number

w
Negative

(O=off.

Lq

Sequence

j$
0

Signal

a close-in

external

single

the negative-sequence trip counter exceeding the predefined threshold of 15. The positive-sequence trip
counter was incremented for a short duration while the
positive-sequence reactance dipped slightly below zero
for a few samples. However, when the positive-sequence
reactance became positive again, the positive-sequence
trip counter was decremented to zero. The total time to
trip from fault inception, including filter delay, was
approximately 31 ms or 1; cycles.
A phase-to-phase fault was applied at the generator
terminals. Fig. 12 shows the results of this test. The
fault occurred at sample number 32 and a trigger signal

53

was set at sample number 34, as depicted in Fig. 12(a).

Both sequence reactances, shown in Fig. 12(b) and (c),
initially oscillated between the positive and negative
halves of the complex Z-plane but settled quickly to
negative values. As a result of the initial oscillations,
both the positive- and negative-sequence trip counters
were delayed in accumulating counts. However, a trip
signal was issued at sample number 53 due to the
accumulated count in the positive-sequence
trip counter. The negative-sequence
trip counter also exceeded
the predefined threshold of 15 a few samples later. The
total time to trip from fault inception, including filter
delay, was approximately
33 ms.

Trigger

siid

co=dr,

30
Sample

40
Number

.H
0

20

10

Positive

.squence

20

Positive

--Rez1
-

-0.25
-0.5 1
0

60

70

1
10

20

30

40

Sequence

Impedance

-Re[Zl

Impedance

--bIm[Zl

-0.5 J
0

10

20

30
Sample

40
Number

50

60

70

Cc)

-0.5 t
1
0

70

0.75

60

d -0.26
I

0.25

4.25

50

Number

0.25

0.5

t
5

Im[ZI

(W

30
40
50
Sample
Number
(a)

Sequence

70

Impedance

3
B

Negative
10

60

0.25

Triggersiid (O=&, l=on)

60

(a)

Sample

!:I..

l-an)

Positive
10

30

20

40
Number

Sample

50

60

z-

Sequence

Trip

Count

70

(b)
Negative

Sequence

10

20

30
Sample

Impedance

40
Number

50

60

70

50

60

70

50

60

70

(4
Negative

Sequence

Trip

Count

-ReRe[z1
b

:;I-

Im[Zl

0
0

10

20

30
Sample

40
Number

Positive

50

60

Trip

20

30
Sample

50

60

10

Sequence

Fig. 12. Performance

fault at the generator

Trip

10

20

30
Sample

40
Number

50

60

70

50

60

70

(e)
nip

Signal

(O=off,

l=an)

s;]
0

10

20

30
Sample

40
Number

(f-l

Fig. 11. Performance

of the proposed
phase-to-ground
fault on phase A.

20

30
Sample

40
Number

of the proposed
technique for a phase-to-phase
terminals
between phases B and C.

Count

p]/
0

( 0 = MT, 1 = on )

(f-l

70

Cd)
Negative

Signal

$;I

Count

40
Number

40
Number

63

10

30
Sample

70

(c),.I
0

20

Trip

Sequence

j El

10

technique

for an internal

single

A double phase-to-ground
fault involving phases B
and C was applied external to the generator. The
voltage and current waveforms
recorded at the terminals of the generator for this condition are shown in
Fig. 13. The results showing the performance of the
algorithm for this test are shown in Fig. 14. The fault
occurred at sample number 31. Fig. 14(a) shows that
the trigger signal was activated at sample number 33.
The sequence impedances were calculated from sample
33 onward and and are depicted in Fig. 14(b) and (c).
Both sequence reactances remained positive, which kept
both the positive- and negative-sequence trip counters

T.S. Sidhu et ul. / Electric

54

Powr

S,ystms

Research

at zero, as shown in Fig. 14(d) and (e). No trip signal

was issued, as the fault was correctly identified as being
external to the generator.
In addition to the above tests, the performance of the
proposed technique was evaluated for a number of
additional faults. Results obtained from experimental
data indicate that the proposed algorithm did not issue
a trip command for external faults. The trip signal was,
however, issued for all internal faults in about 29 ms
after fault inception.

45-55
TriggE

siid

co.oIT,

1-m)

11

%01
0

a3

10

30

40

sample

50

60

70

Number

(a)
Panitive

7. Conclusions

A digital technique for detecting generator stator

winding faults has been presented in this paper. The
technique uses voltages and currents measured at the
generator terminals and can be used for protecting
generators,irrespective
of their size and ratings. The
proposed technique was tested by using the simulated
data and the data that were recorded when a laboratory
generator was subjected to a variety of faults. Test
results show that the technique correctly discriminates
between external and internal faults. The typical fault
detection time for internal faults is 29 ms. The proposed technique also detected open-circuit
faults and
faults when windings of one phase are short-circuited.
These faults cannot be detected by conventional differ-

36 (1996)

10

Sequence

20

Impedance

30

40

Sample

Number

50

60

70

(b)

27
1

.3
o 0.

rk[Zl

-Im[Z]

-1 1
0

10

20

30
Sample

40
Number

50

60

70

Cc)
Fbsitive

Sequence

ji$

Trip

Count

-~
0

10

20

40

30

Negative

Sequence

pJ

Trip

50

60

70

50

60

70

50

60

70

Count

~
0

10

20

30
sample

40
Number

(e)
31
Sample

41
Number

Trip

signal

(O=ofr,

l=on)

E;l
0

@I

la

11

21

It-

31
Sample

41
Number

Fig. 14. Performance

double phase-to-ground

-1c

51

10

61

71

(b)
Fig. 13. Filtered and resampled (a) voltage and (b) current waveforms
at the relay for an external
double phase-to-ground fault involving
phases B and C.

20

30
Sample

40
Number

of the proposed
technique
for an external
fault involving
phases B and C.

ential relays. The algorithm based on the proposed

technique can be easily implemented on a microprocessor based system and integrated with other generator
protection and monitoring functions.

References
[I]

M.S. Sachdev
lio~z Systems.

(Coordinator),
IEEE Tutorial

Microprocessor
Course Text.

Relays
Power

and ProtecEngineering

T.S. Sidh

[2]

[3]

[4]
[5]

[6]

et crl. , Electric

Poner

Society
Special Publ. No. 88 EHO269-I-PWR.
IEEE, Piscataway. NJ. USA, 1988.
M.S. Sachdev and D.W. Wind, Generator
ditrerential
protection
using a hybrid
computer,
IEEE
Trams. Power Appar-. Syst.,
PAS-92 (1973) 2063-2072.
G.S. Hope,
P.K. Dash and O.P. Malik.
Digital
differential
protection
of a generating
unit scheme and real-time
test results,
IEEE Trans. Power Appar. Syst.. PAS-96
(1977) 502-512.
H. Tao and I.F. Morrison,
Digital
winding protection
for large
generators,
J. Eiecfr. Electron.
Eng. Ausf.. 3 (1983) 316-321.
P.K. Dash, O.P. Malik and G.S. Hope, Fast generator
protection against internal
asymmetrical
faults. IEEE Trans. Po~mer
Appar. Syst., PAS-96 (1977) 1498~1506.
G. Benmouyal,
S. Barceloux
and R. Pelletier,
Field experience
with a digital
relay for synchronous
generators,
/EEE Truns.
Power Delivery,
7 (4) (1992) 1984- 1992.

Svstems

Research

36 (1996)

45 -55

55

[7] H.T. Yip,

.4n integrated
approach
to generator
protection.
Proc. Ccm. Elecrr. Assoc. Eng. Oper. Die. Meel.,
1994, Paper
No. 94-SP-25.
[8] G. Ziegler. Developments
in generator
protection
~ design and
application
aspects of a new numerical
relay range, Sr/z ht.
Confl Deuelopments
in Power
System Protection,
York,
UK,
1993, Conf. Pub]. No. 368. IEE, London,
pp. 111~114.
[9] Manitoba
HVDC
Research
Center,
EMTDC
Users Mnnual,
Winnipeg,
Manitoba.
Canada.
1986.
[IO] H.C. Wood.
T.S. Sidhu, M.S. Sachdev,
and M. Nagpal,
A
general-purpose
hardware
for microprocessor
based relays,
Proc,. ht. Conj. Power System Protection.
Singapore,
1989, pp.
43 -59.
[I I] M.S. Sachdev and M.A.
Baribeau,
A new algorithm
for digital
impedance
relays. IEEE
Trans. Power Appur.
Syst.. PAS-98
(1979) 2232-2240.