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Confidential
Table of Contents
CONTENTS
PAGE
Sections
1. Features
1-1
2. Specifications
2-1
3. On Screen Display
3-1
4-1
5. Pin Assignment
5-1
6-1
7-1
8. Waveforms
8-1
9. Trouble Shooting
9-1
10-1
11-1
12-1
Appendix
1. Main Board Circuit Diagram
2. Main Board PCB Layout
3. Assembly Explosion Drawing
Block Diagram
VINC
Service Manual
VIZIO VP50HDTV10A
Chapter 1
Features
Wall-mountable
HDCP supportive
2 HDMI inputs
Closed caption
Page 1-1
File No. SG-0219
Chapter 2
Specification
1. OPTICAL CHARACTERISTICS
Item
Specification
Display Pixels
Display Cells
Pixel Pitch
Pixel Type
Non-stripe
Color Depth
(w/glass filter)
Contrast ratio (panel spec)
Note
Min.280 cd/m2
15000:1 (Typical, dark room)
x=0.3100.02, y=0.3100.02
RGB
2. INPUT SOURCE
RGB Signal
H: support to 30-80KHz
V: support to 60-85Hz
Pixel Clock: support to 108MHz
HDMI Signal
H: 15.734KHz
V: 60Hz (480i)
H: 31KHz
V: 60Hz (480p)
H: 45KHz
V: 60Hz (720p)
H: 33KHz
V: 60Hz (1080i)
Page 2-1
File No. SG-0219
V: 60Hz
(NTSC)
YPbPr/YCbCr
H: 15.734KHz
V: 60Hz (NTSC-480i)
H: 31KHz
V: 60Hz(NTSC-480p)
H: 45KHz
V: 60Hz(NTSC-720p)
H: 33KHz
V: 60Hz(NTSC-1080i)
RF Connector
Page 2-2
File No. SG-0219
3. INPUT CONNECTORS
Input Label
SERVICE1
Connector Type
RJ-11 x 1
Input Label
Connector Type
SERVICE2
RJ-11 x 1
HDMI1
19 pin HDMI x 1
AV1
19 pin HDMI x 1
D-sub 15 pin x 1
OUT
(Optical)
input)
DTV/TV
RF x 1 (Combo, F
Connector for internal
ATSC/QAM/NTSC
Tuner)
4. OUTPUT CONNECTORS
a. Audio RCA Jack x 2
b. 3.5mm Mini-jack earphone x 1
c. SPDIF Digital Audio Out (Optical)
5. POWER SUPPLY
Consumption: 550W MAX
6. SPEAKER
Output 8/10W (max) X2
Page 2-3
File No. SG-0219
7. ENVIRONMENT
Operating
a.
Temperature: 0~40
b.
c.
Altitude: 0~6,560 ft
Non-operating
a.
Temperature: -20~60
b.
c.
Altitude: 0~9,840 ft
8. DIMENSIONS
a.
Height: 871 mm
b.
Width: 1241mm
c.
9. WEIGHT
a.
Net
b.
Page 2-4
File No. SG-0219
Chapter 3
On Screen Display
Name
MENU
CH+/
CH-/
VOL+/ VOL-/
7
INPUT
OSD Adjustment
Main OSD Tree
Mode
Image Settings
Picture Mode
VIDEO (Custom,vivid,
Movie,Game,Sport)
VIDEO Brightness(0~100)
VIDEO Contrast(O~100)
VIDEO Saturation(0100)
VIDEO Hue(-50~50)
VIDEO Sharpness(0~24)
VIDEO Advanced
VIDEO
Noise Reduction
VIDEO
Motion(0~16)
VIDEO
Digital(0~64)
OffHigh
VIDEO
Fleshtone
ModerateLow
Dynamic Contrast
VIDEO
(0,1,2,3)
CONFIDENTIAL DO NOT COPY
Page 3-1
File No. SG-0219
Mode
VIDEO Custom Color
VIDEO
Red(0~100)
VIDEO
Green(0100)
VIDEO
Blue(0~100)
PC
Auto Adjustment
PC
lmage Position
PC
Phase
PC
CIocks/Line
PC
Color Temp
PC
Warm(5400K)
PC
Standard(6500K)
PC
Cool(9300K)
PC
User
PC
Red(0~100)
PC
Green(0100)
PC
Blue(0~100)
Display Settings
16:94:3Zoom
Aspect Ratio
16:94:3
PIP
Off, Large PIP,
PIP Mode
Small PIP, POP
PIP Position
Top-Left,
Page 3-2
File No. SG-0219
Mode
Top-Right,
Bottom-Left,
Bottom-Right
PIP Input **
Audio Settings
Bass(0~20)
Treble(0~20)
Balance(-10~10)
SRS TS XT(On,Off)
Auto
Volume(On,Off)
Speakers(OnOff)
Audio Out***
VIDEO
Password
VIDEO
VIDEO
Settings
TV Rating
TV Youth
VIDEO
(Unblocked
Blocked)
TV Youth 7
VIDEO
(Unblocked
Blocked)
VIDEO
CONFIDENTIAL DO NOT COPY
TV G
Page 3-3
File No. SG-0219
Mode
(Unblocked
Blocked)
TV PG
(Unblocked
VIDEO
Blocked)
TV 14
(Unblocked
VIDEO
Blocked)
TV MA
(Unblocked
VIDEO
Blocked)
VIDEO
VIDEO
Unblocked
Movie Rating
Movie G
VIDEO
(Unblocked
Blocked)
Movie PG
VIDEO
(Unblocked
Blocked)
Movie PG-13
VIDEO
(Unblocked
Blocked)
Movie R
VIDEO
(Unblocked
Blocked)
Page 3-4
File No. SG-0219
Mode
Movie NC-17
(Unblocked
VIDEO
Blocked)
Movie X
(Unblocked
VIDEO
Blocked)
VIDEO
Unblocked
Block
VIDEO
Unrated(NoYes)
Change
VIDEO
Password
Please enter new
VIDEO
password
Please re-enter
VIDEO
new password
Clear All
VIDEO
(No,Yes)
Setup
Closed Caption
CC1, CC2, CC3,
CC4, TEXT1,
Display
TEXT2, TEXT3,
TEXT4
Captions on mute On, Off
Page 3-5
File No. SG-0219
Mode
English, French,
Language
Spanish
Factory Reset
(No,Yes)
Image Cleaner
Firmware Version
TV
TV Menu
TV
Auto Scan
Set Channel
TV
(Add/Skip)
TV
DTV
Cable/Antenna
DTV Menu
Page 3-6
File No. SG-0219
DTV Menu
DTV Menu
A.DTV Tuner
Setup
a.Time Zone
1.Hawall
2.Eastern Time
3.Indiana
4.Central Time
5.Mountain Time
6.Arizona
7.Pacific Time
8.Alaska
b.Cable/Air/Auto
c.Scan****
d.Manual Scan****
Scan mode
Add-on Mode
Range Mode
From Channel
To Channel
e.Channel Skip
f.Digital Audio Out
CONFIDENTIAL DO NOT COPY
Page 3-7
File No. SG-0219
DTV Menu
1.PCM
2.OFF
3.Dolby Digital
B.Closed
Caption
a.Analog Closed
Caption
CC1~CC4OFF
b.Digital Closed
Service1~Service6
CAPTION
OFF
Page 3-8
File No. SG-0219
DTV Menu
Yellow
Magenta
(3)Font Opacity
Solid
Translucent
Transparent
(4)Background
Color
Black
White
Green
Blue
Red
Cyan
Yellow
Magenta
(5)Background
Opacity
Solid
Translucent
Transparent
(6)Window Color
Black
CONFIDENTIAL DO NOT COPY
Page 3-9
File No. SG-0219
DTV Menu
White
Green
Blue
Red
Cyan
Yellow
Magenta
(7)Window Opacity
Solid
Translucent
Transparent
Parental
control
C. Password
Channel Block
Page 3-10
File No. SG-0219
SUB
DT
AV1
AV2
Component 1
Component 2
DTV
TV
MAIN
TV
RG
HDMI 1
HDMI 2
AV1
AV2
Component 1
Component 2
RGB
HDMI 1
HDMI 2
9
9
Remark
(1)
9 Indicates which inputs are available for PIP and POP modes.
(2)
For AV1 and AV2, S-Video has priority. If a signal is connected to AV1 S-Video by itself or
signals are connected to AV1 S-Video and AV1 Video simultaneously, then S-Video will be
the only choice for AV1. If a signal is connected to AV1 Video only, then Video will be the
only choice for AV1. The same input priority scheme applies to AV2.
***
**** Do Scan or Manual Scan function, it maybe spend several minutes is normal. It
depends on channels and area.
Page 3-11
File No. SG-0219
Chapter 4
Mode
No.
Refresh Horizontal
Resolution
Rate
Vertical
Frequency Frequency
(Hz)
(KHz)
(Hz)
Horizontal
Vertical
Sync
Sync
Pixel Rate
Polarity
Polarity
(MHz)
(TTL)
(TTL)
Remark
640x480
60
31.5
59.94
25.175
Windows
640x480
75
37.5
75.00
31.500
Windows
800x600
60
37.9
60.317
40.000
Windows
800x600
75
46.9
75
49.500
Windows
800x600
85
53.7
85.06
56.250
Windows
1024x768
60
48.4
60.01
65.000
Windows
1024x768
70
56.5
70.07
75.000
Windows
1024x768
75
60.0
75.03
78.750
Windows
1366X768
60
47.7
60.00
85.500
Windows
10
1280X1024
60
63.98
60.02
108.000
Windows
1024x768
Page 4-1
File No. SG-0219
Mode No.
Resolution
480i
480p
720p
1080i
Resolution
480i
480p
720p
1080i
3.2 PC input
Mode
No.
Resolution
640x480
Horizontal
Refresh
Horizontal
Vertical
Rate
Frequency
Frequency
(Hz)
(KHz)
(Hz)
60
31.5
59.94
Vertical
Sync
Sync
Pixel Rate
Polarity
Polarity
(MHz)
(TTL)
(TTL)
25.175
Remark
Windows
Resolution
1080i
Mode No.
Resolution
480i
3.4 TV input
Page 4-2
File No. SG-0219
Chapter 5
Pin Assignment
(1) RF Connector
(2)
RGB Connector
a. Type:
Analog
b. Frequency: H: 30-80KHz
V: 60-85Hz
Video bandwidth:
g. Connector type:
TTL
TTL
135MHz
15-pin D-Sub, female
Page 5-1
File No. SG-0219
1
5
10
(3)
15
15
Pin
1
10
11
Pin Assignment
Pin
11
Pin Assignment
+5V
10
Ground
11
No connection
Ground
12
(SDA)
Ground
13
14
Vertical sync
15
(SCL)
HDMI
a. Frequency: H: 15.734KHz
V: 60Hz
H: 31KHz
V: 60Hz
H: 45KHz
V: 60Hz
H: 33KHz
V: 60Hz
b. Polarity:
Positive or Negative
c. Type:
Type A
d. Pin Assignment:
Page 5-2
File No. SG-0219
Pin 19
Pin 1
Pin 2
Pin
(4)
Signal Assignment
Pin
Signal Assignment
TMDS Data2+
TMDS Data2-
TMDS Data1+
TMDS Data1-
TMDS Data0+
TMDS Data0-
10
TMDS Clock+
11
12
TMDS Clock-
13
CEC
14
15
SCL
16
SDA
17
EDID/CEC Ground
18
+5V Power
19
RCA jack
V: 60Hz
c. Impedance: 75
Sync (H+V):
d. Connector type:
RCA jack
(NTSC)
Page 5-3
File No. SG-0219
(5)
S-Video Connector
1, 2 = GND
3 = Luminance (Y)
4 = Chrominance(C)
a. Frequency: H: 15.734KHz
V: 60Hz
C: 0.286Vp-p
(NTSC)
c. Impedance: Y: 1Vp-p
d. Connector type:
(6)
V: 60Hz
(NTSC-480i)
H: 31KHz
V: 60Hz
(NTSC-480p)
H: 45KHz
V: 60Hz
(NTSC-720p)
H: 33KHz
V: 60Hz
(NTSC-1080i)
c. Impedance: 75
d. Connector type:
(7)
RCA jack
PC audio in
a. Signal level: 1Vrms
b. Impedance: 47K
c. Connector type:
Page 5-4
File No. SG-0219
RCA L/R:
630 690 m
13.2M pbs
(10) Earphone
a. Signal level: 1Vrms (max.)
b. Impedance: 32
c. Output:
50 mW
d. Connector type:
RCA L/R:
Page 5-5
File No. SG-0219
CN2
CN3
DC POWER INPUT
PIN
Description
PDP_+5Vsc
PDP_+5Vsc
PDP_+5Vsc
GND
GND
GND
PDP_+12V
PDP_+12V
GND
10
GND
11
PDP_+12V_FAN
12
PDP_FGND
PIN
Description
PDP_Audio
PDP_Audio
GND
GND
DC POWER INPUT
DC POWER INPUT/OUTPUT
PIN
Description
GND
VS_ON
RLY_ON
PDP_+5Vsb
BRIGHT
Page 6-1
File No. SG-0219
CN5
CN6
CN7
CONNECTION
KEYPAD
PIN
Description
LED2_KEYPAD
KEY_VCC
IR
ADC_IN2
NC
GND
+3.3V_LBADC
ADC_IN1
LED1_KEYPAD_BUF
10
GND
P1
GND
P2
GND
CONNECTION HDMI/ATSC_UP
PIN
Description
+5V
51_TXD
51_RXD
GND
PIN
Description
VGA_SCL_CTZ
VGA_SDA_CTZ
GND
CONNECTTION ODC2BI
Page 6-2
File No. SG-0219
CN12
CN13
J7
J8
FAN CONNECTION
PIN
Description
NC
FANIN1
+12V_FAN
FGND
PIN
Description
FANIN1
+12V_FAN
FGND
FAN CONNECTION
CONNECTION SPEAKER R
PIN
Description
RL-
RL+
NC
PIN
Description
LL-
LL+
CONNECTION SPEAKER L
Page 6-3
File No. SG-0219
W1
CONNECTION LVDS
PIN
Description
PIN
Description
GND
TXA3+
TXA3-
TXAC+
TXAC-
GND
TXA2+
TXA2-
TXA1+
10
TXA1-
11
TXA0+
12
TXA0-
13
GND
14
GND
15
+5V_SW
16
+5V_SW
17
+5V_SW
18
GND
19
GND
20
NC
21
NC
22
NC
23
NC
24
TXB3+
25
TXB3-
26
GND
27
VS_ON
28
SCL_33V
29
SDA_33V
30
NC
31
GND
Page 6-4
File No. SG-0219
W1
J3
Description
PIN
Description
GND
SCL_5V
ATSC_CLK
SDA_5V
GND
ATSC_RST
ATSC_WS
ATSC_RDY
GND
10
GND
11
ATSC_DA
12
SV1_CTZ / SV1_HUD
13
GND
14
GND
15
ATSC_Y
16
N/C
17
GND
18
GND
19
ATSC_Pb
20
SIF_Tuner1
21
GND
22
GND
23
ATSC_Pr
24
SIF_Tuner2
25
N/C
26
N/C
27
+12V_SW
28
ATSC_Audio_L
29
+12V_SW
30
ATSC_Audio_R
31
+5V_SW
32
ATSC_TX
33
+5V_SW
34
ATSC_RX
35
+5V_SW
36
CHKTNR0
37
+5V_SW
38
+8V
39
+5V_SW
40
+8V
ON
ADD JUMPER
PIN
Description
Default
1-2
+3.3V_I/O
ON
2-3
+5V
OFF
, OFF NO JUMPER
Page 6-5
File No. SG-0219
J9
CONNECTION PROGRAMUPDATA
ON
J10
ADD JUMPER
PIN
Description
Default
1-2
ARXD
ON
2-3
ARXD_HUD
OFF
, OFF NO JUMPER
CONNECTION PROGRAMUPDATA
ON
ADD JUMPER
PIN
Description
Default
1-2
ATXD
ON
2-3
ATXD_HUD
OFF
, OFF NO JUMPER
Page 6-6
File No. SG-0219
ATSC Board
W1
J10
Description
PIN
Description
GND
Tuner-SCL2
A01MICLK/A01BLK
Tuner-SDA2
GND
ORESET
A01LRCK
READY
GND
10
GND
11
A01SDATA0
12
NTSC-CVB1
13
GND
14
GND
15
MAIN-YOUT
16
N/C
17
GND
18
GND
19
MAIN-PbOUT
20
NTSC-SIF
21
GND
22
GND
23
MAIN_PrOUT
24
N/C
25
HDMI-SPDIF
26
SPDIF-Ctrl
27
+12V_SW
28
Audio_LCHOUT
29
+12V_SW
30
Audio_RCHOUT
31
N/C
32
U2TX
33
N/C
34
U2RX
35
N/C
36
Tuner SW
37
N/C
38
N/C
39
N/C
40
N/C
PIN
Description
1-3
GND
4-5
+12V
Page 6-7
File No. SG-0219
Chapter 7
Page 7-1
File No. SG-0219
Clock Generation:
The FLI8532 features six clock inputs. All additional clocks are internal clocks derived from
one or more of these:
1.Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator
and corresponding logic. A 19.6608 MHz TV crystal is recommended for best noise
immunity with the 3D decoder. Alternatively, a single-ended TTL/CMOS clock oscillator can
be driven into the TCLK pin (leave XTAL as N/C in this case). If an external crystal is being
used, connect a 10K pull-up to OCMADDR_19. See Figure 9.
2.Digital Input Video/Graphics Clocks (IPCLK0, IPCLK1, IPCLK2 and IPCLK3)
3.Audio Delay Clock (AVS_CLK)
The FLI8532 TCLK oscillator circuitry is a custom designed circuit to support the use of an
external oscillator or a crystal resonator to generate a reference frequency source for the
FLI8532device.
CONFIDENTIAL DO NOT COPY
Page 7-2
File No. SG-0219
Figure 8-3
The figure above depicts the data-path for the AFE and Decoder blocks with connections to
the input multiplexer that selects whether the data follows the Main Video Channel or PIP
video channel.
The analog front end of FLI8532 provides the capability to capture 16 analog video inputs
which can be a combination of Composite (CVBS), S-Video (SY, SC), YPrPb (Y, Pr, Pb) or
RGB (R,G, B).
Page 7-3
File No. SG-0219
Page 7-4
File No. SG-0219
LVDS Transmitter:
Two LVDS channels (A and B) are available on the output of the FLI8532 to transmit data and
timing information to the display device.
The following diagram shows the available LVDS mapping for 30-bit LVDS output which is
applying to PDP panel spec:
Note:
OSD OVL data bit is enabled with register 0x8500[9] with polarity controlled by 0x8500[10].
If 0x8500[9] = 0, then OSD OVL LVDS bit is clamped to 0.
CONFIDENTIAL DO NOT COPY
Page 7-5
File No. SG-0219
On Chip Microcontroller:
The FLI8532 on-chip micro-controller (OCM) serves as the system micro-controller.
It programs the FLI8532 and manages other devices in the system such as the keypad and
non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins.
The OCM can address a 22-bit address space to utilize 4 MB external ROM
Page 7-6
File No. SG-0219
The two-wire protocol requires each slave device to be addressable by a 7-bit identification
number.
A two-wire data transfer consists of a stream of serially transmitted bytes formatted as shown
in the figure below. A transfer is initiated (START) by a high-to-low transition on MSTR_SDA
while MSTR_SCL is held high. A transfer is terminated by a STOP (a low-to-high transition on
MSTR_SDA while MSTR_SCL is held high) or by a START (to begin another transfer).
Page 7-7
File No. SG-0219
Clock Generation
The FLI8125 accepts the following input sources:
1.Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator
and corresponding logic. Alternatively, a single ended TTL/CMOS clock input can be driven
into the XTAL pin (leave TCLK as n/c in this case).
2.External Clocks on various GPIOs for test purposes
3.Host Interface Transfer Clock (SCL), I2C slave SCL for DDC2Bi and another SCL for Serial
Inter-Processor Communication (SIPC)
4.Video Port VCLK
5.Second Video port clock. This is shared with ROM Address line 11. This is available only
when parallel ROM interface is not used.
Clock Synthesis
Additional synthesized clocks using PLLs:
1.Main Timing Clock (T_CLK) is the output of the chip internal crystal oscillator. T_CLK is
derived from the TCLK/XTAL pad input.
2.Reference Clock (R_CLK) synthesized by RCLK PLL using T_CLK or EXTCLK as the
reference.
3.Input Source Clock (SCLK) synthesized by SDDS PLL using input HS as the reference. In
case of analog composite video input this runs in open loop. The SDDS also uses the
R_CLK to drive internal digital logic.
4.Display Clock (DCLK) synthesized by DDDS PLL using IP_CLK as the reference. The
DDDS also uses the R_CLK to drive internal digital logic.
5.Fixed Frequency Clock (FCLK) synthesized by FDDS. Used as OCM_CLK domain driver.
6.Extended Clock (ECLK) synthesized by EDDS. Used by the decoder.
7.A fixed frequency clock created by LDDS (LCLK). Used by the expander in case of
panoramic scaling.
Page 7-8
File No. SG-0219
Page 7-9
File No. SG-0219
Page 7-10
File No. SG-0219
Figure 8-10
Digital Datapath
Page 7-11
File No. SG-0219
Input Capture
The Input Capture block is responsible for extracting valid data from the input data stream and
creating the required synchronization signals required by the data pipeline. This block also
provides stable timing when no stable input timing exists.
The selected input data stream is cropped using a programmable input capture window. Only
data within the programmable window is allowed through the data pipeline for subsequent
processing. Data that lies outside of the window is ignored.
Figure 8-11
Input cropping is required in a video system since video signals are normally over scanned.
For a flat panel TV, in order to over scan the image, a smaller portion of the input image needs
to be selected and then expanded to fill the entire screen.
Input data streams originating from CCIR656 sources are cropped with reference to the start
and end of active video flags encoded into the data stream. For all other inputs, the Input
Capture Window is referenced with respect to Horizontal and Vertical Sync.
Page 7-12
File No. SG-0219
Image Processing
The following figure shows the various image processing blocks that operate on the captured
video data stream. Each block is individually selectable and can be removed from the
processing chain via a selectable bypass path. When a processing block is bypassed, it
automatically enters a low power mode to help reduce overall power consumption.
Figure 8-12
Scaling Engine
The Scaling Engine accepts both 16-bit 4:2:2 YUV and 24-bit RGB inputs. It is capable of
scaling the input by a factor of 0.05 to 5.0. A flexible tap structure is used so that the number
of taps can be increased based on the number of pixels per line and whether the input is 4:2:2
YUV or 4:4:4 RGB. To reduce the amount of memory required for the vertical scaling process,
horizontal shrink is performed prior to vertical scaling and horizontal expansion happens after
vertical scaling. The maximum number of pixels per line supported by the vertical scalar is
1366.
Page 7-13
File No. SG-0219
display frame rate is synchronized to the input frame or field rate. This mode is used for
standard operation.
no valid input timing (i.e. to display OSD messages or a splash screen) or for testing purposes.
In free-run mode, the display timing is determined only by the values programmed into the
display window and timing registers.
Page 7-14
File No. SG-0219
Data captured by the Input Capture Window and processed by the various image
manipulation blocks is output in the Display Active Window. This window is always in the
foreground and lies on top of all other output windows, except OSD overlay windows.
Typically the Display Active Window is set to the same size as the output of the Scaling
Engine. If the Display Active Window is set too small, then the bottom and right hand edges of
the image data are cropped. If the Display Active Window is set too large, then the extra
space to the left and bottom of the Display Active Window is forced to the Background
Window color.
Output Dithering
The CLUT outputs a 10-bit value for each color channel. This value is
dithered down to either 8-bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels. In
this way it is possible to display 16.7 million colors on a LCD panel with 6-bit column drivers.
Page 7-15
File No. SG-0219
The benefit of dithering is that the eye tends to average neighboring pixels and a smooth
image free of contours is perceived. Dithering works by spreading the quantization error over
neighboring pixels both spatially and temporally. Two dithering algorithms are available:
random or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel.
All gray scales are available on the panel output whether using 8-bit panel (dithering from 10
to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).
Page 7-16
File No. SG-0219
Figure 8-14
Page 7-17
File No. SG-0219
Page 7-18
File No. SG-0219
Figure 8-16
Figure 8-17
CONFIDENTIAL DO NOT COPY
Page 7-20
File No. SG-0219
Chapter 8
Waveforms
1. Ripple Voltage
(1) PDP_+5Vsc (CN1.1)
Page 8-1
File No. SG-0219
Page 8-2
File No. SG-0219
+3.3V_ADC_HUD
+1.8V_ADC_HUD
Page 8-3
File No. SG-0219
+1.8V_ADC
Page 8-4
File No. SG-0219
+2.5V_DDR
+1.8V_CORE
Page 8-5
File No. SG-0219
Page 8-6
File No. SG-0219
Page 8-7
File No. SG-0219
2. Clock Timing
(1) NT5DS16M16CS-5T DDR clock (pin 45 of the U16 or U17)
(2) FLI8125
Crystal clock (pin 15 of the U10)
Page 8-8
File No. SG-0219
(3) FLI8532
Crystal clock (pin B26 of the U13 or pin 1 of the C155)
Page 8-9
File No. SG-0219
Page 8-10
File No. SG-0219
Page 8-11
File No. SG-0219
Page 8-12
File No. SG-0219
V-sync
Page 8-13
File No. SG-0219
BHS-sync
Page 8-14
File No. SG-0219
BVS-sync
Page 8-15
File No. SG-0219
Page 8-16
File No. SG-0219
ATSC Board
1. Voltage Measurement
(1) 12V (+12V, C4)
Page 8-17
File No. SG-0219
Page 8-18
File No. SG-0219
Page 8-19
File No. SG-0219
Page 8-20
File No. SG-0219
2. Clock Timing
(1) MT5351 Clock Timing (U10 B2-OXTALI)
(2) MT5112 Clock Timing (U9 97-XTAL1 / 96-XTAL2) Ch1 XTAL1 / Ch2 XTAL2
Page 8-21
File No. SG-0219
Page 8-22
File No. SG-0219
Chapter 9
A. SYSTEM OVERVIEW
Y driver board
X driver board
Display board
Main board
EMI filter
IR board
ATSC Board
Page 9-1
File No. SG-0219
PART NUMBER
FUNCTION DESCRIPTION
X DRIVER BOARD
Y DRIVER BOARD
MAIN BOARD
385001020150
IR BOARD
385000220189
DISPLAY BOARD
385000220156
ATSC BOARD
385000120187
DTV/TV MODLE
C. BOARD PICTURE
MAIN BOARD
Page 9-2
File No. SG-0219
DISPLAY BOARD
IR BOARD
Page 9-3
File No. SG-0219
ATSC BOARD
Page 9-4
File No. SG-0219
U26 MAX232A
ATXD_HUD
J9
2
1
3
J10
2
1
3
ARXD
ATXD_HUD
ATXD
ARXD_HUD
ARXD_HUD
U40 24LC128
EEPROM(8051)
UC_SCL/UC_SDA
U20 4052
I/O SW
U38
SST89C58
HY5DU56822CT-D4
U17 DDR RAM CTZ
51_RXD/51_TXD
HY5DU56822CT-D4
U16 DDR RAM HUD
FL8532_CTZ
Frame Store
DDR Interface
W8
51_RXD/51_TXD
ARXD
ATXD
ADATA[0:23]
IPCLK0/AHS/AVS/AHREF_DE
HDMI1 AUDIO
CN17
U37 24LC02
EEPROM HDMI1
IPCLK0/AHS/AVS/AHREF_DE
IPCLK1/BHS/BVS/BDE
BDATA[0:23]
IPCLK1/BHS/BVS/BDE
HDMI2 AUDIO
W13
ANLOG DDC
U40 24LC02
EEPROM HDMI2
VS / HS
CN16
U45 74HCT14
Inverting Schmitt Trgger
R G B
U22 M61323FP
VEDIO SW
MSTR1_SCL/MSTR1_SDA
2 Wire
Controller
AIR_RAW_HS_CS/AIR_RAW_VS
SV4_CTZ
SV2_CTZ
SV3_CTZ/A1_CTZ
B1_CTZ/C1_CTZ
A4/B4/C4_CTZ
A3/B3/C3_CTZ
A2/B2/C2_CTZ
A4/B4/C4
JTAG_BS_TCK/TDO/TMS/TDI/TRST
NTSC CVBS(SV1_HUT)
W6
U23 M61323FP
VEDIO SW
A3/B3/C3_CTZ
U24 M61323FP
VEDIO SW
A3/B3/C3_HUD
ATSC Y
Pr Pb
MSTR1_SCL/MSTR1_SDA
Y Pr Pb
JTAG_BS_TCK/TDO/TMS/TDI/TRST
ATXD_HUD
ARXD_HUD
Y Pr Pb
W7
AIR_RAW_HS_CS/AIR_RAW_VS
A4/B4/C4_HUD
A3/B3/C3_HUD
A2/B2/C2_HUD
SV4_HUD
SV2_HUD
SV3_HUD/A1_HUD
B1_HUD/C1_HUD
A2/B2/C2
COMP1_Audio_R/L
COMP2_Audio_R/L
W11
2 Wire
Controller
KEY PAD
CN5
CN12
CN13
GPIO
2 Wire
Controller
ADATA[0:23]
BDATA[0:23]
U21 24LC02
EEPROM VGA
UART
MSTR2_SCL/MSTR2_SDA
VGA_SCL / VGA_SDA
VGA_SCL / VGA_SDA
Frame Store
DDR Interface
Digital A
Input
Digital B
Input
LVDS
Display
Interface
Display
W1
Analog
input
JTAG Boundary
Scan
OCM External
SRAM
2 Wire
Controller
XU1 A29LV320D
MEMERY_CTZ
NC7SB3157
U18 BUS SW
JTAG Boundary
Scan
I2CCM
UART
Analog
input
Serial ROM
Interface
U11 24LC32
EEPROM HUD
U12 SST25VF040
FLASH 512K HUD
AudioAV1_R/L
IPCLK1/BHS/BVS/BDE
CVBS1
CVBS2
W14
BDATA[0:23]
AudioAV2_R/L
NTSC CVBS(SV1_CTZ)
GPIO
LVDS
Display
Interface
FL8125_HUD
W10
Y1/C1
Y2/C2
U37 CS3443
HDMI2 LR DAC
U36 CS3443
HDMI1 LR DAC
U46 IDTQS3253
HDMI1 AUDIO SW
U42 IDTQS3253
HDMI1 AUDIO SW
W5
MSTR2_SCL/MSTR2_SDA
HDMI1_AUDIO_L/R
HDMI2_AUDIO_L/R
AudioAV1_R/L
AudioAV1_R/L
VGA_AUDIO_L/R
COMP1_Audio_R/L
COMP2_Audio_R/L
VGA_AUDIO_L/R
ATSC Audio L/R
W13
AUDIO L/R
OUT
U28 MAX4550
AUDIO SW
4/2 I/O
U27 MAX4550
AUDIO SW
4/2 I/O
CH4_R/L
CH3_R/L
CH2_R/L
CH1_R/L
TUNER SIF
U32 P4450G
AUDIO
PROCESS
Lineout_R/L
U33 PT2308
AUDIO DRIVER
HLIN/HRIN
U34 PT2308
AUDIO DRIVER
TDA8946AD
AUDIO_AMP
J7
Speaker R
J8
Speaker L
W12
Headphone
DTV
TV
TUNER
TUNER SIF
NTSC CVBS
U9
MT5112
U10
MT5351
FQD1236/F H-5
Page 9-5
File No. SG-0219
No
Power LED is lighting?
Yes
Yes
No
Power LED is lighting?
No
No
No
No
Remove R87.
Check U13 pin AD14.
Is AD14 high?
U13 fail
Yes
No
Power LED is lighting?
No
Check internal cable?
1.CN1s cable
2.CN3s cable
Yse
No
Yes
Panel power
fail
Fuse fail
No
No
Yes
D10,D11 LED is lighting?
Check U3.43.3V
Yes
U3 fail
No
Check U81.8V
U8 fail
Yes
No
Yes
Check U92.5V
No
Yes
U13 fail
U9 fail
No
If power_off high
U2,U5 ON
Check +3.3V_SW
,+5V_SW,+12V_SW
(pin 5,6 and pin 7,8)
U2,U5 fail
Block 1
Check component 1
(Y signal) C252
Is there sync?
No
Yes
1
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U13 fail
Page 9-6
File No. SG-0219
No
No
Check component 1
(Pb signal) C259
Is there sync?
Is picture on screen?
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U13 fail
No
No
Check component 1
(Pr signal) C264
Is there sync?
Is picture on screen?
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U13 fail
No
Is picture on screen?
Check component 1
(Y signal) =>C255
Is there sync?
No
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U10 fail
Page 9-7
File No. SG-0219
No
Is picture on screen?
Check component 1
(Pb signal) C255
Is there sync?
No
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U10 fail
No
Is picture on screen?
Check component 1
(Pr signal) C255
Is there sync?
No
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U10 fail
No
Is picture on screen?
Check component 2
(Y signal) C258,R195
Is there sync?
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
No
Check U23
outnputpin 31
Input pin 13
Input clamp voltagepin 3(+5V)
Output clamp voltagepin 32(+5V)
VCC3pin 22,23(+5V)
Input_switch_selecthigh(+5V)
Yes
U13 fail
No
U23 fail
No
Input source fail
Page 9-8
File No. SG-0219
No
Is no blue color on screen?
Check component 2
(Pb signal) C260,R197
Is there sync?
No
Yes
Check U23
outnputpin 28
Input pin 15
Input clamp voltagepin 5(+5V)
Output clamp voltagepin 29(+5V)
VCC3pin 22,23(+5V)
Input_switch_selecthigh(+5V)
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U13 fail
No
U23 fail
No
Input source fail
No
Is no red color on screen?
Check component 2
(Pr signal) C254,R192
Is there signal?
No
Yes
Check U23
outnputpin 34
Input pin 11
Input clamp voltagepin 1(+5V)
Output clamp voltagepin 35(+5V)
VCC3pin 22,23(+5V)
Input_switch_selecthigh(+5V)
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
U13 fail
No
U23 fail
No
Input source fail
No
Is picture on screen?
Check component 2
(Y signal) C287,R212
Is there sync?
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
No
Check U24
outnputpin 31
Input pin 13
Input clamp voltagepin 3(+5V)
Output clamp voltagepin 32(+5V)
VCC3pin 22,23(+5V)
Input_switch_selecthigh(+5V)
Yes
U10 fail
No
U24 fail
No
Input source fail
Page 9-9
File No. SG-0219
No
Is no blue color on screen?
Check U24
outnputpin 28
Input pin 15
Input clamp voltagepin 5(+5V)
Output clamp voltagepin 29(+5V)
VCC3pin 22,23(+5V)
Input_switch_selecthigh(+5V)
No
Check component 2
(Pb signal) C288,R213
Is there sync?
Yes
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
No
U24 fail
U10 fail
No
Input source fail
No
Is no red color on screen?
No
Check component 2
(Pr signal) C284,R210
Is there signal?
Yes
No
Use GProbe connect
from main to PC.
Does scaler detect the signal?
Check U24
outnputpin 34
Input pin 11
Input clamp voltagepin 1(+5V)
Output clamp voltagepin 35(+5V)
VCC3pin 22,23(+5V)
Input_switch_selecthigh(+5V)
Yes
No
U24 fail
U10 fail
No
Input source fail
No
Is picture on screen?
Check U45
H sync output U45 pin4,R181
V sync output U45 pin8,R184
Is there signal?
No
Check U45
H sync input U45 pin1,R185
V sync input U45 pin5,R187
Yes
Check U45
pin 14 +3.3V
Yes
U45 fail
No
Check input source
Yes
No
No
U22 fail
Page 9-10
File No. SG-0219
No
Is picture on screen?
Check U45
H sync output U45 pin4,R181
V sync output U45 pin8,R184
Is there signal?
No
Check U45
H sync input U45 pin1,R185
V sync input U45 pin5,R187
Yes
Check U45
pin 14 +3.3V
Yes
U45 fail
No
Check input source
Yes
No
No
U22 fail
Page 9-11
File No. SG-0219
No
Is picture on screen?
No
Check C310,R275,R274
Is there signal?
No
No
Q28 fail
Yes
No
Q13 fail
Yes
Check:
1.C309 (signal AC coupled)
2.R276
3.R279(75ohm impedance)
Is there signal?
No
Check input source
No
Is picture on screen?
No
Check C308,R273,R274
Is there signal?
No
No
Q28 fail
Yes
No
Q10 fail
Yes
Check:
1.C309 (signal AC coupled)
2.R276
3.R279(75ohm impedance)
Is there signal?
No
Check input source
Page 9-12
File No. SG-0219
No
Is picture on screen?
No
Check C316,R286,R285
Is there signal?
No
No
Q29 fail
Yes
No
Q13 fail
Yes
Check:
1.C315 (signal AC coupled)
2.R282
3.R283(75ohm impedance)
Is there signal?
No
Check input source
No
Is picture on screen?
No
Check C316,R284,R285
Is there signal?
No
No
Q29 fail
Yes
No
Q10 fail
Yes
Check:
1.C315 (signal AC coupled)
2.R282
3.R283(75ohm impedance)
Is there signal?
No
Check input source
Page 9-13
File No. SG-0219
No
Is picture on screen?
No
Check C320,R293,R292
Is there signal?
No
No
No
Q30 fail
Yes
No
Q13 fail
Yes
Check:
1.C319 (signal AC coupled)
2.R297
3.R299(75ohm impedance)
Is there signal?
No
Is picture color ok?
No
Check input source
No
Check C328,R308,R307
Is there signal?
No
Q31 fail
Yes
No
Q13 fail
Yes
Check:
1.C327 (signal AC coupled)
2.R296
3.R298(75ohm impedance)
Is there signal?
No
Check input source
Page 9-14
File No. SG-0219
No
Is picture on screen?
No
Check C318,R291,R292
Is there signal?
No
No
No
Q30 fail
Yes
No
Q10 fail
Yes
Check:
1.C319 (signal AC coupled)
2.R297
3.R299(75ohm impedance)
Is there signal?
No
Is picture color ok?
No
Check input source
No
Check C326,R306,R307
Is there signal?
No
Q31 fail
Yes
No
Q10 fail
Yes
Check:
1.C327 (signal AC coupled)
2.R296
3.R298(75ohm impedance)
Is there signal?
No
Check input source
10
Page 9-15
File No. SG-0219
No
Is picture on screen?
No
Check C332,R316,R320
Is there signal?
No
No
No
Q33 fail
Yes
No
U13 fail
Yes
Check:
1.C335 (signal AC coupled)
2.R300
3.R302(75ohm impedance)
Is there signal?
No
Is picture color ok?
No
Check input source
No
Check C336,R319,R318
Is there signal?
No
Q32 fail
Yes
No
U13 fail
Yes
Check:
1.C333 (signal AC coupled)
2.R301
3.R303(75ohm impedance)
Is there signal?
No
Check input source
11
Page 9-16
File No. SG-0219
No
Is picture on screen?
No
Check C331,R313,R320
Is there signal?
No
No
No
Q33 fail
Yes
No
U10 fail
Yes
Check:
1.C335 (signal AC coupled)
2.R300
3.R302(75ohm impedance)
Is there signal?
No
Is picture color ok?
No
Check input source
No
Check C334,R317,R318
Is there signal?
No
Q32 fail
Yes
No
U10 fail
Yes
Check:
1.C333 (signal AC coupled)
2.R301
3.R303(75ohm impedance)
Is there signal?
No
Check input source
12
Page 9-17
File No. SG-0219
No
Check input source?
Is picture on screen?
Yes
No
Is picture on screen?
No
No
No
Check +3.3V_SW
FB19,FB20,FB21,FB22
U41+1.8V_HDMI1
Yes
No
D66 fail
or
D65 fail
Check crystal
Y2=28.322MHz
Yes
Check Q44
sourcehigh(3.3V)
No
Check Q44
Gatahigh(5V)
No
Q44 fail
Yes
Check U35 I2C bus
CSDApin 39
CSCLpin 40
No
No
I2C addr.R424
Check Block 2
Yes
Yes
Check U35 all power
No
Is picture color ok?
U35 fail
14
Page 9-18
File No. SG-0219
Block 2
start
HDMIs chip
communicate with
SM5964,is ok?
No
No
Yes
Check Y3
11.0592MHz
Yes
No
Check U20
pin 16+5V
Pin 10output select=high
No
U20 fail
Yes
No
Check R143,R144
U13 fail
15
Page 9-19
File No. SG-0219
Start
No
Support DDC2B
1.Analog cable ok?
2.Voltage of +5V_BUF ok?
3.Check U21
4.Is compliant protocol?
No
Support DDC2B
1.HDMI cable ok?
2.Voltage of VCC5_E2P_2ok?
3.Check U44
4.Is compliant protocol?
No
Support DDC2B
1.HDMI cable ok?
2.Voltage of VCC5_E2P_1 ok?
3.Check U37
4.Is compliant protocol?
Yes
Yes
End
Page 9-20
File No. SG-0219
PDP NO SOUND
PDP NO SOUND
Start
No
No
Yes
No
No
Check C436,C430
Yes
No
Block 3
Yes
speaker fail
No
U32 has output signal?
No
Check U32 input R372~R379
No
U32 Fail
No
Check U27,U28
+5V power
Pin 8,24,4
-5V power
Pin 25
No
Yes
Yes
Check U29 output
-5V_Npin 5
No
No
Check Q35MSTR2_SCL
Q37MSTR2_SDA
Is there signal?
U29 fail
Yes
No
Check U13
Q35,Q37 fail
No
U13 fail
Page 9-21
File No. SG-0219
Page 9-22
File No. SG-0219
POWER BOARD
Y DRIVER BOARD
X DRIVER BOARD
LVDS BOARD
CN12 CN13
W1
CN5
CN3 CN1
CN2
J8
J2
J7
MAIN BOARD
ATSC BOARD
W2
J4
IR BOARD
EMI
Fillter
Page 10-1
File No. SG-0219
J9
1
U26 MAX232A
ATXD_HUD
ARXD
3
J10
2
1
3
ATXD_HUD
VEDIO
ATXD
ARXD_HUD
ARXD_HUD
U40 24LC128
EEPROM(8051)
UC_SCL/UC_SDA
U20 4052
I/O SW
U38
SST89C58
HY5DU56822CT-D4
U17 DDR RAM CTZ
51_RXD/51_TXD
HY5DU56822CT-D4
U16 DDR RAM HUD
FL8532_CTZ
Frame Store
DDR Interface
ADATA[0:23]
W8
51_RXD/51_TXD
ARXD
ATXD
IPCLK0/AHS/AVS/AHREF_DE
HDMI1 AUDIO
CN17
U37 24LC02
EEPROM HDMI1
IPCLK0/AHS/AVS/AHREF_DE
IPCLK1/BHS/BVS/BDE
BDATA[0:23]
IPCLK1/BHS/BVS/BDE
HDMI2 AUDIO
VGA_SCL / VGA_SDA
W13
ANLOG DDC
U40 24LC02
EEPROM HDMI2
VS / HS
U45 74HCT14
Inverting Schmitt Trgger
R G B
CN16
U22 M61323FP
VEDIO SW
MSTR1_SCL/MSTR1_SDA
2 Wire
Controller
AIR_RAW_HS_CS/AIR_RAW_VS
SV4_CTZ
SV2_CTZ
SV3_CTZ/A1_CTZ
B1_CTZ/C1_CTZ
A4/B4/C4_CTZ
A3/B3/C3_CTZ
A2/B2/C2_CTZ
A4/B4/C4
NTSC CVBS(SV1_HUT)
W6
U23 M61323FP
VEDIO SW
A3/B3/C3_CTZ
U24 M61323FP
VEDIO SW
A3/B3/C3_HUD
ATSC Y
Pr Pb
MSTR1_SCL/MSTR1_SDA
Y Pr Pb
ATXD_HUD
ARXD_HUD
Y Pr Pb
Digital A
Input
Digital B
Input
COMP2_Audio_R/L
W11
CN13
LVDS
Display
Interface
Display
W1
Analog
input
OCM External
SRAM
XU1 A29LV320D
MEMERY_CTZ
NC7SB3157
U18 BUS SW
2 Wire
Controller
UART
AIR_RAW_HS_CS/AIR_RAW_VS
A4/B4/C4_HUD
A3/B3/C3_HUD
Analog
A2/B2/C2_HUD
SV4_HUD input
SV2_HUD
SV3_HUD/A1_HUD
B1_HUD/C1_HUD
A2/B2/C2
COMP1_Audio_R/L
CN12
JTAG Boundary
Scan
JTAG_BS_TCK/TDO/TMS/TDI/TRST
W7
JTAG Boundary
Scan
JTAG_BS_TCK/TDO/TMS/TDI/TRST
KEY PAD
CN5
GPIO
2 Wire
Controller
ADATA[0:23]
BDATA[0:23]
U21 24LC02
EEPROM VGA
UART
MSTR2_SCL/MSTR2_SDA
VGA_SCL / VGA_SDA
Frame Store
DDR Interface
I2CCM
U11 24LC32
EEPROM HUD
Serial ROM
Interface
U12 SST25VF040
FLASH 512K HUD
AudioAV1_R/L
IPCLK1/BHS/BVS/BDE
CVBS1
GPIO
CVBS2
W14
BDATA[0:23]
AudioAV2_R/L
NTSC CVBS(SV1_CTZ)
LVDS
Display
Interface
FL8125_HUD
W10
Y1/C1
Y2/C2
U37 CS3443
HDMI2 LR DAC
AUDIO
U36 CS3443
HDMI1 LR DAC
U46 IDTQS3253
HDMI1 AUDIO SW
U42 IDTQS3253
HDMI1 AUDIO SW
VGA_AUDIO_L/R
W5
MSTR2_SCL/MSTR2_SDA
HDMI1_AUDIO_L/R
HDMI2_AUDIO_L/R
AudioAV1_R/L
AudioAV1_R/L
COMP1_Audio_R/L
COMP2_Audio_R/L
VGA_AUDIO_L/R
ATSC Audio L/R
W13
AUDIO L/R
OUT
U28 MAX4550
AUDIO SW
4/2 I/O
U27 MAX4550
AUDIO SW
4/2 I/O
CH4_R/L
CH3_R/L
CH2_R/L
CH1_R/L
TUNER SIF
U32 P4450G
AUDIO
PROCESS
Lineout_R/L
U33 PT2308
AUDIO DRIVER
HLIN/HRIN
U34 PT2308
AUDIO DRIVER
TDA8946AD
AUDIO_AMP
J7
Speaker R
J8
Speaker L
W12
Headphone
TV/DTV
DTV
TV
TUNER
TUNER SIF
NTSC CVBS
U9
MT5112
U10
MT5351
FQD1236/F H-5
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File No. SG-0219