Sl.

N
o

Question

Text Book Page Nos.

DIGITAL SYSTEM DESIGN

Unit-4
1

.a)Discuss about Kohavi algorithm and design a two level ANDOR circuit that realizes the function F=X1.X2+ X1X3 X4+ X2X4.
Find a minimum test set for this network.
b) )Apply Kohavi algorithm and derive the minimal complete test
set for SA-0 and SA-1 faults for a given function
F(W,X,Y,Z)=WY+YZ+WXZ+XYZ.

T1

133-138
(material)

a) A combinational circuit is defined by the functions F1=m(3,

5, 6, 7 )F2=m(0,2,4,7). Implement the circuit with a PLA having
3 inputs,3 product terms and 2 outputs.
b) Explain the faults in PLA

T1

179

a) Explain the fault diagnosis process of

combinational logic circuit with an example.
b) What is the significance of Kohavi Algorithm?
Explain how it detects multiple faults ina two-level
network.

T1

123-134
133-138

Explain the circuit under test methods

a)path sensitization method
b) Boolean difference method
Explain the concept built in self-test

T1

128-133

T1

What are the fault classes and models explain each

with gates ?

T1

19599,457(t3)
179,meteria
l

5
6

Unit-5
1

a) Conduct a Homing experiment and determine

shortest homing sequence which identifies
the final state with an example?
b) Write short note on sequential test techniques.

T1

250

2
3

Explain the fault detection in sequential circuits?

Explain the following
a)circuit test approach
b)initial state identification
Explain the procedure for machine identification?
Explain the following with short description
a) distinguishing experiments
b) adaptive distinguishing experiments

T3

549,564

T2

meterial

4
5
6

NOTE: ALL ARE AVAILABLE IN DSD MATERIAL AND IN N BISWAS TEXT

T1N.N.BISWAS

T2--MIRON MOVICI
T3MATERIAl
DEGITAL DESIGN USING HDL
Sl.N
o

Question

Text
Book

Page Nos.

T2

(760-63)

T2

(807-808)

Unit-4
1
2
3
4
5
6

What is meant by synthesis? Explain the synthesis in logic

circuits.
What are the sequential logic circuits (F/F,latches) and explain
the synthesis of sequential logics ?
Explain the following
a) implicit state machines
b) explicit state machines
How the synthesis process performed in
a) registers
b)counters
Explain the concept synthesis in combinational logic

T2
T2

(739-740)

T2

(322-329)

T2

728-729

T2
T2
T2

743-747
760-772
750-753

T2

731-736

T2

729

Unit-5
1
2
3
4
5
6

Explain
a)need for testing logic circuits
b)fault model
What is built in self-test?
Explain the CAD TOOLS and give description?
Explain the operation of printed circuit board in VLSI
technology?
Explain the following
a) path sensitization
b)random tests
what is complexity of a test set and explain the synthesis in
testing of digital logic circuits ?

T1Bhaskars VHDL Primer

T2Digital Logic Design By Stephen Brown ,Tata Mc Grahill

VLSI DESIGN &TECHNOLOGY

Sl.N
o

Question

Text Book

Page Nos.

Unit-4
1

a) What are the various simulators used for

combinational logic design? Explain their need.
(b) Explain how the gate placement effects load
capacitance in fan-out of combinational logic

T3

(218-222)

a) Explain the technology independent and technology

dependant strategies of power
optimization used in sequential systems.
(b) Write notes on clocking disciplines.
a) What is meant by switch logic? Discuss about alternative
gate circuits.
(b) Explain how to determine resistive and inductive
interconnect delays of logic circuits.
Explain the design of arithmetic logic unit (ALU) ?
What are the other system considerations in sub system
design ?

T3

(249-53)

T3

(253-57)

T3
T3

(349-50)

4
5
6

T3

Unit-5t3
1

(a) Explain the design validations in the floor

planning methods.
(b) Describe the Placement and routing techniques
used in floor planning.

T3

(379-90)

2
3

Explain the chip designing methodologies give description ?

Explain the different types of architecture register transfer
design ?
Explain the floor planning methods and off chip connections
in floor planning .
write short notes on the following:
(a) Layout Synthesis.
(b) Hardware/Software Co-Design.
Explain the architectures for low power vlsi chips&
architecture testing .

T3
T3

(493-502)
(442-45)

T3

(403-408)

T3

(533-540)
566

T3

(502-510)

4
5
6

T1:PUCKNEL
T2:JOHN.P.VYEMUVA
T3. VLSI by Wayne wolf

CPLD & FPGA ARCHITECTURE AND APPLICATIONS

Sl.No

Question

Text Book

Page Nos.

T1

(27-29)

T1

(16-18)

Explain the device architecture in anti-fuise programmed

architecture ?
Explain the following actel architecture
a) actel 1
b) actel 2

T1

(28-30)

Explain the ACT 2 and ACT 3 Logic Modules.

T1

2.15
,folder

T1

(8-9)

Unit-4
1
2
3

The Actel ACT1 FPGA uses the following circuit shown

below. How would you
Implement the function Y = A+B+C?
Explain about anti-fuse programming technology with an
example ?
Write notes on the following.
a) ACTELs and their speed performance.
b) Parallel adder design using FPGA.

Unit-5
1
2
3
4
5
6

What are the applications over the FPGA architectures give

description?
Give brief description about following
a)general design issues
b)accumulators with act architecture
What are the sequential circuit examples of FPGAS ?
Explain the operation and architecture of fast DMA
controller?
Explain the following applications
a)fast video controller
b)position tracker for robot
Explain the designing of counter with act devices and give
application ?

T1: FPGA ARCHITECHTURE& APPLICATION BY STEPHEN BROWN

T2: DSD WITH FPGA &CPLD BY IAR GROUT
T3: CPLDFPGA FOLDER

CMOS ANALOG IC DESIGN

Sl.No

Question

Text Book

Page Nos.

T2

(355-369)

T2
T2
T2

(297-307)
(334-336)
(296-307)

Unit-4
1
2
3
4
5
6

Explain how the compensation of op-amps in cmos op-amp

devices?
Explain the any two measurements techniques in op-amps?
Explain the concept of cascode op-amps in CMOS.
Define PSSR? And how it will be in two stage op-amps?
Design a two stage operational amplifier with CMOS
implementation?
How a CMOS op-amp is designed? And give analysis?

Unit-5
1
2
3
4
5
6

What is comparator? Give its characterization?

Explain the following
a) two-stage comparators
b)open-loop comparators
Explain the discrete time comparators?
What are the procedures for improving the performance of
open-loop comparators?
What are the other open loop comparators explain in brief ?

T1: ANALYSIS & DESIGN OF ANALOG IC CIRCUITS by PAUL GRAY (SOFT COPY)
T2: DESIGN OF ANALOG CMOS IC CIRCUITS by BEHZAD RAZANI

CMOS DIGITAL IC DESIGN

Sl.No

Question

Text Book

Page Nos.

T1

(380,388)

Unit-4
1
2
3
4
5

Differentiate the high performance dynamic CMOS circuits

with CMOS circuits?
What is the basic principle of dynamic logic circuits and
explain the need of dynamic logic in digital era ?
Give complete description of dynamic CMOS transmission
gate logic? Give its circuits?
Explain the concept voltage bootstrapping?
What is a pass transistor? And explain the synchronous
dynamic pass transistor circuits?

T1
T1

(245-248)

Stephen
brown

(146-149)

Unit-5
1
2
3
4
5

What are the different types of semiconductor memories

give brief description?
Explain the array organization of RAM?
Explain the following
a) DRAM types
b) Leakage currents & refresh operation.
Explain the following in SRAM
a)leakage currents
b) SRAM cells implementation
Explain the two types of flash memories
a)NOR
B) NAND

T1: ken martin ,oxford university edition

T2: jan.p. rabey,PHI edition

T1

437

T1
T1

440
(458-63)

T1

(438-440)