UNIVERSITY OF CALIFORNIA

College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on Feb 6, 2004 by Gang Zhou (zgang@eecs.berkeley.edu)

Jan Rabaey

Homework #3 Solution

EECS141

Problem 1 VTC of Inverter

a) Figure 1a depicts the Id VOUT curve of a typical NMOS transistor
Figure 1b depicts the Id VOUT curve of a typical PMOS transistor
Assume we use these FETs to create a CMOS inverter. Using this family of
curves, graph the VTC, and calculate VM, VIL, and VIH. The values for VGS you
should use are 0, 0.5, 1, 1.5, 2, 2.5 (negative values for the PMOS). There are
actually 6 graphs per device, the 0 and 0.5 graphs lay pretty much on top of each
other since the current is near 0 for those gate values. These are normal PMOS
and NMOS devices so the VDS values for the PMOS should actually be negative
as well as the current. They were just displayed this way so it would be easier for
you to work on them.

Top: Figure 1a, Bottom: Figure 1b

The VTC is plotted below in Figure Solutions1. Note that we plotted this graph directly
from SPICE. However, you can get the same graph (with lower resolution but still ok)
from the method we used in Hw#2.

Figure Solutions 1
The simplest way to determine the input voltages is to note the points on
the curve where the slope is 1, which was defined in class (of course, just
estimate it from your curve since its resolution is not very good). VM can
be determined by noting the point of intersection between the VTC and a
linear curve with slope = 1.
VIL = 1.1V
NML = 1.1V
VIH = 1.4V
NML = 1.1V
VM = 1.25V
b) If we increase the W/L ratio of the pull-down NMOS (leaving the PMOS size
fixed), in which direction will the VTC shift?
The VTC will shift to the left.
c) If instead, we increase the W/L ratio of the pull-up PMOS (and leave the NMOS
the original size), in which direction will the VTC shift?

The VTC will shift to the right.

d) Please explain how the resizing in b) and c) will affect the above I-V curves in
each case and give an intuitive explanation of how this affects the VTC of each.
If we increase the W/L of an NMOS or PMOS, it moves the I-V curves up (higher
magnitude of current for same input voltage). As such, a larger NMOS gives
more pulldown strength, while a larger PMOS gives more pullup strength.
If youre interested, the input SPICE Deck used to create the family of curves and the VTC
seen in Figure Solution can be found below. Note that those are old files. So if you want to
run them youll need to first modify the model link to the existing one.
Input Spice Deck for Prob. 1, NMOS Id-Vout Characteristics:

________________________________________________________
Hw #3, Prob. 1 - NMOS (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 0
vds vds 0 0
m1 vds vin 0 0 nmos w=1.0u l=0.25u
.dc vds 0 2.5 0.1 vin 0 2.5 0.5
.plot LX4(m1)
.option post=2 nomod
.END_____________________________________________________

Input Spice Deck for Prob. 3, PMOS Id-Vout Characteristics:

_________________________________________________________
Hw #3, Prob. 1 - PMOS (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 0
vds vds 0 0
m1 vds vin vdd vds pmos w=3.0u l=0.25u
.dc vds 0 2.5 0.1 vin 0 2.5 0.5
.plot LX4(m1)
.option post=2 nomod
.END______________________________________________________

Input Spice Deck for Prob. 3, VTC:

_________________________________________________________
Hw #3, Prob. 1 - VTC (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 pulse 0 2.5 0 5n 5n 10n 10n
m1 vout vin vdd vdd pmos w=3.0u l=0.25u

m2 vout vin 0 0 nmos w=1.0u l=0.25u

.dc vin 0 2.5 0.1
.tran 1n 50n
.option post=2 nomod
.END________________________________________________________________________

Problem 2 Inverter Delay Calculation

a) For inverter A, prove that when the output voltage characteristics satisfy the
following relation: VM (VOH + VOL)/2, the delay for output to rise from VOL to
VM (or fall from VOH to VM) can be modeled as tp = 0.69ReqCL, even if the output
swing is not rail to rail. Here Req is the equivalent resistance of the device
driving the output, and CL is the load capacitance on the output node.
The capacitor charging process can be modeled as:

VC ( t ) = V ( ) + V ( 0 ) V ( ) e

t
Req CL

where V() is the capacitor voltage at the end of the charging

(when t = ), and V(0) is the capacitor voltage at the beginning
of the charging (when t = 0).
solve:

+
E

CL
Req

In this problem during the output low to high transition, V(0) = VOL, V() = VOH,

VC = VM = VOH + VOL VOH e

t
Req C L

tp = 0.69ReqCL

b) Evaluate the propagation delays of the two inverters by measuring the delay as the
time between VIN = VM and VOUT = VM. You will need to find VM, VOH and VOL
for each of these two inverters first. Use the switch approximation analysis of the
MOS transistor presented in class (Req = (RM + RVOH) / 2) to estimate tpLH, and
same for tpHL.
Find VOH, VOL, VM using the quadratic equations.
All-NMOS inverter:
Calculate VOH Set VIN = 0, M1 is off
Since ID1 = ID2, M2 is also off, which happens when
VGS2 - VT2 = VDD VOH VT2 = 0
Solve for VOH get

+
VC

Where VSB = VOH.

Calculate VOL Set VIN = VDD, then M2 is saturated and M1 is likely in linear
region.
VDS

Method 1: Using math software the equations can easily be solved. VOL = 0.374V is
the accurate solution of the equation.
Method 2: Hand analysis with approximations can also produce the result with good
accuracy.
i)

First using the Taylor series approximation to get rid of the square root
calculation,

ii)

Then ignore the channel length modulation by assuming temporally that

= 0.

With these two approximations the equation can now be solved by hand easily =>
VOL = 0.335V.
Generally speaking this result is already accurate enough because the error
introduced by ignoring the channel length modulation is only a factor of (1+
(VDD-VOL)) = 1.15 1.
iii)

However we can still improve the accuracy of the result by hand solving
the same equation in ii) with ID2 multiplied by a factor 1.15. This would
give us the result:

VOL = 0.372V, which is very close to the Matlab solution.

This is a simple illustration on how proper approximations in engineering
analysis can help us simplify the calculations, while still producing results with
good accuracy.

VOL = 0.374V => VDS1 < VGS1 VT0 = VDD VT0

Thus M1 is in linear region. Our previous assumption is correct.
Calculate VM Set VIN = VOUT = VM. Both M1 &M2 are in saturation.

Solve ID1 = ID2 => VM = 1.27V

CMOS inverter:
Calculate VOH, VOL
When VIN =0, NMOS is off, PMOS is on and pull VOUT all the way up to VDD.
Similarly, when VIN = 3.3V, PMOS is off, NMOS is on and pulls VOUT all the way
down to ground.
Thus VOH = 3.3V, VOL = 0.
Calculate VM Set VIN = VOUT = VM. Both M1 &M2 are in saturation

Solve IDn = IDp => VM = 1.68V

Find Propagation Delay
Inverter A:
Calculate Req during pull down (OK if you also find an Req of M2 and then find
Req=Req1//Req2, but Req2 >> Req1 anyway)
At VIN = VDD = 3.3V, VOUT = VOH = 2.24V, M1 is in linear region.
W
1
2
I D = k n 1 ((V IN VT 0 )VOH VOH )(1 + VOH ) = 236.1uA
L1
2
R(VOH) = VOH / ID = 9.5K
At VIN = VDD = 3.3V, VOUT = VM = 1.27V, M1 is in linear region.

W1
1 2
((V IN VT 0 )VM VM )(1 + VM ) = 167.3uA
L1
2
R(VM) = VM / ID = 7.6K
I D = kn

Pull down Req = (R(VOH)+ R(VM))/2 = 8.55 K

Calculate Req during pull up:
At VIN = 0, VOUT = VOL = 0.374V, M2 is saturated.
VT 2 = VT 0 + ( | 2 F + VOL | | 2 F | ) = 0.71V
k n W2
(VDD VOL VT 2 ) 2 (1 + (V DD VOL )) = 56.3uA
2 L2
R(VOL) = (VDD - VOL) / ID = 52K
ID =

At VIN = 0, VOUT = VM = 1.27V, M2 is saturated.

VT 2 = VT 0 + ( | 2 F + VOM | | 2 F | ) = 0.9V
k n W2
(VDD VM VT 2 ) 2 (1 + (VDD VM )) = 14.1uA
2 L2
R(VM) = (VDD -VM ) / ID = 144K
ID =

Pull up Req = (R(VOL)+ R(VM))/2 = 98 K

tpLH = 0.69 RupCL = 10.1ns
tpHL = 0.69 RdownCL = 0.88ns
tp = (tpLH + tpHL)/2 = 5.49ns
Inverter B:
Calculate Req during pull down:
At VIN = VDD = VOH = 3.3V, , Mn is saturated.
k W
I D = n n (VIN VT 0 ) 2 (1 + VOH ) = 84.9uA
2 Ln
R(VOH) = VOH / ID = 38.9K
At VIN = VDD = 3.3V, VOUT = VM = 1.68V, Mn is in linear region.
W
1 2
I D = k n n ((VIN VT 0 )VM VM )(1 + VM ) = 67.7uA
Ln
2
R(VM) = VM / ID = 24.8K
Pull down Req = (R(VOH)+ R(VM))/2 = 31.85 K
Calculate Req during pull up:
At VIN = VOUT = VOL = 0, Mp is saturated.

ID =

k p Wp

(VDD VOL VT 0 ) 2 (1 + (VDD VOL )) = 101.8uA

2 Lp
R(VOL) = (VDD - VOL) / ID = 32.4K

At VIN = 0, VOUT = VM = 1.68V, Mp is in linear region.

Wp

1
((VDD VT 0 )(VDD VM ) (VDD VM ) 2 ))(1 + (VDD VM )) = 74.7uA
Lp
2
R(VM) = (VDD -VM ) / ID = 21.7K

ID = kp

Pull up Req = (R(VOL)+ R(VM))/2 = 54.1 K

tpLH = 0.69 RupCL = 5.6ns
tpHL = 0.69 RdownCL = 3.3ns
tp = (tpLH + tpHL)/2 =4.45ns

c) Verify tpLH and tpHL using HSPICE. (Note that there may be slight difference
between your SPICE and hand calculation results, because approximations are
used in our hand analysis. You can think about the reason for the discrepancy
while you are not required to do so in this homework.)
The SPICE deck used to calculate the tPLH and tPHL of inverter A:
____________________________________________________________________________
.model nmos NMOS VTO=0.6 GAMMA=0.5 PHI=0.6 KP=20E-6 LAMBDA=0.05
.model pmos PMOS VTO=-0.6 GAMMA=0.5 PHI=0.6 KP=7E-6 LAMBDA=0.1
m2 out vd vd 0 nmos w=1.2u l=1.2u
m1 out in 0 0 nmos w=3.6u l=1.2u
vin in 0 PULSE(0 3.3 5n 10p 10p 40n 80n)
vdd vd 0 3.3
c1 out 0 150f
.tran 1n 100n
.meas t1 trig v(in) val=1.27 cross=1 targ v(out) val=1.27 cross=1
.meas t2 trig v(in) val=1.27 cross=2 targ v(out) val=1.27 cross=2
.option post=2 nomod
.op
.end

Inverter A:

HSPICE
HSPICE
HSPICE

tpLH = 5.03ns
tpHL = 0.87ns
tp = (tPLH + tPHL)/2 = 3ns

(Hand tpLH = 10.1ns)

(Hand tpHL = 0.88ns)
(Hand tp = 5.49ns)

Inverter B:

HSPICE
HSPICE
HSPICE

tpLH = 4.7ns
(Hand tpLH = 5.6ns)
(Hand tpHL = 3.3ns)
tpHL = 2ns
tp = (tpLH + tpHL)/2 = 3.35ns (Hand tp = 4.45ns)

Here comes the fun part: although the HSPICE takes more delay factors into account
including the parasitic capacitances of the devices which should lead to larger delay,
it actually produces much smaller delay numbers than our hand calculations. Why is
that?
Lets look at the tPLH of inverter A which has the discrepancy of almost a factor of 2
as an example. The Device Resistance vs. Vds curve of M2 in inverter A is plotted as
below. It can be easily observed that the two points of M2 resistance at VOUT = VOL =
0.374V and VOUT = VM = 1.27V match our calculations perfectly. However the non
linear increase of resistance with Vds leads to the pessimistic results in our Req
calculation the actual Req should be smaller than the linear average result that we
got. Therefore the subsequent delay calculation turns out to be pessimistic than the
reality.

d) Explain why M2 is sized to be much smaller than M1 in the first (all-NMOS)

circuit? Briefly comment on that. What disadvantages on performance does the
inverter with NMOS-load have compared to the CMOS inverter?
M1 has to be sized much larger than M2 in this circuit because during the pull down
operation the M1 must be strong enough to pull the output voltage down to VOL,
which should be close to 0. However small M2 results in the weak pulling up drive,
so that the VTC of this inverter is very unsymmetrical with delay on one transition
almost 10 times larger than the other.
Though the average propagation delays of the two inverters are similar, the
unsymmetrical timing characteristics of inverter A are very undesirable in achieving

good delay path balancing. Also the long pull up time to VOH brings even degraded
noise margin or long settling time, which worsen its performance.
Problem 3 Computing the MOSFET Capacitances

a) It is always good to get a feel for design rules in a layout editor. Fire up Cadence
Virtuoso with 0.24um technology. Place a minimum sized NMOS transistor and
examine the dimensions. The layers are listed and shown below. Determine and
list the following:
a. Minimum Transistor Length
b. Minimum Transistor Width
c. Minimum Source/Drain Area
d. Minimum Source/Drain Perimeter
Please list the design rules you come across that lead to your results.

poly
nfet

ct
ndif

Rules are:
i)
Poly minimum width = 0.24um
ii)
Minimum active width = 0.36um
iii)
Minimum contact size = 0.24um*0.24um
iv)
Minimum spacing from contact to gate = 0.24um
v)
Active enclosure of contact = 0.12um
See http://www.mosis.org/Technical/Layermaps/lm-scmos_scn5m.html for more
details
Use these values
a. L = 0.24um
b. W = 0.36um (0.48um ok just add or subtract a 0.12um*0.12um
diffusion area at the next-to-the-gate corner of each of the diffusion regions
(Source/Drain), this also means add/subtract a diffusion area under the poly (gate)
in order to form a channel)
c. Ldrain = 0.24um+0.24um+0.12um = 0.6um
AD=AS= 0.48 * 0.6um-0.12um * 0.12um= 0.2736 um2 (0.288 um2 ok)
d. PD=PS =0.6um*2+0.48um+0.12um= 1.8um (1.68um ok)

b) We desire a minimum sized CMOS inverter with a symmetrical VTC

(VM=VDD/2) with 0.24um technology. Calculate the following for the pull-up
PMOS transistor in the design.
a. Minimum Transistor Length
b. Minimum Transistor Width
c. Minimum Source/Drain Area
d. Minimum Source/Drain Perimeter
Assume the following:
VDD = 2.5V, VM = 1.25V, and refer to Table 3.2 in the Book
We will use equation 5.5 from the book:

kn'VDSAT , n(VM Vt , n 12 VDSAT , n)

(W / L) p
=
= 3.48
(W / L) n kp 'VDSAT , p (VDD VM + Vt , p + 12 VDSAT , p )
The gate lengths will be identical and thus we can calculate
a. Lp = 0.24 m
b. Wp = 0.36 m *3.48 = 1.25 m
c. AD=AS= 0.6 m * 1.25m = 0.75 m2
d. PD=PS = 0.6 m *2 +1.25 m = 2.45 m
c) Using the same minimum size inverter from part b), determine the input
capacitance (i.e. the load it presents when driven). Please calculate the
capacitance during a transition. From these, determine the total load capacitance
that the inverter presents. Refer to Table 3.5 for capacitor parameters.
*Hint: Consider the Miller effect
You have three capacitances per transistor to consider on an inverter for input
capacitance, gate to bulk, gate to source and gate to drain. Cox = 6.0fF/m2
Cin = Cgs12 + 2Cgd12 + Cgb12
(The factor of 2 is due to Miller effect)
During the transition M1 & M2 operate in either linear or saturation region, thus
Cgb = 0.
Cgd12 = Cgdo + Cgdc
Cgs12 = Cgso + Cgsc
PMOS:
Overlap cap.
Cgdop = COWP = (0.27 fF/m)*(1.25 m) = 0.338 fF
Cgsop = COWP = (0.27 fF/m)*(1.25 m) = 0.338 fF
Channel cap.
Saturated
Cgdcp_sat = 0, Cgscp_sat = 2/3 (CoxLpWp) = 1.20 fF
Linear
Cgdcp_lin = Cgscp_lin = 1/2 (CoxLpWp) = 0.90 fF
NMOS:

Overlap cap.
Cgdon = COWn = (0.31 fF/m)*(0.36 m) = 0.112 fF
Cgson = COWn = (0.31 fF/m)*(0.36 m) = 0.112 fF
Channel cap.
Saturated
Cgdcn_sat = 0, Cgscn_sat = 2/3 (CoxLnWn) = 0.346 fF
Linear
Cgdcn_lin = Cgscn_lin = 1/2 (CoxLnWn) = 0.259 fF
The channel capacitances of MOSFET change with the operation region. Thus in
this problem the equivalent input capacitance is calculated as the average
capacitance during the transition.
For an input high-to-low transistion ( Vout from 0 to Vdd/2),
Operation Region 1
Operation Region 2
PMOS
Saturated
Saturated
NMOS
Linear
Saturated
At operation region 1,
Cin1 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgdcp_sat + Cgdcn_lin) + Cgscp_sat + Cgscn_lin
= 3.327 fF
At operation region 2,
Cin2 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgdcp_sat + Cgdcn_sat) + Cgscp_sat + Cgscn_sat
= 2.896 fF
Taking average of the two operation regions,
CinHL = (Cin1 + Cin2)/2 = 3.112fF

During an input low-to-high transistion,

Operation Region 1
PMOS
Linear
NMOS
Saturated

Operation Region 2
Saturated
Saturated

At operation region 1,
Cin1 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgdcp_lin + Cgdcn_sat) + Cgscp_lin + Cgscn_sat
= 4.396 fF
At operation region 2,
Cin2 = Cgsop + Cgson + 2(Cgdop + Cgdon) + 2 (Cgdcp_sat + Cgdcn_sat) + Cgscp_sat + Cgscn_sat
= 2.896 fF
Taking average of the two operation regions,
CinLH = (Cin1 + Cin2)/2 = 3.646fF

NOTE!!!!!!
The Miller effect is included in the calculations purely because the inverter in
question is unloaded by anything external. THIS WILL RARELY OCCUR
IN REALITY!!!! Only in this very special unloaded case does an inverter
have this Miller multiplication seen as part of its input capacitance.

d) Using the g25 model provided in /home/ff/ee141/MODELS/g25.mod, please

verify the accuracy of your results in part c by determining the total input
capacitance in a high-low and a low-high transition with HSPICE and comparing
with your total capacitance in part c. Turn in your HSPICE input deck.
You'll notice there are four corners, TT, FF, SS, FS, and SF. These represent the
different variation extremes we can expect due to process variations. For
example, TT stands for NMOS: typical, PMOS: typical. FS stands for NMOS:
fast, PMOS: slow etc. For this homework, please use the TT model.
To use these models, include the following in your HSPICE deck:
.lib '/home/ff/ee141/MODELS/g25.mod' TT
___________________________________________________________________________
HW #3, prob. 3d

Measuring CinLH of Inverter

*****begin DEFINITIONS*****
.lib '/home/ff/ee141/MODELS/g25.mod' TT
.param vddp = 2.5
.param ln_min = 0.24u
.param lp_min = 0.24u
*****end DEFINITIONS*****
VDD vdd 0 vddp
IIN 0 in 1u
M1 out in vdd vdd pmos L=lp_min W=1.25u AD=0.75p AS=0.75p PS=2.45u
PD=2.45u
M2 out in 0 0 nmos L=ln_min W=0.36u AD=0.2736p AS=0.2736p PS=1.8u PD=1.8u
.ic v(in) = 0
.meas t1 when v(in)='vddp/2' cross=1
.meas CinLH param='1u*t1/(vddp/2)'
.options post=2 nomod
.op
.tran 0.1ns 15ns
.END
HW #3, prob. 3d

Measuring CinHL of Inverter

*****begin DEFINITIONS*****
.lib '/home/ff/ee141/MODELS/g25.mod' TT
.param vddp = 2.5
.param ln_min = 0.24u
.param lp_min = 0.24u
*****end DEFINITIONS*****
VDD vdd 0 vddp

IIN 0 in -1u
M1 out in vdd vdd pmos L=lp_min W=1.25u AD=0.75p AS=0.75p PS=2.45u
PD=2.45u
M2 out in 0 0 nmos L=ln_min W=0.36u AD=0.2736p AS=0.2736p PS=1.8u PD=1.8u
.ic v(in) = vddp
.meas t1 when v(in)='vddp/2' cross=1
.meas CinLH param='1u*t1/(vddp/2)'
.options post=2 nomod
.op
.tran 0.1ns 15ns
.END

SPICE calculates:
Hand calculations:

CinLH = 3.59 fF
CinLH = 3.65 fF

CinHL = 2.85 fF
CinHL = 3.11fF

CinLH is larger than CinHL due to the fact that the gate capacitance decreases when VGS
is near VT. During the H-L transition, the PMOS gate cap is at its minimum. Thus,
since the PMOS transistor is considerably larger than the NMOS, CinHL is smaller
than CinLH.

e) Determine VIH, VIL , NMH, and NML.

*Hint: The 2 parameters r and g vary proportionally with transistor width. The
equations given are derived with the minimum width in mind. (Please refer to
eqn. 5.3 and 5.10 in the book for r and g)
First find r using eqn. 5.3 in the book and then g using eqn. 5.10. Remember to
account for the size difference by applying direct ratio.
r = 1.44
g = 30.2
VM = VDD/2 = 1.25V
Then use equations 5.7 to solve:
VIH = VM + (2.5-VM)/g = 1.29V
NMH = VDD VIH = 1.21 V

VIL = VM VM/g = 1.21V

NML = VIL = 1.21V