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I.
INTRODUCTION
206
Figure 2. Schematic of the proposed low-voltage charge pump along with the control signals. V in the timing diagram represents the voltage at VIN.
207
With an area of 35,000 m2, the total dual-metal-insulatormetal capacitance that can be realized, including area for
routing is about 100 pF. For the 3-stage LCP, with
complementary cross-coupling branches, the CP capacitance
for each stage is about 16 pF.
The charge pump circuit has been simulated with the
extracted parasitic capacitances and resistances from the
layout. For an input voltage of 100 mV, the system is capable
of generating the required control signals for startup.
However, the low gain in the CP stages reduces the efficiency
to 34%. The usable range of VIN starts from 125 mV, where
the efficiency is close to 70%. The output voltage reaches its
steady-state value in less than 1ms. At VIN of 125 mV, the RO
oscillates at 360 kHz and the output ripple voltage is 1.2 mV
for a DC load current of 0.1 A.
Fig. 4 presents the 3-stage CPs output voltages across
low-voltage inputs for different load conditions. The CP
provides a gain of about than 3 V/V for input voltages greater
than 125 mV. The conversion efficiency of the CP is given by
p
I L VOUT
I Power VIN
K
N 1
(1)
N2
N 1 K
208
0.8
80
0.7
70
0.6
Efficiency,
In this work, NOV clock phases along with efficient gatecontrol signals reduce the reversion loss. Some of the gate
control strategies for efficient charge pumps discussed in [12]
are adapted to this CP. The gate control signals for the
switches are derived from the complementary cross-coupled
stages using level-shifters and from two NOV clock phases.
The gate voltage for the N-th stage PMOS switch is designed
to swing from (N-1)VIN to (N+1)VIN in two steps to control
the transfer of charge to the subsequent stage.
0.5
0.4
0.3
IL = 0 A
0.2
IL = 50 nA
0.1
IL = 0.1 A
0
0.05
0.1
0.15
0.2
Input Voltage (V)
0.25
60
50
IL = 0 A
40
IL = 50 nA
30
IL = 0.1 A
20
0.05
0.1
0.15
0.2
Input Voltage (V)
0.25
80
1.2
70
Efficiency,
1.4
0.8
0.6
IL
I L == 00A
A
IL
I L == 50
50nA
nA
IL
I L == 0.1
0.1A
A
0.4
0.2
0
0.05
0.1
0.15
0.2
Input Voltage (V)
60
50
IL
I L == 00A
A
I L == 50
50nA
nA
IL
I L == 0.1
0.1A
A
IL
40
30
20
0.05
0.25
0.1
0.15
0.2
REFERENCES
0.25
[1]
1.4
80
1.2
75
70
Efficiency,
0.8
0.6
Vin = 125 mV
Vin = 150 mV
Vin = 175 mV
Vin = 200 mV
0.4
0.2
0
4
6
Number of CP stages, N
[3]
65
60
55
Vin = 125 mV
Vin = 150 mV
Vin = 175 mV
Vin = 200 mV
50
45
40
[2]
4
6
Number of CP stages, N
[4]
8
[5]
[6]
Refer
ence
[8]
[9]
[10]
[11]
CONCLUSION
TABLE I.
[7]
[12]
[13]
[14]
Startup
mechanism
Converter
Topology
Ext.
Parts
Startup
Voltage
Input
Voltage
Output
Voltage
% Efficiency
Output
Ripple
Area
(mm2)
Process
Charge pump
LCP (N=3)
None
270 mV
450 mV
1.40 V
58 %*
15 mV
0.42
130-nm
Inductor
based
LCP,
inductor
ECP (N=3)
Cap.
95 mV
100 mV
0.90 V
72 %*
N/A
0.17
65-nm
N/A
180 mV
180 mV
0.74 V
N/A
N/A
0.29
65-nm
[8]
None
150 mV
150 mV
0.85 V
30 % (sim.)
N/A
N/A
65-nm
This
work
Charge pump
(IL= 0.1 A)
LCP (N=3)
None
125 mV
125 mV
0.35 V
65 (est.) / 62 % (sim.)
0.1
130-nm
LCP (N=7)
None
125 mV
125 mV
0.61 V
59 (est.) / 51 % (sim.)
1.2 mV
(IL= 0.1
A)
0.15
130-nm
[3]
[6]
[7]
209