Signature of Invigilator

Signature of Examiner

Marks Obtained:

NAME:

ROLL NO.
GATE EC BY RK Kanodia

Logic Circuits

Q1

D1

D2

Q2

Chap 4.3

13. The counter shown in fig. P4.3.13 counts from

Q1

Q2

Q1

D1

D1

D2

Q2

A
B

Q1

1. The modulus of a 4-bit Ring CounterC is

(a) 4 (b)Q28 (c) 16 (d) 15

Q1

(A) 0 0 0 to 1 1 1
2. The modulus of a 4-bit Johnsons
Counter is
Y
Q
(C) 1 0 0 to 0 0 0
1(a) D4
2 (b) 28 (c) 16 (d) 15

Q1

IIB. Tech II MidTerm Examinations: Objective Exam AY 2014-2015

Time: 20 Minutes Subject: S.T.L.D
Branch:E.E.E Max Marks: 10
C following
B CLR K Each question
A CLR K carries mark.
Answer the
Questions.
CLR K

(B) 1 1 1 to 0 0 0
(D) 0 0 0 to 1 0 0

14. to
Themod-numberoftheasyncr
3. How many 21 MUXS required
implement 10241 MUX
Q2
shown in fig. P4.2.13 is
(a) 10 (b)
11 (c) 1023 (d) 1024
J

4.5.QThe
forT0crictically
damping
series of
RLC
circuit are required
Q
To condition
count from
to 1024
how
many innumber
flip-flops
All J.K. input are HIGH
(a) 11 (b) CLK
10 (c) 12
B (d) 1023.
A
(A) R=2LC
(B) R= 4 L/C
(C) R^2 =4 L/C (D) R^2 =4 LC
Q and a 4 bit synchronous counter are made by flips flops having a propagation delay
6.Q A 4 bit ripple counter
Fig.P4.3.14
5. Fig.P4.3.11
Aofseries
circuit
R=15
ohms
, a counter
constantand
voltage
of 15V is applied
at t=o
10 nsRC
each.
If having
the worst
case
delayand
in L=
the0.2F
ripple
the synchronous
counter
be R and S
(A) 24
(B) 48
the
expression
for i(t) is
respectively,
then
counter
(C) 25S=10ns (c) R=10ns (D)
36
(a) 1.5e^(-t/3)
R=10ns, S=40ns
(b)e^(-t/3)
R=40ns,
,S=10ns
(d) R=40ns, S=40ns
(A)
(B) 15
(c) 1.e^(-t/3) (D) e^(-3t)
counter
T

D2

D3

the pulse
at is
z in
the network
of the pulse at 15.
z inThe
thefrequency
networkofshown
in fig
6. The time constant of the
circuit having R=5ohms L=0.2H is
Chap 8

7.00,
The
ate sequence
10, frequency
01, 00.....

shown
in
Chap 8
Analog and Digital

ate sequence 00, 10, 00, 10, 00 Analog

...... and Digital

(A) 2sec

ounter shown in fig. P4.3.12 is a

NOTES

Ring Counter
Counter
160 kHZ
MCQ
8.98
*
MCQ 8.98*Fig.P4.3.15
at

Mod-25
Ripple Counter

4-Bit Johnson
Counter

ripple
counter shown(B)
in 160
figure
(a)50%
10 HZ
(b) 160 HZ
5 HZ
(d)
40 HZ(C)
(A)The
10 Hz
Hz is made up of negative edge
(A)
efficiency
(B) (C)
100%
efficiency
20% efficiency
(D) 25%
triggered J-K
flip-flops.
The signal levels
at J efficiency
and K inputs of all
(C) 40 Hz

J
C

]2

]3

]4

[[ ] ]

(D) 5 Hz

the flip
flops are
logic triggered
1. Assume all
outputs are
8. The ripple counter shown in figure
is made
up maintained
of negativeat edge
J-Ktheflip-flops.
The signal levels
1 is applicable to
J
J
8.Q Reciprocity
Q theorem
cleared
just prior
to
applying
the clock
signal.
at J and K inputs of all the flip
are
maintained
logic
Assume
all the outputs are cleared just
16. flops
The three-stage
Johnson at
counter
as1.shown
in fig.
(A)
only
( B)signal
Bi-lateral
network
only
(C) linear/
bilateral networhonly (D) neather of the two
Blinear
A
prior
to network
applying
the clock
module
no. of
the counter
is:-

]6

[ ]
[[ ] ]

NOTES

7. Max power transfer occur

fig. P4.3.15. is

10-Bit (D)w 2.5Sec

4-Bit Parallel
Electronics
1sec
(C)Electronics
0.04 sec

( B)

]1

2
3
4
4. The Output Y of a 2-bit Comparator0 is logic 11 whenever
the 2-bit
input
A is greater than 2-bit input
B .The Number of combinations for which the logic 1 is (a) 4 (b) 5 (c) 10 (d) 6
K CLR
K CLR
K CLR
K CLR
K CLR

ircuit shown in fig. P4.3.11 is

CLK

[
Fig.P4.3.13

[ ]
[[ ] ]

P4.2.16
is clocked
at acounter
constantis:frequency of fc from the
module
no. of the

[ ]

Q
1is a property
K
K
starting
state of with
Q2Q1Q0 = 101. The frequency of output
9.Q mutual
inductance
associate

(A) only one

Fig.P4.3.12

8 up counter
10.

CLK

Q2Q1Q0 will be

(B) two or more coil

(C) two or more coil with magnetic (D) none

Q
J
J
J
The effictive value of an triangular wave
of Qalternative
quaninty
forQ peak value a is

8 down counter

6 up counter

(A) a/2

(B) a

(C) a/v3 (D) av3

K2

Q2

K1

Q1

K0

Q0

[ ]

CLK

6 down counter

11. For the below fig the polarity of(A)

the
7 mutual voltage is
(a) 7 (b) 5 (c) 8 (d) 4
Fig.P4.3.16
(C) 4

[[ ] ]

(B) 5
(D) 8

www.gatehelp.com

9. How
many 38
to implement 416 decoder
(A) Positive
(B) decoders
Negative required
( C) none
(a) 3 (b) 2 (c) 4 (6)
MCQ 8.99*

Page
218

10. The type of Flip-Flop used in a In

shift
Registers
is switch

Figure
, the ideal
S is switched on and off with a switching
. The
switching
time period is T = tON + tOFF s.
f = 10 kHz(d)
(a)SR Flip-Flop (b) D Flip-Flopfrequency
(c) T Flip-Flop
JK
Flip-Flop
The circuit is operated in steady state at the boundary of continuous

12.The
equivalent
oftoagenerated
given network
will so
have
F0 capacitor
11. TheLaplace-transformed
number of T flip-flops
required
a periodic
sequence
2
5 replaced
4 0 is
and discontinuous
conduction,
that(8/5)
the inductor
current
i6 isas3 by
(a)2 (b) 4 (c) 3 (d) 2
shown in Figure. Values of the on-time tON of the switch and peak
(A) 8/5 S (B) 5/8 S (C) 8/5S (D) 5/8S
current ip . are
12. A Flip-Flop is a Multi-vibrator
(a) Mono-Stable (b)Astable (c) both (d) Bi-stable
(A) 240 V

(B) 120 V

(C) 60 V

(D) 30 V

]10

[[ ] ]

11

]12

13. Number of parity bits required for 13-bits data word is

(a)5 (b) 3(c) 4 (d)2

]13

14. In Hamming Code Sequence number of parity bits are 6 for a range of data bits
(a)58-120 (b) 25-57 (c) 12-126 (d) 5-11

]14

15. In T Flip-Flop ,the output toggles when input T is

(a) 0 (b) 0 or 1 (c) 1 (d) dont care

]15

16. The Characteristic Equation Q(t+1) for SR Flip-Flop is

17. The Characteristic Equation Q(t+1) for JK Flip-Flop is
18. The Characteristic Equation Q(t+1) for T Flip-Flop is
19. The Characteristic Equation Q(t+1) for D Flip-Flop is
20. Race Around Condition will happen in Flip-Flop

II B.TECH II MID TERM EXAMINATIONS : DESCRIPTIVE EXAM

TIME :90 MIN SUBJECT ::STLD

AY:2014-2015

SET-1

BRANCH :EEE MAX.MARKS::30

ANSWER ANT THREE OF THE FOLLOWING QUESTIONS.

1. (a) Design a 4 bit binary UP/DOWN ripple counter.

(b) Draw the neat diagram of 4-bit Johnson counter and draw the relevant output wave forms.
SYNCHRONOUS (CLOCKED) SEQUENTIAL CIRCUITS

2. Complete the timing diagram for the circuit given below.

3.

257

Complete the timing diagram for this circuit.

CLK

CLK
Q

4.

Design a circuit that implements the state diagram

3. (a) Draw the neat diagram of locked JK flip-flop using NAND gates and give its truth table.
(b) Give the excitation table for T flip-flop,SR flip-flop,JK 0/0
flip-flop.
S0
1/1
4. (a) Design 32:1 multiplexer using 16:1 multiplexers.

S1

0/1

(b) Implement the following combinational circuit using 4 to 16 line decoder.

Y1 = m(2,3,9). 0/1
1/0
Y2 = m(10,12,13).
Y3 = m(2,4,8).
Y4 = m(1,2,4,7,10,12).S2
1/1

5. (a) List the PLA program table for combinational circuit that squares a 3-bit number.
(b) What is ROM ?Describes using the block diagram, what size ROM would it take to implement binary multiplier
that multiplies
two binary
numbers.
5. Design
a circuit
that implements the state diagram

0/0

S1

1/0

0/1

S0

1/1
S2

0/1

0/1
1/0
1/1

1/0

S4

S3
0/0

II B.TECH II MID TERM EXAMINATIONS : DESCRIPTIVE EXAM

TIME :90 MIN SUBJECT ::STLD

AY:2014-2015

SET-2

BRANCH :EEE MAX.MARKS::30

ANSWER ANT THREE OF THE FOLLOWING QUESTIONS.

1. (a) Design and implement MOD-6 synchronous counter using JK flip-flop.

(b) Draw the logic diagram of 4-bit shift register.Explain how Shift-left and Shift-Right operations are performed.
SYNCHRONOUS (CLOCKED) SEQUENTIAL CIRCUITS

2. Complete the timing diagram for the circuit given below.

3.

257

Complete the timing diagram for this circuit.

CLK

CLK
Q

4.

Design a circuit that implements the state diagram

3. (a) Draw the neat diagram of locked JK flip-flop using NAND gates and give its truth table.
(b) Give the excitation table for T flip-flop,SR flip-flop,JK 0/0
flip-flop.
S0
1/1
4. (a) Design 32:1 multiplexer using 16:1 multiplexers.

S1

0/1

(b) Implement the following combinational circuit using 4 to 16 line decoder.

Y1 = m(2,3,9). 0/1
1/0
Y2 = m(10,12,13).
Y3 = m(2,4,8).
Y4 = m(1,2,4,7,10,12).S2
1/1

5. (a) List the PLA program table for combinational circuit that squares a 3-bit number.
(b) What is ROM ?Describes using the block diagram, what size ROM would it take to implement binary multiplier
that multiplies
two binary
numbers.
5. Design
a circuit
that implements the state diagram

0/0

S1

1/0

0/1

S0

1/1
S2

0/1

0/1
1/0
1/1

1/0

S4

S3
0/0