Electrical Power and Energy Systems 58 (2014) 319328

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Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

Enhanced PLL based SRF control method for UPQC with fault protection
under unbalanced load conditions
A. Jeraldine Viji a,, T. Aruldoss Albert Victoire b,1
a
b

Mailam Engg College, Research Scholar, Jntuk, India

Anna University Regional Centre, Coimbatore, India

a r t i c l e

i n f o

Article history:
Received 27 September 2012
Received in revised form 30 November 2013
Accepted 2 January 2014

Keywords:
UPQC
EPLL
Modulated hysteresis current controller
Power quality

a b s t r a c t
This paper presents novel control strategy of a three-phase four-wire unied power quality conditioner
(UPQC). It is used to improve power quality in distribution system. The UPQC is realized by the integration of series and parallel active power lter (SAPF and PAPF) sharing a common dc bus capacitor. The
realization of parallel APF and series APF are carried out using a three-phase, three legs voltage source
inverter (VSI) with split capacitor. In both APFs the fundamental source voltages and currents are
extracted by synchronous reference frame technique. SAPF connected with the supply by series transformer. The secondary of series transformer is affected by load side short circuits. This paper also explains
the control circuit for protection of series transformer against over voltage and over current. PAPF connected with the system by series inductance. The performance of the applied control algorithm of shunt
active lter with series active lter is evaluated in terms of power-factor correction, load balancing, and
mitigation of voltage and current harmonics in a three-phase four-wire distribution system for non-linear
load, unbalanced supply and load conditions . Sinusoidal PWM current controller, modulated hysteresis
current controller are used for generation of switching pulses to series and parallel APFs. The two control
algorithm is simulated by use of MATLAB/Simulink-based environment and the obtained results validated through experimental study with the UPQC hardware prototype.
2014 Elsevier Ltd. All rights reserved.

1. Introduction
The modern power distribution system is becoming highly vulnerable to the different power quality problems [1,2]. The extensive use of non-linear loads is further contributing to increased
current and voltage harmonics issues. Unied power quality
control was widely studied by many researchers as an eventual
method to improve power quality of electrical distribution system
[1,3].
The function of unied power quality conditioner is to compensate supply voltage icker/imbalance, reactive power, negativesequence current, and harmonics. In other words, the UPQC has
the capability of improving power quality at the point of installation (PCC) on power distribution systems or industrial power
systems. Therefore, the UPQC is expected to be one of the most
powerful solutions to large capacity loads sensitive to supply
Corresponding author. Tel.: +91 9443677164.
E-mail addresses: jeraldrovan@gmail.com, jerald_robin@yahoo.co.in (A. Jeraldine
Viji), t.aruldoss@gmail.com (T. Aruldoss Albert Victoire).
1
Tel.: +91 9944350279.
http://dx.doi.org/10.1016/j.ijepes.2014.01.039
0142-0615/ 2014 Elsevier Ltd. All rights reserved.

voltage icker/imbalance [4]. The UPQC consisting of the combination of a series (APF) and parallel APF shared by common dc voltage. UPQC can also compensate the voltage interruption if it has
some energy storage or battery in the dc link [4]. The parallel
APF is usually connected across the loads to compensate for all
current-related problems such as the reactive power compensation, power factor improvement, current harmonic compensation,
and load unbalance compensation [5] whereas the series APF is
connected in a series with the line through series transformers. It
acts as controlled voltage source and can compensate all voltage
related problems, such as voltage harmonics, voltage sag, voltage
swell, and icker. Several papers studied and compared the performances of lter with different reference current generation technique. Generally the reference signal generation technique is
classied in to two major classications that are frequency domain
method and time domain method. In this frequency domain method, Fourier transform, DFT, FFT, RDFT are used for extracting
harmonic component from polluted voltage and current signals.
There are many types available in time domain method such as
P-q theory, Instantaneous reactive power theory, Synchronous
reference frame theory, P-q-r theory, Instantaneous active and

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A. Jeraldine Viji, T. Aruldoss Albert Victoire / Electrical Power and Energy Systems 58 (2014) 319328

reactive current component theory, Adaptive notch lter, Improved active and reactive current component theory [58]. Compare to Instantaneous active reactive compensation method
enhanced PLL with SRF method the transformation angle is not distorted under unbalanced source condition. Therefore, Enhanced
PLL SRF technique is used for both voltage and current reference
generations. Sinusoidal PWM current controller used in series active lter and hysteresis current controller is used in parallel active
lter for gate pulse generations. When a load side short circuit occurs, the voltage across on the load is nearer to zero, and all the
supply voltage being distributed between the series coupling
transformer and the impedance of the supply system. Compare
to impedance introduced by the series compensator, the supply
system impedance is small, so it introduces higher supply voltage
drops across the primary of the series transformer. The rated voltage of the series transformer primary winding would not be greater than 50% of the supply nominal voltage. Therefore a protection
circuit is the way to protect the series transformer under over voltage and over current. A protection circuit is connected across the
secondary of series transformer which consists of two anti parallel
Traics and zener diode. It protects secondary of series transformer
under short circuit condition at the load side. The proposed control
techniques have been evaluated and tested under non linear and
unbalanced load conditions using MATLAB/Simulink software and
also experiment.

phase difference. The supply voltage is used to nd the voltage

sag, and load voltage is used to feedback the output voltage in
order to minimize steady state error in the fundamental component [2022,26]. The injected voltage generated by the series APF
according to the difference between reference load voltage and
supply voltage and it is applied to PI controller but this voltage
has some harmonics because of unbalanced load connected in
the load side. The harmonics are eliminated by applying component into LPF and q components make into zero. In Eqs. (1) and
(2) supply and load voltages vsa and vla are transformed to rotating
reference frame co-ordinates (d-q-l).

3
2
32
3
p1
p1
p1
V s0
V sa
2
2
2
6
7 p6
7
6
7
4 V sd 5 2=34 sinxt sinxt  2 p3 sinxt 2 p3 54 V sb 5
V sq
V sc
cosxt cosxt  2 p3 cosxt 2 p3
2

2
32 3
p1
p1
p1
V la
2
2
2
p

6 7
6
76 7
p
p
4 V ld 5 2=34 sinxt sinxt  2 3 sinxt 2 3 54 V lb 5
V lq
V lc
cosxt cosxt  2 p3 cosxt 2 p3

2.1. Reference voltage signal generation for series APF

The function of the series APF is to compensate the voltage disturbance in the source side, which is due to the fault in the distribution line at the PCC. The series APF control algorithm calculates
the reference value to be injected by the series transformers, comparing the positive-sequence component of source voltage with
the load side line voltages [1014] If there is any sag or swell present in the source voltage, the detection block generates the reference peak amplitude by root mean square method, the error
vector obtained is used for nding symmetry of sag with their

Fig. 2.1. UPQC block diagram.

xtdt

q
v 2d v 2q

h h0 

jV sd j

The voltage in d axes (vsd) given in (5) consists of average and

2. Derivation of reference signals

The UPQC consists of two voltage source inverters connected
back to back with each other sharing a common dc link. The main
aim of the series APF is harmonic isolation between load and supply; it has the capability of voltage icker/imbalance compensation
as well as voltage regulation and harmonic compensation at the
utility-consumer point of common coupling (PCC) [9]. The parallel
APF is used to absorb current harmonics, compensate for reactive
power and negative-sequence current, and regulate the dc link
voltage between both APFs. The general UPQC block diagram is
shown in Fig. 2.1.

V l0

g The average
oscillating components of source voltages Vsd; Vsd.
voltage vsd is calculated by using second order LPF (low pass lter).

g
v sd Vsd Vsd

g
v sq Vsq Vsq

The oscillating components of vsd, vsq having harmonics and

negative sequence components under unbalanced load condition.
The load side reference voltages v labc are calculated as given in
Eq. (7). The switching signals are assessed by comparing reference
voltages v labc and the load voltages vlabc via PWM controller.

32
2 1
3
p
sinxt
cosxt
V0
2
p

7
6
6  7
7
p
p 76
p1
4 V Lb 5 2=36
4 2 sinxt  2 3 cosxt  2 3 54 V sd 5
0
V Lc
p1
sinxt 2 p3 cosxt 2 p3
2
2

V La

The three-phase load reference voltages are compared with load

line voltages and the errors are then processed by PWM controller
to generate the required switching signals for series APF IGBT
switches.
2.2. Control circuit for protection of series transformer
A protection scheme against the load side short circuits has
been derived and implemented in the UPQC proto type. The major
protection complication for this series inverter is that current
ows in the primary side of the injection transformer as long as
the system load or fault current exists. If the secondary of series
injection transformer is open to compensate over current, it creates unbalanced magneto motive force (MMF), which will over
magnetize the transformer core and generate substantial secondary-side voltages. Even if the VSI is disabled, VSI acts as a diode
rectier and the dc-bus voltage will quickly charge up beyond
the voltage rating of the power stage. This will happen within a
millisecond that is it can occur within one fundamental cycle even
under normal load current conditions. Hence, an effective protection scheme must at all times provide a continuous secondary
current path, and divert this current to appropriately rated

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A. Jeraldine Viji, T. Aruldoss Albert Victoire / Electrical Power and Energy Systems 58 (2014) 319328

elements depending on the level and duration of current to

be passed [10]. In order to protect the series inverter from
overvoltage and over current, it is proposed to accomplish this
short circuiting by using a pair of anti parallel connected thyristors with a pair of zener diode. The proposed protection scheme
is shown in Fig. 2.2.
During load side fault current, the short-circuit current following from the supply side is diverted to the thyristors of the protection scheme. However, since the series VSI remains in operation, a
large current will ow through it, which comes from the DC side. In
order to interrupt the path for this current, the series VSI switches
must be disabled [23,24]. Thus, as soon as the secondary of the series transformer is short-circuited by the protection scheme, the
gate signals of the series VSI have to be disabled in a reasonably
short time and also in order to prevent the short circuit of load
being fed from dc side the parallel APF gate signal must be disabled. An over current indicator is placed in the phase of the series
APF [10], it works when current ow in the series APF greater than
threshold value of indicator, it disable the gating control of two
APFs, and enable the protection schemes. A primary bypass breaker
is placed in the primary side to give protection to primary windings [25]. The reference voltage and current generation is explained in diagram Fig. 2.4.

currents of the load are determined by PLL algorithms. The

angular position of the supply voltage vector shown by xt of
the PLL. In 3P4W nonlinear power systems, the id and iq components of the current decompose into oscillating components and
average components. The oscillating component indicating
harmonic and average component indicates active and reactive
currents. Conventional PLL circuit has low performance for highly
distorted and unbalanced system voltages. The enhanced PLL diagram is shown in Fig. 2.3. In enhanced PLL the measured line
voltages are multiplied by feedback currents with unity amplitude, and one of them leads other by 120. The reference fundamental angular frequency (x0 = 2pf) is added to the output of the
PI controller to stabilize the output. The exact transformation angle (xt) is obtained by output of the integral after the PI controller, but the produced xt lead by 90 with x0; therefore, the p/2
is added to the output of the integrator in order to reach system
fundamental frequency. This EPLL circuit arrives at a stable operating point when three phase instantaneous active power (p3ax)
becomes zero.
The proposed EPLL and SRF-based shunt APF reference sourcecurrent signal-generation algorithm uses only source voltages,
source currents, and dc-link voltages. The enhanced PLL circuit is
designed to operate properly under distorted and unbalanced voltage waveforms.

2.3. Reference current signal generation for parallel APF

2.3.1. Enhanced PLL
Control schemes for parallel APF usually use the instantaneous
reactive power theory (pq theory) for reference signals determination. Although this theory presents a very powerful tool, but
it requires more number of analog multiplier and dividers etc.
For hardware setup, minimization of component is required.
The synchronous reference frame (SRF) is best solution for making hardware [16]. In SRF three phase quantities are converted
into two phase quantity of dq domain .Advantages of dq control
is easy ltration, since the 50 Hz components are transferred into
dc quantities and all harmonic components are ac quantities. But
conventional SRF method transformation angle is oscillated under
distorted supply voltage condition. For this problem enhanced PLL
technique is used. In this compensation strategy, the distorted
currents are rst transferred into two quantity synchronous rotating frames using cosine and sinus functions from the phaselocked loop (PLL). This PLL helps to maintain the synchronization
with supply voltage and current. Similar to the p-q theory, using
lters, the harmonics and fundamental components are separated
easily and transferred back to the a-b-c frame as reference signals
for the lter. In nonlinear load conditions, harmonics and reactive

Fig. 2.2. Protection circuit for series transformer.

2.3.2. Reference current generation

The parallel APF described in this paper is used to compensate
the current harmonics, reactive power generated by the nonlinear
load. The source currents are transformed to d-q-0 coordinates, as
given in (6) and using xt which coming from the EPLL. In 3P4W
systems under with nonlinear load conditions, the instantaneous
source currents (isd and isq) include both oscillating components
(f
isd and (f
isq ) and average components (isd and isq ). The oscillating
components consist of the harmonic and negative-sequence components of the source currents. The average components consist
of the positive-sequence components of current and reactive current. The proposed SRF-based method employs the positive-sequence average component (isd ) in the d-axis and assigned 0
value to zero- and negative-sequence components, in order to
compensate harmonics and unbalances in the load.

3
2
1
is0
2
6 7
6
4 isd 5 2=34 sinxt
isq

1
2

1
2

sinxt  2 p3

cosxt cosxt

 2 p
3

32

isa

76 7
sinxt 2 p3 54 isb 5

cosxt 2 p3

isc

In order to compensate the active power losses of the UPQC,

during the active power is injected to the power system by the
series APF, which causes dc-link voltage reduction, in parallel
APF, the active power is absorbed from the power system for

Fig. 2.3. Enhanced PLL.

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A. Jeraldine Viji, T. Aruldoss Albert Victoire / Electrical Power and Energy Systems 58 (2014) 319328

Fig. 2.4. Reference voltage, current generation.

regulating dc-link voltage. Due to absorption and injection of active power, the dc link voltage is not maintained constant for this
purpose, the dc-link voltage is compared with its reference voltage
(vdc), and the required active current (idloss) is obtained by a PID
controller. The PID controller is used to control the dc side capacitor voltage of the PWM-inverter. The PID controller is a linear
combination of the P, I and D controller. Its transfer function can
be represented as:

ki
HS kp kd S
s

where kp is the proportional constant that determines the dynamic response of the DC-bus voltage control, kI is the integration
constant that determines it is settling time and kd represents the
derivative of the error. The controller is tuned with proper gain
parameters of [kp = 0.7, kI = 23, kd = 0.01]. These values are obtained by tuning rules based on improved ZieglerNichols method. The PID controller estimates the required active current [15].
The source current fundamental reference component is calculated by adding to the required active current and source current
average component (isd ), which is obtained by an LPF, as given in
Eq. (8).

isdr ef idloss lsd

10

The source current references are calculated as given in (9) to

compensate the harmonics, neutral current, unbalance, and reactive power by regulating the dc-link voltage.

isa
6
4 isb
isc

ref
ref
ref

2 3
0
7
7
1 6

T
l
5
4 sd 5
0

11

In hysteresis current control method reference source currents

(isa_ref, isb_ref, and isc_ref) and measured source currents (isa, isb, and
isc) are compared for generating IGBT switching signals to compensate all current-related problems. The reference voltage and current generation diagram is shown in Fig. 2.4.
3. Current control scheme of UPQC
The control scheme of UPQC includes reference voltage and current extraction control strategy for both lters and generation of
gate pulse for PWM VSI. The generation of reference current,
voltage technique is explained in previous sections. The gate
pulse generations of both lters are explained in the following
sections.

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323

voltage acquired from the load and then the error signal is passed
to the sinusoidal PWM controller, the PWM controller produces
pulses to the IGBT gates. A closed loop feedback can ensure the
dynamical changes in voltage variation [8,9]. Fig. 3.1 shows the
control block diagram of series APF.
3.2. Parallel active lter

Fig. 3.1. Current control technique for series APF.

Fig. 3.2. Modulated hysteresis current control technique for parallel APF.

3.1. Series active lter

The Higher order harmonic content in the supply line side is reduced by carrier based sinusoidal PWM technique. In this modulation technique a sinusoidal signal is compared with carrier
(triangular) waveform. The width of each pulse is calculated by
the amplitude of sine wave at that moment. The peak value of output voltage can be controlled by varying the pulse width. This
PWM controller imposes constant switching frequency of the IGBT
switches. It forces the input PWM voltages of inverter to track their
reference values. The reference voltage is compared with the actual

Linear current controller with pulse width modulation technique having constant switching frequency but its dynamic property is limited. Compared with other controllers, non-linear
based on hysteresis strategies allows faster dynamic response
and better robustness with respect to the variation of the non-linear load [810]. Nevertheless, with non-linear current controllers,
the switching frequency is not constant and this technique generates a large side harmonics band around the switching frequency.
In literature, number of solution is available to x switching frequency; one among them is using a variable hysteresis bandwidth.
But this variable band hysteresis controller needs the knowledge of
system model and its parameter; this implies difculty in making
hardware implementation. Here, we implemented a non linear
current controller, i.e. modulated hysteresis current controller
[16,17]. In this method the carrier frequency is chosen which is
equal to the desired switching frequency for the voltage source inverter. The resulting signal (H) constitutes then the new reference
of a classical hysteresis controller with a bandwidth of 2Bh. The
outputs of the hysteresis block are the switching pattern to the
voltage source inverter. Fig. 3.2 shows the block diagram of hysteresis current controller. To control the active lter at xed switching
frequency, the triangular carrier signal of amplitude Atr is combined with hysteresis bandwidth Bh [18,19].
4. Simulation and experimental results and analysis
The proposed UPQC system with series transformer protection
circuit compensates the current harmonics produced by a diode

Fig. 4.1. Phase (A) hare ware model of UPQC.

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A. Jeraldine Viji, T. Aruldoss Albert Victoire / Electrical Power and Energy Systems 58 (2014) 319328

bridge rectier, and eliminates the voltage harmonics, and also

protect the series transformer under load side short circuit condition. The experimental prototype in the 3P4W UPQC system consists of two voltage controlled inverters (shunt and series APFs)
sharing the same dc bus in split-capacitor topology. The series
APF is connected in series with the supply via a ripple RC lter,
RT and CT, and a matching Series transformer. The dc links of both
shunt and series APFs are connected to two common series 2200lF dc capacitors under 700-V dc in split capacitor topology. A
three-phase and a single-phase diode bridge rectier are used as
nonlinear loads and the effect of change in load current is recorded
for each phase. The control algorithm for the UPQC is evaluated by
MATLAB/Simulink software. The system is investigated under
unbalanced load conditions. The control unit of hardware setup
consists of an ATMEL 89S52 microcontroller along with the driver
circuit. The driver circuit performs the PWM method to perform
switching operation and the pulses are fed to the microcontroller.
The microcontroller receives both the switching pulses, the signal
from the VI detector and the PLL signal. It coordinates and provides
the switching pulses appropriately to the active power lters. The
ATMEL 89S52 microprocessor is fed with the program with the
help of the KEIL software. The circuit diagram of the UPQC hardware kit is shown Fig. 4.1. The system parameters used are; line
to line source voltage Vrms is 380 V; system frequency (f) is
50 Hz; source inductance is LS is 1 mH; series side Filter impedance
of Rc1, Lc1, Cc1 is 100 X, 1 lH, 60 lF; shunt side Filter impedance of
Rc2, Lc2, Cc2 is 5 X, 3.5 mH, 10 lF; three phase diode rectier RL, LL

Fig. 4.1d. Load current (UPQC OFF).

Fig. 4.1e. Source side neutral current (UPQC OFF).

Fig. 4.1f. Load side neutral current (UPQC OFF).

Fig. 4.1a. Source voltage (UPQC OFF).

Fig. 4.2a. Source voltage (UPQC ON).

Fig. 4.1b. Source current (UPQC OFF).

Fig. 4.2b. Source current (UPQC ON).

Fig. 4.1c. Load voltage (UPQC OFF).

Fig. 4.2c. Load voltage (UPQC ON).

A. Jeraldine Viji, T. Aruldoss Albert Victoire / Electrical Power and Energy Systems 58 (2014) 319328

325

Fig. 4.2d. Load current (UPQC ON).

Fig. 4.3b. Inductive load.

Fig. 4.2e. Compensating current (UPQC ON).

Fig. 4.3c. Experiment result of source current (phase A) without UPQC.

Fig. 4.2f. Source side neutral current (UPQC ON).

Fig. 4.2g. Load side neutral current (UPQC ON).

Fig. 4.3d. Experiment result of source side voltage (phase A) without UPQC.

Fig. 4.2h. Voltage across capacitance (UPQC ON).

Fig. 4.3e. Experiment result of source voltage with UPQC.

load: 10 X; 30 mH respectively; unbalanced three phase load resistances are R1 = 20 X, R2 = 70 X, R3 = 100 X and load inductance LL
is 50 mH; DC side capacitance is 2200 lF; reference voltage (VDC,ref)
is 700 V, switching frequency of series and shunt inverter is
approximately12 KHz. Fig. 4.1 shows the block diagram of hard
setup in phase A.

4.1. UPQC OFF condition

Fig. 4.3a. 1.5 KVA proto type UPQC kit.

Figs. 4.1af show the source voltage, source current, load voltage, load current, source side neutral current, load side neutral current of three phase with bridge rectier and unbalanced load
condition. The THD of the source voltage and current is 26.6%
and 29.7%.

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A. Jeraldine Viji, T. Aruldoss Albert Victoire / Electrical Power and Energy Systems 58 (2014) 319328

4.2. UPQC ON condition

Figs. 4.2ah show the source voltage, source current, load voltage, load current, compensating current, source side neutral current, load side neutral current and voltage across capacitance of
three phase with bridge rectier and unbalanced load condition.
The THD of the source voltage (phase A) and current (phase A) is
2.33% and 2.25%. The circuit parameters and experimental
conditions are set up the same as the simulation conditions. The
experimental set up is shown in diagram Figs. 4.3ad shows experiment result of source current (phase A), source voltage (phase A)
without UPQC. Figs. 4.3eh show experiment result of source
voltage, source current, load current, compensating current with
UPQC.
The experimental results show that the control objectives are
satised. Table 1 explains the comparison of source, load voltages
and currents with simulation, experimental results before and
after UPQC conditions.

Fig. 4.3f. Experiment result of source current with UPQC.

5. Conclusion
Fig. 4.3g. Experiment result of load current with UPQC.

Fig. 4.3h. Experiment result of compensating current with UPQC.

Table 1
Simulation, experimental results and thd levels of voltage and current waveforms at
the pcc.
Various parameters (THD)

Input source current (A

phase)
Load side current (A phase)
Input source current (B
phase)
Load side current (B phase)
Input source current (C
phase)
Load side current (C phase)
Input source voltage (A
phase)
Load side voltage (A phase)
Input source voltage (B
phase)
Load side voltage (B phase)
Input source voltage (C
phase)
Load side voltage (C phase)

Simulation results

Experimental results

UPQC
OFF

UPQC
ON

UPQC
OFF

UPQC
ON

28.07

2.25

36.7

4.56

36.2
28.07

13.6
2.45

46.2
33.2

10.5
4.6

38.2
28.07

15.42
2.50

42.2
37.4

13.6
4.9

28.07
28.07

2.50
2.25

42.5
41.07

13.6
2.25

36.2
28.07

12.6
3.0

38.6
40.45

4.02
12.45

38.2
28.07

16.4
3.2

38.42
4250

14.2
3.3

36.07

13.3

49.50

12.50

This paper describes a enhanced PLL based SRF control strategy

used in the UPQC, which mainly compensates the reactive power
along with voltage and current harmonics under unbalanced
load-current conditions. Sine PWM current control technique is
used for series APF voltage reference and modulated hysteresis
current control technique for Parallel APF current reference generation. By the use of EPLL, able to generate reference current under
distorted of load condition. The series APF isolates the loads and
source voltage in unbalanced and distorted load conditions, and
the parallel APF compensates reactive power, neutral current,
and harmonics and provides three-phase balanced and rated currents for the mains. A protection circuit is connected across the series transformer to protect the secondary of series transformer
under load short circuit condition. A bypass breaker is connected
across the primary of series transformer to protect heavy current
ow thro it under load fault condition. The comparison table shows
the simulation, experimental result of proposed UPQC. Experimental results obtained from a laboratory model of 1.5 kVA, along with
a theoretical analysis, are shown to verify the viability and effectiveness of the proposed EPLL with SRF-based UPQC control
method.
Appendix A

S. No

Components required

Switches in the APF

2
3
4
5
6
7
8
9

Congurations

IRF 840 N Channel

MOSFET (8A max, 500 V
max)
Transformer
Primary ? 18A (AWG)
Secondary ? 21A (AWG)
Optocoupler
MCT2E (60 V max,
500 mA max)
For capacitor bank
2200 lF
Microcontroller
ATMEL 89S52
Load inductance
Equal to 5 HP motor
Step down transformer
2305 V for
for DC input components microcontroller units
Ammeter
05 A, 030 A
Triac
32 A

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327

Appendix B

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