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Culture Documents
assign pcinc = pc + 4;
+4
6>
0:1
: <2
Ra
L
SE
WA
ter
gis
Re ile
1
F
RA
AA
WW
1
RD
JT
1
X5P:21> 0
: <2
Rc
>)
Z 15:0
T(<
X
S
C:
0
)
1
(C
XT
EL
4*S
AS
+4+
Z
PC
IRQ
gic
A
Lo
ol
ntr
Co
L
N
SE
UF
PC SEL
AL
2
RA L
E
AS
EL
BS SEL
WD FN
U
AL
Wr
RF
WE EL
S
WA
2
RA
2
RD
WERF
WD
WE
EL
BS
Wr
R/W
WD
ory
em
ta M
Da
RD
r
Ad
B
U
AL
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PC
01
EL
WDS
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n
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o
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eta
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data
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5:2
: <2
Rc
EL
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RA
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1>
5:1 0
: <1
Rb
t [3 1
PC
L4
SE
on
cti
tru
Ins emory
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D
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ILLP JT
r
dO
XA
c
l
k
,re
se
t
,
irq
,
If (done) $finish;
Figures by MIT OCW.
02/04/05
L02 Verilog 1
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L02 Verilog 2
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L02 Verilog 3
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L02 Verilog 4
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L02 Verilog 5
Advantages of HDLs
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L02 Verilog 6
Advantages of HDLs
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L02 Verilog 7
Advantages of HDLs
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L02 Verilog 8
Advantages of HDLs
Processor
B
Processor
C
Network
Memory
Bank
A
Memory
Bank
B
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L02 Verilog 9
Advantages of HDLs
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L02 Verilog 10
VHDL
Verilog
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L02 Verilog 11
Advantages
Choice of many US design teams
Most of us are familiar with C-like syntax
Simple module/port syntax is familiar way to organize
hierarchical building blocks and manage complexity
With care it is well-suited for both verification
and synthesis
Disadvantages
Some comma gotchas which catch beginners everytime
C syntax can cause beginners to assume C semantics
Easy to create very ugly code, good and consistent
coding style is essential
02/04/05
L02 Verilog 12
An HDL is NOT a
02/04/05
L02 Verilog 13
adder
cout
sum
endmodule
Don't forget the semicolon!
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L02 Verilog 14
adder
cout
sum
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L02 Verilog 15
b
cin
cout
FA
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L02 Verilog 16
adder
cout
FA
FA
FA
FA
FA
FA
FA
FA
fa0(
fa1(
fa2(
fa3(
...
...
...
...
);
);
);
);
endmodule
02/04/05
L02 Verilog 17
adder
cout
FA
FA
FA
c0, S[0] );
c1, S[1] );
c2, S[2] );
cout, S[3] );
FA
endmodule
0,
c0,
c1,
c2,
02/04/05
Carry Chain
L02 Verilog 18
adder
cout
FA
FA
FA
02/04/05
L02 Verilog 19
Verilog Basics
Data Values
Numeric Literals
4b10_11
0 1
X Z
Underscores
are ignored
Base format
(d,b,o,h)
Decimal number
representing size in bits
32h8XXX_XXA3
02/04/05
L02 Verilog 20
Behavioral
Dataflow
Module is implemented by
specifying how data flows
between registers
Gate-Level
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L02 Verilog 21
Behavioral
Dataflow
The process of
automatically generating a
gate-level model from
either a dataflow or a
behavioral model is called
Gate-Level
Logic Synthesis
02/04/05
L02 Verilog 22
n3;
sel[1]
sel_b[1]
sel[1]
sel_b[1]
);
);
);
);
sel[1]
out
d
b
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L02 Verilog 23
endmodule
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L02 Verilog 24
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L02 Verilog 25
sel
sel
sel
sel
==
==
==
==
0
1
2
3
)
)
)
)
?
?
?
?
a
b
c
d
:
:
:
: 1bx;
endmodule
// Simple four bit adder
module adder( input [3:0] op1, op2,
output [3:0] sum );
assign sum = op1 + op2;
endmodule
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L02 Verilog 26
+ - * / % **
! && ||
> < >= <=
== != === !===
~ & | ^ ^~
& ~& | ~| ^ ^~
{ }
?:
02/04/05
Avoid these
operators since
they usually
synthesize poorly
L02 Verilog 27
Reduction:
Shift:
Concatenation:
Conditional:
+ - * / % **
! && ||
?:
02/04/05
assign signal[3:0]
= { a, b, 2b00 }
L02 Verilog 28
begin
if ( sel == 0 )
evaluated sequentially
else if ( sel == 2 )
out = c
The code in an always block can
else if ( sel == 3 )
end
code) here we implement a mux
endmodule
02/04/05
L02 Verilog 29
else if ( sel == 3 )
block is executed
out = d
end
endmodule
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L02 Verilog 30
c, d, sel )
)
== 1 )
== 2 )
== 3 )
endmodule
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L02 Verilog 31
begin
if ( sel == 0
out = a;
else if ( sel
out = b
else if ( sel
out = c
else if ( sel
out = d
end
endmodule
)
== 1 )
== 2 )
== 3 )
L02 Verilog 32
)
== 1 )
== 2 )
== 3 )
endmodule
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L02 Verilog 33
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end
endmodule
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L02 Verilog 34
end
endmodule
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L02 Verilog 35
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L02 Verilog 36
reg out;
always @( * )
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end
endmodule
02/04/05
L02 Verilog 37
reg out;
always @( * )
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end
endmodule
02/04/05
L02 Verilog 38
reg out;
always @( * )
begin
case ( sel )
default : out = 1bx;
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end
endmodule
02/04/05
L02 Verilog 39
clk
next_x
clk
clk
clk
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clk
L02 Verilog 40
clk
clk
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L02 Verilog 41
Behaviora
l
Dataflow
Gat
e-L
eve
l
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L02 Verilog 42
Behavioral
Dataflow
Gate-Level
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L02 Verilog 43
Behavioral
Dataflow
Gate-Level
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L02 Verilog 44
02/04/05
L02 Verilog 45
carry[i], carry[i+1] );
end
endgenerate
endmodule
02/04/05
L02 Verilog 46
Static Elaboration
Model
Static Elaboration
Elaborated Model
Synthesis
Gate-Level
02/04/05
L02 Verilog 47
Larger Examples
GCD
6.884 Spring 2005
Beta
02/04/05
L02 Verilog 48
integer
done;
begin
done = 0;
A = A_in; B = B_in;
while ( !done )
begin
if ( A < B )
begin
swap = A;
A = B;
B = swap;
end
else if ( B != 0 )
A = A - B;
else
done = 1;
end
Y = A;
end
endmodule
02/04/05
L02 Verilog 49
GCD Behavioral
Test Harness
module gcd_test;
parameter width = 16;
reg [width-1:0] A_in, B_in;
wire [width-1:0] Y;
gcd_behavioral #( .width(width) )
initial
begin
B_in = 15;
endmodule
02/04/05
L02 Verilog 50
go
done
Control Unit
zero?
lt
out
A_in
sub
B_in
Design
Design Strategy
Strategy
Partition
Partition into
into control
control and
and datapath
datapath
Keep
Keep all
all functional
functional code
code in
in the
the leaf
leaf modules
modules
6.884 Spring 2005
02/04/05
L02 Verilog 51
assign Y = A;
// Datapath logic
wire [width-1:0] out
= ( out_mux_sel ) ? B : A - B;
if ( A_en )
A <= A_next;
if ( B_en )
B <= B_next;
end
Edge-triggered
flip-flops with
enables
A mix of dataflow
and behavioral
endmodule
02/04/05
L02 Verilog 52
// The running bit is one after go goes high and until done goes high
reg running = 0;
begin
if ( go )
running <= 1;
end
always
begin
if (
else
else
else
end
@(*)
!running )
if ( A_lt_B )
if ( !B_zero )
ctrl_sig
ctrl_sig
ctrl_sig
ctrl_sig
=
=
=
=
6'b11_00x_0;
6'b11_111_0;
6'b10_1x0_0;
6'b00_xxx_1;
//
//
//
//
endmodule
02/04/05
L02 Verilog 53
GCD Testing
Behavioral
Model
RTL
Model
Identical
Outputs?
02/04/05
L02 Verilog 54
Beta Redux
ILL
XAdr OP JT
PCSEL
PC
00
+4
Instruction
Memory
Ra: <20:16>
RA2SEL
WASEL
XP
Rc: <25:21>
RA1
WA
WA
RD1
PC+4+4*SXT(C)
IRQ
Rc: <25:21>
Rb: <15:11>
Register
File
RA2
WD
RD2
WE
WERF
JT
C: SXT(<15:0>)
Z
ASEL
BSEL
Control Logic
PCSEL
RA2SEL
ASEL
ALU
ALUFN
WD
BSEL
WDSEL
ALUFN
Wr
WERF
WASEL
Wr
Data Memory
Adr
RD
PC+4
0 1 2
R/W
02/04/05
WDSEL
L02 Verilog 55
Think about physical partition since wires that cross boundaries can take
lots of area and blocks have to fit into the floorplan without wasteful
gaps.
02/04/05
L02 Verilog 56
details so we could
02/04/05
L02 Verilog 57
PCSEL
JT
2
1
PC
00
Instruction
Memory
D
+4
Ra: <20:16>
RA2SEL
WASEL
XP
PC
Rc: <25:21>
RA1
WA
WA
RD1
PC+4+4*SXT(C)
IRQ
Rc: <25:21>
Rb: <15:11>
Register
File
RA2
WD
RD2
WE
1
WERF
JT
C: SXT(<15:0>)
Z
ASEL
BSEL
Control Logic
PCSEL
RA2SEL
ASEL
ALU
ALUFN
WD
BSEL
WDSEL
ALUFN
Wr
WERF
Wr
Data Memory
Adr
WASEL
Main Datapath
R/W
PC+4
0 1 2
2
02/04/05
RD
WDSEL
L02 Verilog 58
02/04/05
L02 Verilog 59
Laboratory 1
% cp r /mit/6.884/examples/gcd .
% cat gcd/README
02/04/05
L02 Verilog 60