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Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
Single power supply operation
5.0 volt-only operation for read, erase, and
program operations
Minimizes system level requirements
Manufactured on 0.35 m process technology
Compatible with 0.5 m Am29F400 device
High performance
Access times as fast as 55 ns
Low power consumption (typical values at 5
MHz)
48-pin TSOP
44-pin SO
PRELIMINARY
GENERAL DESCRIPTION
The Am29F400B is a 4 Mbit, 5.0 volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in 44-pin SO and 48-pin TSOP
packages. The word-wide data (x16) appears on
DQ15DQ0; the byte-wide (x8) data appears on DQ7
DQ0. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply.
A 12.0 V VPP is not required for write or erase operations. The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMDs 0.35 m
process technology, and offers all the features and benefits of the Am29F400, which was manufactured using
0.5 m process technology.
The standard device offers access times of 55, 60, 70,
90, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithman internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
Am29F400B
PRELIMINARY
Am29F400B
VCC = 5.0 V 5%
-55
-60
-70
-90
-120
-150
55
60
70
90
120
150
55
60
70
90
120
150
30
30
30
35
50
55
BLOCK DIAGRAM
DQ0DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0A17
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
21505C-1
Am29F400B
PRELIMINARY
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin TSOPReverse Pinout
21505C-2
Am29F400B
PRELIMINARY
CONNECTION DIAGRAMS
SO
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
21505C-3
PIN CONFIGURATION
A0A17
LOGIC SYMBOL
= 18 addresses
18
A0A17
DQ15/A-1
BYTE#
CE#
= Chip enable
OE#
= Output enable
WE#
= Write enable
RESET#
RESET#
BYTE#
RY/BY#
= Ready/Busy# output
VCC
VSS
= Device ground
NC
16 or 8
DQ0DQ15
(A-1)
CE#
OE#
WE#
RY/BY#
21505C-4
Am29F400B
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F400B
-55
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
E
= 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F
= 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S
= 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations
Am29F400BT-55,
Am29F400BB-55
Am29F400BT-60,
Am29F400BB-60
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29F400BT-70,
Am29F400BB-70
Am29F400BT-90,
Am29F400BB-90
Am29F400BT-120,
Am29F400BB-120
Am29F400BT-150,
Am29F400BB-150
Am29F400B
PRELIMINARY
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Operation
CE#
OE#
WE#
RESET#
A0A17
DQ0DQ7
BYTE#
= VIH
AIN
DOUT
DOUT
High-Z
AIN
DIN
DIN
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Read
Write
BYTE#
= VIL
VCC
0.5 V
VCC
0.5 V
Output Disable
High-Z
High-Z
High-Z
Hardware Reset
High-Z
High-Z
High-Z
VID
AIN
DIN
DIN
High-Z
CMOS Standby
TTL Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Dont Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic 1, the device is in
word configuration, DQ15DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte
configuration, and only data I/O pins DQ0DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Am29F400B
PRELIMINARY
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC 0.5 V.
(Note that this is a more restricted voltage range than
VIH.) The device enters the TTL standby mode when
CE# and RESET# pins are both held at VIH. The device
requires standard access time (tCE) for read access
when the device is in either of these standby modes,
before it is ready to read data.
The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the CMOS and TTL/NMOS-compatible DC Characteristics tables, ICC3 represents the standby current
specification.
Am29F400B
PRELIMINARY
Table 2.
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
64/32
00000h0FFFFh
00000h07FFFh
SA1
64/32
10000h1FFFFh
08000h0FFFFh
SA2
64/32
20000h2FFFFh
10000h17FFFh
SA3
64/32
30000h3FFFFh
18000h1FFFFh
SA4
64/32
40000h4FFFFh
20000h27FFFh
SA5
64/32
50000h5FFFFh
28000h2FFFFh
SA6
64/32
60000h6FFFFh
30000h37FFFh
SA7
32/16
70000h77FFFh
38000h3BFFFh
SA8
8/4
78000h79FFFh
3C000h3CFFFh
(x8)
Address Range
(x16)
Address Range
SA9
8/4
7A000h7BFFFh
3D000h3DFFFh
SA10
16/8
7C000h7FFFFh
3E000h3FFFFh
Table 3.
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
16/8
00000h03FFFh
00000h01FFFh
SA1
8/4
04000h05FFFh
02000h02FFFh
SA2
8/4
06000h07FFFh
03000h03FFFh
SA3
32/16
08000h0FFFFh
04000h07FFFh
SA4
64/32
10000h1FFFFh
08000h0FFFFh
SA5
64/32
20000h2FFFFh
10000h17FFFh
SA6
64/32
30000h3FFFFh
18000h1FFFFh
SA7
64/32
40000h4FFFFh
20000h27FFFh
SA8
64/32
50000h5FFFFh
28000h2FFFFh
(x8)
Address Range
(x16)
Address Range
SA9
64/32
60000h6FFFFh
30000h37FFFh
SA10
64/32
70000h7FFFFh
38000h3FFFFh
Note:
Address range is A17:A-1 in byte mode and A17:A0 in word mode. See Word/Byte Configuration section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection,
Am29F400B
PRELIMINARY
Table 4.
Description
Mode
CE#
OE#
Device ID:
Am29F400B
(Top Boot Block)
Word
Byte
Device ID:
Am29F400B
(Bottom Boot Block)
Word
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
01h
22h
23h
23h
22h
ABh
ABh
01h
(protected)
00h
(unprotected)
VID
VID
VID
A6
A5
to
A2
X
Byte
A9
A8
to
A7
SA
VID
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Dont care.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
10
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1.
Am29F400B
PRELIMINARY
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than V LKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
AC Characteristics section.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are dont care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Am29F400B
11
PRELIMINARY
number of times, without initiating another command
sequence.
START
A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector
addresses.
Write Program
Command Sequence
Embedded
Program
algorithm
in progress
Data Poll
from System
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
21505C-6
Note:
See Table 5 for program command sequence.
Figure 2.
Program Operation
12
Am29F400B
PRELIMINARY
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See
Write Operation Status for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in AC
Characteristics for parameters, and to Figure 14 for
timing diagrams.
Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the AC Characteristics section for parameters, and to
Figure 14 for timing diagrams.
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 s time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Addresses are dont-cares when writing the Erase Suspend command.
Am29F400B
13
PRELIMINARY
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See Autoselect Command Sequence
for more information.
The system must write the Erase Resume command
(address bits are dont care) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device has resumed erasing.
START
Write Erase
Command Sequence
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
21505C-7
Notes:
1. See Table 5 for erase command sequence.
2. See DQ3: Sector Erase Timer for more information.
Figure 3.
14
Erase Operation
Am29F400B
PRELIMINARY
Table 5.
Cycles
Data
Read (Note 6)
RA
RD
Reset (Note 7)
XXX
F0
Command
Sequence
(Note 1)
Autoselect (Note 8)
Manufacturer ID
Word
Byte
Device ID,
Top Boot Block
Word
Device ID,
Bottom Boot Block
Word
Byte
Byte
4
4
4
Word
Sector Protect Verify
(Note 9)
Program
Chip Erase
Sector Erase
First
555
AAA
555
AAA
555
AAA
Second
AA
AA
AA
555
4
Addr
2AA
555
2AA
555
2AA
555
Third
Data
Addr
555
55
AAA
555
55
AAA
555
55
AAA
2AA
AA
55
555
AAA
Word
555
2AA
555
Word
Byte
Word
Byte
6
6
AAA
555
AAA
555
AAA
AA
AA
AA
XXX
B0
XXX
30
555
2AA
555
2AA
555
90
90
90
55
AAA
555
55
AAA
555
55
AAA
A0
80
80
Data
X00
01
X01
2223
X02
23
X01
22AB
X02
AB
(SA)
X02
XX00
(SA)
X04
00
PA
PD
90
AAA
4
Data Addr
555
Byte
Byte
Fourth
555
AAA
555
AAA
Fifth
Sixth
Addr Data
Addr
Data
XX01
01
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
X = Dont care
Notes:
1. See Table 1 for description of bus operations.
11. The Erase Resume command is valid only during the Erase
Suspend mode.
Am29F400B
15
PRELIMINARY
START
Read DQ7DQ0
Addr = VA
DQ7 = Data?
No
No
Read DQ7DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because
DQ7 may change simultaneously with DQ5.
16
DQ5 = 1?
Yes
Yes
Am29F400B
21505C-8
Figure 4.
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/BY#. Figures 10, Figure 13 and Figure 14 shows RY/BY# for reset, program, and erase operations, respectively.
Table 6 shows the outputs for Toggle Bit I on DQ6. Figure 5 shows the toggle bit algorithm. Figure 16 in the
AC Characteristics section shows the toggle bit timing
diagrams. Figure 17 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
Am29F400B
17
PRELIMINARY
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
START
Read DQ7DQ0
(Note 1)
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to 1. See text.
21505C-9
Figure 5.
18
Am29F400B
PRELIMINARY
Table 6.
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
N/A
No toggle
Toggle
Toggle
No toggle
N/A
Toggle
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
N/A
N/A
Operation
Standard
Mode
Erase
Suspend
Mode
Notes:
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See DQ5: Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Am29F400B
19
PRELIMINARY
20 ns
20 ns
+0.8 V
0.5 V
2.0 V
20 ns
21505C-10
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to 2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is 0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to 2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Figure 6.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of
the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . 40C to +85C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . 55C to +125C
VCC Supply Voltages
VCC for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
20
Am29F400B
20 ns
20 ns
21505C-11
Figure 7.
PRELIMINARY
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Conditions
ILI
ILIT
ILO
ICC1
Min
Typ
Max
Unit
1.0
50
1.0
19
40
mA
19
50
mA
ICC2
36
60
mA
ICC3
0.4
mA
VIL
0.5
0.8
VIH
2.0
VCC
+0.5
VID
VCC = 5.0 V
11.5
12.5
VOL
0.45
VOH
VLKO
2.4
3.2
V
4.2
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Not 100% tested.
Am29F400B
21
PRELIMINARY
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
ILI
ILIT
ILO
ICC1
Typ
Max
Unit
1.0
50
1.0
20
40
28
50
mA
ICC2
30
50
mA
ICC3
0.3
VIL
0.5
0.8
VIH
0.7 x
VCC
VCC+
0.3
VID
VCC = 5.0 V
11.5
12.5
VOL
0.45
VOH1
0.85
VCC
VCC
0.4
3.2
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Not 100% tested.
4. ICC3 = 20 A max at extended temperature (>+85 C).
22
Min
Am29F400B
4.2
PRELIMINARY
TEST CONDITIONS
Table 7.
Test Specifications
5.0 V
Test Condition
2.7 k
Device
Under
Test
CL
All
others
-55
Output Load
Unit
1 TTL gate
30
100
pF
20
ns
0.03.0
0.452.4
1.5
0.8, 2.0
1.5
0.8, 2.0
6.2 k
Input Pulse Levels
Note:
Diodes are IN3064 or equivalent.
21505C-12
Figure 8.
Test Setup
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
KS000010-PAL
Am29F400B
23
PRELIMINARY
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std
Description
tAVAV
tRC
tAVQV
tACC
tELQV
tCE
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Test Setup
-55
-60
-70
-90
-120
-150
Unit
Min
55
60
70
90
120
150
ns
CE# = VIL
OE# = VIL
Max
55
60
70
90
120
150
ns
OE# = VIL
Max
55
60
70
90
120
150
ns
Max
30
30
30
35
50
55
ns
tDF
Max
15
20
20
20
30
35
ns
tDF
Max
15
20
20
20
30
35
ns
tOEH
tOH
Min
ns
Min
10
ns
Min
ns
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
21505C-13
Figure 9.
24
Am29F400B
PRELIMINARY
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
Unit
tREADY
Max
20
tREADY
Max
500
ns
tRP
Min
500
ns
tRH
Min
50
ns
tRB
Min
ns
Note:
Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
21505C-14
Figure 10.
RESET# Timings
Am29F400B
25
PRELIMINARY
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std.
Description
-55
-60
-70
-90
-120
-150
Unit
tELFL/tELFH
Max
tFLQZ
Max
15
20
20
20
30
35
ns
tFHQV
Min
55
60
70
90
120
150
ns
ns
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0DQ7)
Data Output
(DQ0DQ14)
DQ0DQ14
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0DQ7)
DQ0DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0DQ14)
DQ15
Output
tFHQV
21505C-15
Figure 11.
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
21505C-16
Figure 12.
26
PRELIMINARY
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Std.
Description
-55
-60
-70
-90
-120
-150
Unit
tAVAV
tWC
Min
55
60
70
90
120
150
ns
tAVWL
tAS
Min
tWLAX
tAH
Min
45
45
45
45
50
50
ns
tDVWH
tDS
Min
25
30
30
45
50
50
ns
tWHDX
tDH
Min
ns
tOES
Min
ns
Min
ns
ns
tGHWL
tGHWL
tELWL
tCS
Min
ns
tWHEH
tCH
Min
ns
tWLWH
tWP
Min
tWHWL
tWPH
Min
20
Typ
tWHWH1
Programming Operation
(Note 2)
Byte
tWHWH1
Word
Typ
12
tWHWH2
Typ
sec
30
35
35
45
50
50
ns
ns
s
tVCS
Min
50
tRB
Min
ns
Min
tBUSY
30
30
30
35
50
55
ns
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
Am29F400B
27
PRELIMINARY
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
tCH
tGHWL
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
21505C-17
Figure 13.
28
Am29F400B
PRELIMINARY
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
SA
VA
tAH
CE#
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
2. Illustration shows device in word mode.
21505C-18
Figure 14.
Am29F400B
29
PRELIMINARY
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
21505C-19
Figure 15.
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21505C-20
Figure 16.
30
Am29F400B
PRELIMINARY
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
Note:
The system may use either CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
21505C-21
Figure 17.
Std.
Description
tVIDR
tRSP
Unit
Min
500
ns
Min
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
21505C-22
Figure 18.
Am29F400B
31
PRELIMINARY
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std.
Description
-55
-60
-70
-90
-120
-150
Unit
tAVAV
tWC
Min
55
60
70
90
120
150
ns
tAVEL
tAS
Min
tELAX
tAH
Min
45
45
45
45
50
50
ns
tDVEH
tDS
Min
25
30
30
45
50
50
ns
tEHDX
tDH
Min
ns
tOES
Min
ns
tGHEL
tGHEL
Min
ns
tWLEL
tWS
Min
ns
tEHWH
tWH
Min
ns
tELEH
tCP
Min
tEHEL
tCPH
Min
20
Typ
tWHWH1
Programming Operation
(Note 2)
Byte
tWHWH1
Word
Typ
12
tWHWH2
tWHWH2
Typ
30
35
45
50
50
ns
ns
s
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
32
35
ns
Am29F400B
sec
PRELIMINARY
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
21505C-23
Figure 19.
Am29F400B
33
PRELIMINARY
Typ (Note 1)
Max (Note 2)
Unit
1.0
11
300
12
500
Byte Mode
3.6
10.8
(Note 3)
Word Mode
3.1
9.3
Comments
Excludes 00h programming
prior to erasure
Notes:
1. Typical program and erase times assume the following conditions: 25C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, VCC = 4.5 V (4.75 V for -60), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
1.0 V
12.5 V
1.0 V
VCC + 1.0 V
100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
VIN = 0
7.5
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150C
10
Years
125C
20
Years
34
Am29F400B
PRELIMINARY
PHYSICAL DIMENSIONS
TS 048
48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
1.20
MAX
0
5
16-038-TS48-2
TS 048
DT95
8-8-96 lv
0.08
0.20
0.10
0.21
0.50
0.70
TSR048
48-Pin Reverse Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
SEATING PLANE
0.08
0.20
0.10
0.21
1.20
MAX
0.25MM (0.0098") BSC
0
5
16-038-TS48
TSR048
DT95
8-8-96 lv
0.50
0.70
Am29F400B
35
PRELIMINARY
PHYSICAL DIMENSIONS
SO 044
44-Pin Small Outline Package (measured in millimeters)
44
23
13.10
13.50
15.70
16.30
22
1.27 NOM.
TOP VIEW
28.00
28.40
2.17
2.45
0.10
0.21
2.80
MAX.
0.35
0.50
0.10
0.35
SEATING
PLANE
SIDE VIEW
36
0
8
0.60
1.00
END VIEW
16-038-SO44-2
SO 044
DF83
8-8-96 lv
Am29F400B
PRELIMINARY
REVISION SUMMARY
Revision B
Revision C
Global
Global
Connection Diagrams
AC Characteristics
Revision C+1
Revision C+2
Distinctive Characteristics
AC Characteristics
Am29F400B
37