Radio420X User's Guide 1.

Radio420X
Users Guide

July 2014

Revision history
Revision

Date

Comments

0.1

January 2013

First draft.

1.0

January 2013

Page layout and linguistic revision

1.1

February 2013

Corrections

1.2

March 2013

Corrected error in section 2.2.2

1.3

June 2013

Adjusted standard compliance statements

1.4

September 2013

Changed frequency range upper limit to 3,8 GHz

1.5

November 2013

Integration of the data from caracterisation

1.6

March 2014

2 : Add explanation of the two version of the Radio420X 2.5V and 1.8V
2.1.2 : Add explanation that the clock switch is disabled for the Radio420X 1.8V
2.2.1: Add a second schema for the Radio420 1.8V without the clock switch
Table 10, 13, 14, 15, 16: Add foot note to explain that the clock switch signals are not used for the
Radio420 1.8V
2.2.2: Change Table 3 register values
2.2.3: Add more details on the CPLD SPI register
2.2.4: Figure 2-8, change RX2 port name to IEXMIX2 to clarify input pins used.

1.7

July 2014

TXVGA Gains changed

Up to date for Software Tools Release 6.6

Radio420X User's Guide 1.7

Nutaq All rights reserved.

No part of this document may be reproduced or used in any form or by any meansgraphical, electronic, or
mechanical (which includes photocopying, recording, taping, and information storage/retrieval systems)
without the express written permission of Nutaq.
To ensure the accuracy of the information contained herein, particular attention was given to usage in preparing
this document. It corresponds to the product version manufactured prior to the date appearing on the title page.
There may be differences between the document and the product, if the product was modified after the
production of the document.
Nutaq reserves itself the right to make changes and improvements to the product described in this document at
any time and without notice.
Version 1.7

Trademarks

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Corporation or its subsidiaries in the United States and other countries. Microsoft, MS-DOS, Windows, Windows
NT, and the Windows logo are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries. MATLAB, Simulink, and Real-Time Workshop are registered trademarks of The
MathWorks, Inc. Xilinx, Spartan, and Virtex are registered trademarks of Xilinx, Inc. Texas Instruments, Code
Composer Studio, C62x, C64x, and C67x are trademarks of Texas Instruments Incorporated. All other product
names are trademarks or registered trademarks of their respective holders.
The TM and marks have been omitted from the text.
WARNING

Do not use Nutaq products in conjunction with life-monitoring or life-critical equipment. Failure to observe this
warning relieves Nutaq of any and all responsibility.
FCC WARNING

This equipment is intended for use in a controlled environment only. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of personal computers and peripherals
pursuant to subpart J of part 15 of the FCC rules. These rules are designed to provide reasonable protection against
radio frequency interference. Operating this equipment in other environments may cause interference with radio
communications, in which case the user must, at his/her expense, take whatever measures are required to correct
this interference.

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Radio420X User's Guide 1.7

Table of Contents

Introduction .................................................................................................................... 8
1.1 Conventions .................................................................................................................................................. 8
1.2 Glossary ........................................................................................................................................................ 9
1.3 Technical Support ......................................................................................................................................... 9

Product Description ....................................................................................................... 10

2.1 Hardware Description ................................................................................................................................. 11
2.1.1 Radio420X Top ................................................................................................................................. 12
2.1.2 Radio420X Bottom ........................................................................................................................... 13
2.1.3 Radio420X Front Panel .................................................................................................................... 15
2.2 Component Details ..................................................................................................................................... 16
2.2.1 Clock Distribution Circuit ................................................................................................................. 16
2.2.2 CDCE62005 Operation ..................................................................................................................... 17
2.2.3 I/O Expander CPLDs ......................................................................................................................... 18
2.2.4 RF Path ............................................................................................................................................. 19
2.2.5 RF Chipset ........................................................................................................................................ 22
2.2.6 I/O Expander .................................................................................................................................... 24
2.2.7 FMC Connector ................................................................................................................................ 25
2.2.8 FMC Interface .................................................................................................................................. 25

Specifications ................................................................................................................ 39
3.1 Mechanical .................................................................................................................................................. 39
3.1.1 Radio420S ........................................................................................................................................ 39
3.1.2 Radio420E ........................................................................................................................................ 39
3.1.3 Radio420M ...................................................................................................................................... 39
3.2 Electrical...................................................................................................................................................... 39
3.2.1 Currents ........................................................................................................................................... 39
3.2.2 Overall Power Consumption ............................................................................................................ 39
3.3 Analog Specifications .................................................................................................................................. 40
3.4 Reference Clock Input and Output ............................................................................................................. 40
3.4.1 External Clock Output ...................................................................................................................... 40
3.4.2 Clock Input ....................................................................................................................................... 41
3.5 Onboard Reference TCVCXO ....................................................................................................................... 41
3.6 Acquisition Clock ......................................................................................................................................... 42
3.7 Local RF Oscillator ....................................................................................................................................... 42
3.8 Acquisition PLL Output Frequency Ranges ................................................................................................. 42
3.9 Transmitter ................................................................................................................................................. 43
3.10 Receiver ...................................................................................................................................................... 44
3.11 Full-Scale Input and Output Levels ............................................................................................................. 46
3.12 Local Oscillator Phase Noise ....................................................................................................................... 46
3.13 Minimum Detectable Signal Thresholds ..................................................................................................... 47
3.14 Receiver Operating Curves ......................................................................................................................... 48
3.15 Transmitter Operating Curves .................................................................................................................... 49
3.16 Rx Signal Power Roll-Off ............................................................................................................................. 50

List of Figures and Tables

Figure 2-1 Product number sticker .............................................................................................................................10

Figure 2-2 Radio420X block diagram ..........................................................................................................................11
Figure 2-3 Top view of the Radio420X hardware ........................................................................................................12
Figure 2-4 Bottom view of the Radio420X hardware .................................................................................................13
Figure 2-5 Radio420X front panel ...............................................................................................................................15
Figure 2-6 Clock distribution circuit block diagram of Radio420X 2.5V ......................................................................16
Figure 2-7 Clock distribution circuit block diagram of Radio420X 1.8V ......................................................................16
Figure 2-8 SDR RF path................................................................................................................................................19
Figure 2-9 RDA1005LDS chip .......................................................................................................................................20
Figure 2-10 LMS6002D internal representation .........................................................................................................22
Figure 2-11 A/D and D/A conversion bus interface timing .........................................................................................23
Figure 2-12 LMS6002D TX RF path ..............................................................................................................................23
Figure 2-13 I/O expander pins ....................................................................................................................................24
Figure 2-14 Channels 1 and 2 routing in a Radio420M ...............................................................................................25
Figure 2-15 Channel 1 routing in a Radio420S ............................................................................................................25
Figure 3-1 Low-Band local oscillator phase noise .......................................................................................................46
Figure 3-2 High-Band local oscillator phase noise ......................................................................................................47
Figure 3-3 Minimum detectable signal as a function of VGA1 setting ........................................................................47
Figure 3-4 Low-band receiver operating curves .........................................................................................................48
Figure 3-5 High-band receiver operating curves .........................................................................................................48
Figure 3-6 Low-band transmitter operating curves ....................................................................................................49
Figure 3-7 High-band transmitter operating curves ...................................................................................................49
Figure 3-8 Rx signal power roll-off (see table x in section 3.10 for detailed roll off) ..................................................50
Table 1 Glossary ............................................................................................................................................................9
Table 2 Parameters that cannot be modified .............................................................................................................17
Table 3 CDCE62005 registers configuration example .................................................................................................18
Table 4 I/O expander CPLD bit assignments ...............................................................................................................19
Table 5 Low-band filters .............................................................................................................................................21
Table 6 High-band filters .............................................................................................................................................21
Table 7 I/O expander pin assignments........................................................................................................................24
Table 8 Radio420S A/D conversion data path related pin assignments .....................................................................26
Table 9 Radio420S D/A conversion data path related pin assignments .....................................................................27
Table 10 Radio420S clock, control and SPI pin assignments.......................................................................................29
Table 11 Radio420M A/D conversion data path related pin assignments ..................................................................30
Table 12 Radio420M D/A conversion data path related pin assignments ..................................................................30
Table 13 Radio420M clock, control and SPI pin assignments .....................................................................................32
Table 14 Radio420S low-pin-count connector pin assignments .................................................................................34
Table 15 Radio420M high-pin-count connector pin assignments (1) .........................................................................36
Table 16 Radio420M high-pin-count connector pin assignments (2) .........................................................................38
Table 17 Analog input .................................................................................................................................................40
Table 18 Analog output...............................................................................................................................................40
Table 19 Onboard reference TCVCXO specifications ..................................................................................................41
Table 20 Acquisition clock specifications ....................................................................................................................42
Table 21 Local RF oscillator specifications ..................................................................................................................42
Table 22 Acquisition PLL output frequency ranges .....................................................................................................42
Table 23 Transmitter specifications (1) .......................................................................................................................43
6

Radio420X User's Guide 1.7

Table 24
Table 25
Table 26
Table 27

Transmitter specifications (2)....................................................................................................................... 44

Receiver specifications (1) ............................................................................................................................ 44
Receiver specifications (2) ............................................................................................................................ 45
Full-scale input and output levels ................................................................................................................ 46

1 Introduction

Congratulations on the purchase of the Radio420X FMC.

This document contains all the information necessary to understand and use the Radio420X. It should be read
carefully before using the card and stored in a handy location for future reference.

1.1 Conventions
In a procedure containing several steps, the operations are numbered (1, 2, 3). The diamond () is used to
indicate a procedure containing only one step, or secondary steps. Lowercase letters (a, b, c) can also be used to
indicate secondary steps in a complex procedure.
The abbreviation NC is used to indicate no connection.
Capitals are used to identify any term marked as is on an instrument, such as the names of connectors, buttons,
indicator lights, etc. Capitals are also used to identify key names of the computer keyboard.
All terms used in software, such as the names of menus, commands, dialog boxes, text boxes, and options, are
presented in bold font style.
The abbreviation N/A is used to indicate something that is not applicable or not available at the time of press.
Note:

The screen captures in this document are taken from the software version available at the time of press. For this
reason, they may differ slightly from what appears on your screen, depending on the software version that you are
using. Furthermore, the screen captures may differ from what appears on your screen if you use different
appearance settings.

Radio420X User's Guide 1.7

1.2 Glossary
This section presents a list of terms used throughout this document and their definition.
Term

Definition

Application programming interface (API)

An application programming interface is the interface that a computer system, library, or

application provides to allow requests for services to be made of it by other computer
programs or to allow data to be exchanged between them.

Base design

Empty design or template that is incapable of data processing and is not instantiated in
the custom logic of the boards FPGA.

Board software development kit

Abbreviated BSDK, this kit gives users the possibility to quickly become fully functional
developing C/C++ or assembly code for the DSP and HDL code for the FPGA through an
understanding of all Nutaq boards major interfaces.

Chassis

Refers to the rigid framework onto which the CPU board, Nutaq development platforms,
and other equipment are mounted. It also supports the shell-like casethe housing that
protects all the vital internal equipment from dust, moisture, and tampering.

cPCI

Short for CompactPCI, refers to a 3U or 6U Eurocard-based industrial computer where the

all boards are connected through a passive PCI backplane.

Default design

Design loaded by default on Nutaq boards used for FPGA design.

Digital signal processing

Digital signal processing is the study of signals in a digital representation and the
processing methods of these signals. The algorithms required for DSP are sometimes
performed using specialized devices that use specialized microprocessors called digital
signal processors (DSP).

Digital signal processor (DSP)

A digital signal processor is a specialized microprocessor designed specifically for digital

signal processing, generally in real time.

Example

Refers to examples used to demonstrate functions or applications supplied with the board
software development kit. For this reason, examples come in two flavors: application
examples and functional examples.

HDL

Stands for hardware description language.

Host

A host is defined as the device that configures and controls a Nutaq board. The host may
be a standard computer or the CPU board of the cPCI chassis system where the Nutaq
board is installed. You can develop applications on the host for Nutaq boards through the
use of an application programming interface (API) that comprises protocols and functions
necessary to build software applications. These API are supplied with the Nutaq board.

Model-based design

Refers to all the Nutaq board-specific tools and software used for development with the
boards in MATLAB and Simulink and the Nutaq model-based design kits.

Reception

Any data received by the referent is a reception. Abbreviated RX.

Reference design

Blueprint of an FPGA system implanted on Nutaq boards. It is intended for others to copy
and contains the essential elements of a working system (in other words, it is capable of
data processing), but third parties may enhance or modify the design as necessary.

Software development

Refers to development performed with and for the board with a software development
kit. Software development for a board comes in three flavors: host software development,
DSP software development, and FPGA software development.

Transmission

Any data transmitted by the referent is a transmission. Abbreviated TX.

VHDL

Stands for VHSIC hardware description language.

Table 1 Glossary

1.3 Technical Support

Nutaq is firmly committed to providing the highest level of customer service and product support. If you
experience any difficulties using our products or if it fails to operate as described, first refer to the documentation
accompanying the product. If you find yourself still in need of assistance, visit the technical support page in the
Support section of our Web site at www.nutaq.com.

2 Product Description

The Radio420X FPGA mezzanine card (FMC) is a powerful multimode SDR RF transceiver module designed around
the state-of-the-art, multi-standard, multiband Lime Microsystems LMS6002D RF transceiver IC, which supports
broadband coverage, as well as TDD (Time Division Duplex) and FDD (Frequency Division Duplex) full duplex modes
of operation. The LMS6002D RF transceiver IC bandwidth (1.528 MHz), selectable at will, makes it suitable for a
large number of narrowband and broadband applications with excellent channel selectivity. Combined with
multiple references and synchronization modes, the Radio420X is suited for such applications as multimode
software-defined radio (SDR), advanced telecommunications (MIMO systems, cognitive radios, LTE, WiMAX, white
space, Wi-Fi, GSM, WCDMA), and signal intelligence (SIGINT).
Two different Radio420X FMC card are available. The first one, the Radio420X 2.5V, needs the VADJ supply provided
by the carrier board to be at 2.5V. The Radio420X 2.5V can only be powered from a 2.5V VADJ and should not be
plugged into a carrier board that does not support this voltage.
The second one, the Radio420X 1.8V, needs the VADJ supply provided by the carrier board to be at 1.8V. The
Radio420X 1.8V can only by powered from a 1.8V VADJ and should not be plugged into a carrier board that does not
support this voltage.
This document describes the Radio420X hardware for both the 2.5V and 1.8V version. For most characteristics, the
cards are identical. If not, extra information will explain which features are different between the 2.5V and 1.8V
version.
The Radio420X 2.5V FMC cards have a product number that begin with 800-579 while the Radio420X 1.8V FMC
cards have a product number that begin with PRD-696. The product number of your Radio420 FMC is indicated just
above the serial number of the card on a sticker similar to the ones showed in the image below.

Figure 2-1 Product number sticker

Outstanding features

10

SISO, dual-band and 22 MIMO RF transceivers

Wide frequency range 300 MHz3.8 GHz

Selectable bandwidth 1.528 MHz

Multiple reference configurations and expansion modes

Individually shielded RX and TX analog paths

Radio420X User's Guide 1.7

2.1 Hardware Description

This section presents the Radio420X hardware from a functional standpoint; introducing its parts and their
functions.

Figure 2-2 Radio420X block diagram

11

2.1.1 Radio420X Top

Figure 2-3 Top view of the Radio420X hardware

1- SPI expander/Level translation CPLD

Used as an I/O expander giving access to a number of pins that do not need a high rate of update such as
the PLL function, lock state, band selection and RX RF filter selection.
Note:

Because the CPLD is present in the JTAG configuration chain, you must take care not to erase it.
2- Serial, 16-bit D/A converter
This digital-to-analog converter is based on the Analog Devices LTC2641. It is a 50 MHz, 16-bit device
connected to the voltage adjustment pin of the reference clock to adjust its frequency. So doing, you can
adjust the clock to compensate for its aging or to synchronize an external GPS clock with the proper FPGA
core. Contact Nutaq for details about this core.
3- Custom filter expansion
In each RX band, there is a path linking a pair of micro-coaxial connectors that allow users to connect their
own RF filter to the system.
4- Level translation CPLD
This CPLD is used as an I/O translator/buffer for some of the SPI chain signals and for the external I/O
expander. See the I/O Expander section for details.
Note:

Because the CPLD is present in the JTAG configuration chain, you must take care not to erase it.
5- Expansion FMC connector
To support 22 MIMO, the Radio420X uses a second low-pin-count (LPC) connector to route the second
channel to the high-pin-count (HPC) connector of the master FMC. See the FMC Connector section for
details.
The Radio420M complies with all the electrical specifications of VITA57.1, but the height of the module fails
to comply with the mechanical specifications. An additional 10 mm in height must therefore be allotted
when using the Radio420M on an FMC carrier other than Nutaqs Perseus AMC. On Nutaqs Perseus AMC, it
fits in a full-size TCA slot. See the Specifications chapter for details.

12

Radio420X User's Guide 1.7

6- Analog test points
These connectors, labeled J2 to J9 on the PCB, are connected to the RF chipset. They give access to the A/D
and D/A converters baseband signal (BBS). They can be used to probe the BBS.
Note:

Using these test points for another purpose than probing is not recommended. Nutaq doesnt supply
information about these signals.

2.1.2 Radio420X Bottom

Figure 2-4 Bottom view of the Radio420X hardware

1- Clock distributor
Micrel SY89540U. This low-jitter, LVDS cross-point switch enables routing different clocks on the Radio420X.
This chip can only operate at 2.5V and is disabled on the Radio420X 1.8V FMC card. See the Clock
Distribution Circuit section for details.
2- Internal reference clock
The 30.72-MHz, 2-PPM, temperature-compensated, voltage-controlled crystal oscillator (TCVCXO) driving
the PLL. For details about this clock, see the Clock Distribution Circuit section.
Note:

Revision A and B of the Radio420 FMC had an internal reference clock of 10 MHz.
3- Clock generator/PLL synthesizer
The Texas Instruments CDCE62005. It supplies all the clocks necessary to the Radio420X. The FMC uses the
30.72-MHz clock or the external clock as references to clock the CDCE62005 internal voltage-controlled
oscillator (VCO). The VCO clock is fed to the distribution circuit clocking the entire system. For details about
the clock, see the Clock Distribution Circuit section.
4- I2C EEPROM
Every FMC is equipped with a serial I2C EEPROM to identify itself to its carrier board. The I2C EEPROM
contains information such as the type of hardware, the onboard FPGA, and interfaces used.

13

5- FMC connector
The Radio420X is equipped with an FMC connector used to interface with HPC FMCs such as Nutaqs
Perseus. The Radio420X uses the HPC connector on the Radio420M and an LPC connector on the
Radio420S. The connector uses LA00 to LA32 for channel 1 and HA00HA17 and HB00HB14 to
communicate with channel 2 of the Radio420M. Finally, the connector needs CLK0 as its FPGA system clock.
See the FMC Connector section for details.
6- RF chipset
This is the heart of the systemthe LMS6002D; a fully integrated, multiband, multi-standard, single-chip RF
transceiver. Integrated, high-performance, 12-bit A/D and D/A converter blocks mean that the device can
be directly interfaced to any femtocell baseband IC on the market. The LMS6002D has a standard serial port
interface (SPI) for programming and includes provisions for full calibration. The device combines LNA, PA
driver, RX/TX mixers, RX/TX filters, synthesizer, RX gain control, and TX power control with very few external
components.
7- Intermediate power rail
This step-down switching mode power supply converts the 12 V supplied by the FMC carrier to 5.5 V. The
output is filtered and supplies several linear regulators so they can generate the 1.8 V, 3.3 V, and 5 V
needed by the devices on the Radio420X.
8- Reception filter bank
The RF filter section is divided in two: the low band and high band sections. Each allows users to select a
band filter that suits their needs. A total of 16 bands and pass-through filters are available.
9- Reception band selection switch
This switch allows users to select between the low-band and high-band matching circuits of the RX RF
transceiver.
10- Reception amplifier
Based on RFMD RDA1005L, this amplifier is used to provide full control of the RF input. This wideband
circuit provides up to 18 dB of gain and can be used as an attenuator.
11- Transmission preamplifier
Based on the RFMD RDA1005L, this amplifier is used to provide full control of the RF output. This wideband
circuit provides up to 18 dB of gain and can be used as an attenuator, making it possible to reach 10 dBm of
output power with a good signal-to-noise ratio (SNR).
12- Transmission band selection switch
This switch allows you to select between the low-band and the high-band matching circuits of the TX RF
transceiver.

14

Radio420X User's Guide 1.7

2.1.3 Radio420X Front Panel

Figure 2-5 Radio420X front panel

External clock (Rout)

The external reference clock output connector, labeled J16 on the PCB, is an MMCX-type, 50- output
impedance connector. The output signal is LVCMOS 3.3 V and DC coupled. As a clock output, the connector
is routed to the clock generator. It can be used as a reference output clock to synchronize external
equipment with the Radio420X. This connector is also used to synchronize a second Radio420X when under
MIMO configuration. For details about the clock output, see the Clock Distribution Circuit section.
External clock (Rin)
The external reference clock input connector, labeled J17 on the PCB, is an MMCX-type, 50- input
impedance connector. The input signal is LVCMOS 3.3 V and AC coupled. As a clock input, the connector is
routed to the clock generator input. The external clock input can be used as a PLL reference clock by the
Radio420X to synchronize the card with external equipment. For details about the clock output, see the
Clock Distribution Circuit section.
TX RF connector (TX)
The transmission RF output channel connector, labeled J18 on the PCB, is an MMCX-type, AC-coupled, 50-
output impedance connector. It is connected to the transmission circuit of the RF front end. This output can
deliver full-scale power between 21.5 dBm and 10.0 dBm. See the Full-Scale Input and Output Levels
section for details.
RX RF connector (RX)
The reception RF input channel connector, labeled J19 on the PCB, is an MMCX-type, AC-coupled, 50-
input impedance connector. It is connected to the reception circuit of the RF front end. This input connector
can accept power up to 20 dBm. See the Full-Scale Input and Output Levels section for details.
PPS input connector (PPS in)
The one-pulse-per-second input connector, labeled J21 on the PCB, is an MMCX-type connector routed to
the FPGA where. It can be used for synchronization or as a trigger signal. The input is a standard 3.3-V
LVCMOS input. To be compatible with the FPGA, it is routed through a 2.5-V voltage translator. When it is
used with the proper FPGA core, this input can be used to receive a 1-PPS signal to discipline the internal
reference clock. See the I/O Expander section for details.
I/O expander connector
The I/O expander connector is based on the HDMI format and offers a total of nine custom inputs and
outputs. The I/Os are 3.3-V LVCMOS and pass through a CPLD for buffering to protect the FPGA. This
connector is a custom interface for the RF design if, for example, it needs external control by an external
power amplifier. See the I/O Expander section for details.

15

2.2 Component Details

2.2.1 Clock Distribution Circuit
The clock distribution circuit is based on the Texas Instruments CDCE62005 device and is a high-performance,
low-phase noise, low-skew clock synthesizer/synchronizer that matches the internal VCO frequency with a
reference clock. The Radio420X is equipped with a 2-PPM, 30.72-MHz, temperature-compensated, and
voltage-controlled reference clock (TCVCXO) that acts as a time base. An external reference clock can also be used
through the external clock input connector (see above). All this allows almost any frequency in the A/D, D/A, and
RF PLL clock range. The CDCE62005 is equipped with a programmable VCO loop filter that can be optimized to suit
specific needs.
To draw the best performances from the reference clock, a small, high-resolution serial D/A converter drives the
TCVCXO. This configuration is used to compensate for the drift in clock frequency over time. In addition, when used
with the proper Nutaq core and the 1-PPS input, the reference clock can be slaved to a 1-PPS signal from a GPS, to
synchronize distant systems. Inquire about core details.
The figure 2-6 shows the clock distribution of the Radio420 2.5V while the figure 2-7 shows the clock distribution of
the Radio420 1.8V.
16 bit
SPI DAC

DAC SPI

Translator
CPLD

SPI

VCXO
30.72MHz

IN1

SPI

LockDetect

RefSel
~PD
~Sync

SPI IO Exp
CPLD

FMC

SPI

RX_CLK

PLL - TI
TX_CLK
cdce62005

LockDetect

DIV0

PLL_CLK

DIV1

TX_CLK

DIV2

RX_CLK

LMS6002D

Clock Out
3V3

DIV4

FMC CLK2
FMC CLK3

DIV3

IN2

Ref out clk

CTRL
0 resistors switch.
Default is from Clock In
IN3
OUT0

FMC CLK0

OUT2

FMC CLK1

OUT3

4x4 CrossSwitch
SY89540UMG

Clock In
3V3
LVCMOS->LVPECL
Translator
MC10EPT20DT

IN2
IN1

PPS
3V3

IN0

1PPS

3.3V->2.5V
Translator

Figure 2-6 Clock distribution circuit block diagram of Radio420X 2.5V

DAC SPI

SPI

Translator
CPLD

LockDetect

FMC

SPI

16 bit
SPI DAC

VCXO
30.72MHz

IN1

SPI

RX_CLK

PLL - TI
TX_CLK
cdce62005

LockDetect

SPI IO Exp
CPLD

RefSel
~PD
~Sync

DIV0

PLL_CLK

DIV1

TX_CLK

DIV2

RX_CLK

LMS6002D

Clock Out
3V3

DIV4

IN2

DIV3

Ref out clk

Clock In
3V3
LVCMOS->LVPECL
Translator
MC10EPT20DT

PPS
3V3
1PPS

3.3V->1.8V
Translator

Figure 2-7 Clock distribution circuit block diagram of Radio420X 1.8V

16

Radio420X User's Guide 1.7

2.2.2 CDCE62005 Operation

To use the Radio420X, a minimum set of parameters must be configured. The following is a short list of settings
that cannot be modified when programming the CDCE62005.
Note:

These parameters are automatically handled when using the Nutaq BSDK with a Perseus. Refer to the CDCE62005
data sheet for details.
Description

Value

Frequency range

Connection

Output 0 standard

LVCMOS

2341 MHz*

RF chipset PLL clock

Output 1 standard

LVCMOS

080 MHz

RF chipset D/A clock

Output 2 standard

LVCMOS

080 MHz

RF chipset A/D clock

Output 3 standard

LVCMOS

0250 MHz

External clock output

Output 4 standard

LVDS

080 MHz

FPGA D/A system clock

Primary input standard

LVCMOS

0250 MHz

30.72 MHz reference

clock
(10 MHz on Rev A and B)

Secondary input standard

LVDS

0250 MHz

External clock input

Table 2 Parameters that cannot be modified

Even if the LMS6002D is compatible with this frequency range, it is effectively limited to the LMS VCO loop filter.
Nutaq recommends using a frequency near 30 MHz. See Figure 2-10 on page 22 for details.
The PLL is a complex device. Before attempting to program it, read its data sheet. Texas Instruments also supplies
the CDCE62005 EVM Control Software. The software does not fall within the scope of the present document, but it
should help the user find the appropriate register values.
SISO configuration

Table 3 can be used as a starting point to configure the PLL for the following parameters:

Use the internal 30.72 MHz LVCMOS as the reference clock for the VCO and for the phase-frequency
detector (PFD).

Configure output 0: LSM6002D reference clock to 30.72 MHz (bypass mode).

Configure outputs 1 and 2: LMS6002D RX and TX acquisition clock to 61.44 MHz.

Configure output 3: External clock to 30.72 MHz (bypass mode).

Configure output 4: FPGA design clock (FMCCLK0) to 61.44 MHz.

Address

Value

00

02140002

01

02105030

02

02104030

17

Address

Value

03

02140000

04

0EB04031

05

028001A4

06

0A680004

07

0BD887BF

08

020009CD

Table 3 CDCE62005 registers configuration example

Refer to the document entitled Programmer's Reference Guide Radio420, provided with the Radio420X card, for
details about SPI programming of the chip.
MIMO configuration

When using the Radio420M, the second channel must be configured differently. Instead of using the internal
reference clock, it must be configured to use the external clock input.

Use the secondary LVPECL input as reference with the DC internal termination enabled.

Configure output 0: LMS6002D reference clock to 30.72 MHz (bypass mode).

Configure outputs 1, 2, and 4: LMS6002D RX, TX acquisition clock, and FPGA design clock to 61.44 MHz or
other sampling frequencies.

Configure output 3: External clock to 30.72 MHz (bypass mode).

2.2.3 I/O Expander CPLDs

The Radio420X is equipped with two CPLDs acting as serial I/O expander and I/O translator (from VADJ to 3.3V).
The SPI I/O expander takes care of signals whose timing is not critical such as the RX filter selection, RX band
selection, TX band selection, PLL power down, and PLL sync. These signals are connected to an internal serial
register, itself connected to the SPI chain of the CDCE62005.
From the SPI bus point of view, the CPLD act like a 32-bit register. The signals are assigned as follows:

18

Bit

Bit name

Description

A0

Bit 0 of the targeted register

A1

Bit 1 of the targeted register

A2

Bit 2 of the targeted register

A3

Bit 3 of the targeted register

PLL sync

PLL power down

Reserved

Connected to the CDCE62005 ~SYNC pin.

Connected to the CDCE62005 ~Power_Down pin.
Reserved

Radio420X User's Guide 1.7

Bit

Bit name

Description

RxHighBandSel

Select the RX high band when set to 1.

TxLowBandSel

Select the TX low band when set to 1.

RxFbSel0

RX filter bank selection bit 0.

10

RxFbSel1

RX filter bank selection bit 1.

11

RxFbSel2

RX filter bank selection bit 2.

Table 4 I/O expander CPLD bit assignments

To perform a write transaction on the bits 4 to 11, the address bits (0 to 3) must be 1010 (0xA). The CPLD SPI bus
is shared with the PLL (CDCE62005) chip and both the CPLD and the PLL have their own dedicated chip select (CS)
signal.
The MOSI signal is latch at the CLK rising edge when the CPLD CS is low. The LSB must be sent first and the MSB
last. The data length must be exactly 32 bits since the SPI core use a shift register to store the input data. Once the
CPLD CS goes high, the shift register value is applied to the CPLD output is the received address (Bit 0 to 3) equals
0xA. When not transferring new data, the CPLD CS must be kept high to avoid corrupting its internal register.
To initialize a new transfer, pull down the CPLD CS (FMC G30), apply the first data bit on the MOSI signal (FMC H20)
and on the next CLK (FMC G19) rising edge, the bit will be latched. When the last bit (MSB) is latched on the CLK
rising edge, the CPLD CS signal can be pulled high.

2.2.4 RF Path
Even though the LMS6002D is an integrated RF chipset, several external components must be added to receive and
transmit an RF signal.

Figure 2-8 SDR RF path

Transmission
The transmission path is divided in two: low and high bands. The differences between the two are the
matching component between the LMS6002D and the RF balun. After the RF transformer, the signal passes
a low-loss selector switch to isolate the low band and the high band. An amplifier, based on the
RDA1005LDS boosts the signal up to 10 dBm before it arrives at the antenna.

19

Due to its large frequency coverage, the Radio420X does not come with a TX filter. Users must supply their
own external filter according to the target frequency. The filter must have an impedance of 50 and be
capable of handling a minimum power of 25 dBm.
Reception
The reception path starts at the antenna, where the signal is amplified by a variable gain amplifier based on
the RDA1005LDS chip. This provides a simple way of controlling the signal gain according to the application.
The signal is then routed by a selector switch between the low-band and high-band paths. The signal goes
through a pair of 8-to-1 selectors and the desired RF band-pass filter.
If the low-band path is selected the signal goes through a balun and a matching circuit, and it then goes on
to the RX1 input of the LMS6002D.
Because of RF matching and bandwidth constraints, the LMS6002D RX2 VGA stage is completely bypassed
by the high-band path. This is why the high-band path enters inside the LMS6003D chip by the IEXMIX2 pins
instead of RX2. So doing, we added a 23-dB LNA between the filter and the matching balun to compensate
for the LMS LNA before entering the RX2 mixer of the RF chipset.
To use the high-band path, the user must configure the LMS6002D so that it uses the mixer input 2 as the
RF source. See the RF Chipset section for details.
RF gain
Each RF section is equipped with a RDA1005LDS, which supplies broadband gain ranging from 50 MHz to
4 GHz with up to 18 dB of gain with the serial interface. For both RF paths, the attenuator is followed by the
18-dB amplifier. Its fast serial interface allows rapid gain changes to adapt the signal to the applications.

Figure 2-9 RDA1005LDS chip

RX filter banks
Each reception path incorporates a filter bank used to band pass the signal. Each filter bank is a combination
of filters, pass-through path, and external connections.
The pass-through path is a simple 0- connection between the filter selection switch input and output. The
external connections are micro-coaxial connectors used to connect the users own filters. Cables compatible
with Emerson UMCC series number 128-0711-201 must be used.

20

Radio420X User's Guide 1.7

Select the filter by sending a command to the I/O expander CPLD so that it sets the RxFbSelX bits.
Filter port
number

Frequency (MHz)

Bandwidth (MHz)

00

881.5

25

01

836.5

25

02

CustomJ11 input

CustomJ10 output

03

942.5

35

04

897.5

35

05

Pass through

N/A

06

1747.5

75

07

1842.5

75

Table 5 Low-band filters

Note:

Filters 6 and 7 are out of the normal operation band for the RX low-band channel on Radio420X revisions A and B.
Filter port number

Frequency (MHz)

Bandwidth (MHz)

00

2140

60

01

1950

60

02

CustomJ14 input

CustomJ13 output

03

1960

60

04

1880

60

05

Pass through

N/A

06

2495

390

Table 6 High-band filters

Note:

Filter 7 is out of the normal operation band for the RX high-band channel on Radio420X revisions A and B.

21

2.2.5 RF Chipset
LMS6002D from Lime Microsystems. The chip is a fully integrated RF transceiver. It can convert signals from the
analog RF to the digital baseband. The chip can be divided in two: the digital and the analog parts.
At the time of writing this guide, the LMS6002D data sheet was available only upon request from Lime
Microsystems. Nutaq recommends that you acquire this data sheet and the latest version of the Programming and
Calibration Guide. Contact enquiries@limemicro.com.

Figure 2-10 LMS6002D internal representation

Digital data path

The LMS6002D is equipped with two receiving 12-bit A/D converters and two transmitting 12-bit D/A converters.
These converters can run at up to 40 MSPS. In transmission and reception, one converter is used to handle the real
part of analog signals named I, while in transmission the second converter handles the imaginary part of analog
signals named Q. To pass I and Q information on the same bus, data is multiplexed/interleaved on the bus at
twice the conversion speed. So, if you need a 40-MSPS conversion rate, the bus must be clocked at 80 MHz. The
IQ_SEL signal identifies the sample destination. By default, Nutaq configures the converters to use the rising edge
of the clock. See Figure 2-11 on page 23 for timing information.
A/D conversion data with the IQ_SEL is fed to the FPGA through the FMC connector with a copy of the RX clock.
The carrier can use the clock to sample data synchronously.
D/A conversion data must be forwarded with an IQ_SEL signal so it can be transmitted. As the clock must be as
clean as possible in such cases, the Radio420X D/A clock source is the PLL, not the FPGA. So doing, the phase
relationship between the FPGA clocked by FMCCLK0 and the TXCLK is necessarily aligned. Respecting timing is
important; should there be timing issues on the D/A conversion bus, adding a phase delay to the TXCLK output of
the CDCE62005 or on the FPGA data bus would realign the bus.
Note:

Even if the LMS6002D supports different A/D and D/A conversion rates, Nutaqs software for the Perseus limits
using the same clock speed in the A/D and D/A conversion processes at this time.
Refer to the LMS6002D data sheet for more information.

22

Radio420X User's Guide 1.7

Figure 2-11 A/D and D/A conversion bus interface timing

Internal TX RF path

All the information about this path is available in the LMS6002D data sheet and programming guide. This
presentation is only an overview.

Figure 2-12 LMS6002D TX RF path

Transmission
Transmission consists of only four stages. The first stage is the transmission low-pass filter (TXLPF)a
programmable bandwidth baseband filter that filters the D/A conversion image. The filter can be configured
anywhere between 0.75 MHz and 14.0 MHz, for a maximum IQ bandwidth of 28 MHz. The second stage
involves the filtered analog signal being fed to an amplifier whose gain can be configured between -35 dB
and -4 dB. In the third stage, the signal enters a mixer. Finally, depending on the selected band, the signal
passes through the TXVGA2 amplifier that adds a maximum of 25 dB.
Reception
Depending on the selected band, one of the LNA is bypassed to resolve reception problems. The low-band
input is amplified by LNA1 and the high-band input is directly forwarded to the mixer. After going through
the mixer, the baseband signal is fed to RXVGA1, which can apply a gain of up to 30 dB on the signal. The
programmable baseband filter performs low-pass filtering between 0.75 MHz and 14.0 MHz on the I and Q
analog signals. A final stage of a maximum of 30 dB is applied before the A/D converters.

23

2.2.6 I/O Expander

The Radio420X is equipped with a set of general-purpose I/Os used as external controls, such as a power amplifier
or RF switching matrix. The connector is based on a HDMI type D model connector, which provides up to nine
supplemental I/Os.
Nutaq has only based its connector design on the type D HDMI connector. There stops the similarity with HDMI
standards. The pin assignments and I/O standard are entirely different. To facilitate design, Nutaq offers an HDMI
GPIO expansion prototyping card that can connect directly to the HDMI cable, expanding the type D connector to a
pad matrix. Contact Nutaq for more information.
All the I/O signals are buffered by the translator CPLD. By doing this the FPGA is protected and used as an I/O
translator to go from the 3.3 V to the FPGA 2.5 V. By default, the CPLD is configured with two inputs and seven
outputs. If this configuration is not adequate, contact Nutaq.
Default pin assignments are as follows:

Figure 2-13 I/O expander pins

Pin

GPIO

Pin

GPIO

NC

NC

In0

GND

In1

Out2

GND

Out3

Out4

10

GND

11

Out5

12

Out6

13

GND

14

Out7

15

InPPS

16

GND

17

FMC_SCL

18

FMC_SDA

19

3.3 V

Table 7 I/O expander pin assignments

WARNING

1- The electrical level is 3.3 V LVCMOS. The maximum I/O current drive is 20 mA. Overvoltage, overcurrent, or
contention can seriously damage the CPLD and the carrier FPGA.
2- Pin 15, named InPPS, is directly connected to the front panel PPS input connector, so only one connection must
be used at a time.

24

Radio420X User's Guide 1.7

2.2.7 FMC Connector

The Radio420X is designed to function on any carrier with a low-pin-count (LPC) FMC connector. Under the FMC,
the Radio420X is equipped with a high-pin-count (HPC) connector completely compatible with LPC sockets, but
including extra pins, to interface with an FMC carrier. On top of the Radio420E there is also an LPC connector.
These two connectors allow cascading a Radio420S and Radio420E (a Radio420S with an additional connector to
cascade another Radio420S), yielding a two-channel systemthe Radio420M (where M stands for MIMO).
Figure 2-14 illustrates the FMC connections of Radio420M. The HPC connectors are shown as containing LPC pins
and HPC pins. The LPC connectors only contain LPC pins.

Figure 2-14 Channels 1 and 2 routing in a Radio420M

The MIMO configuration is only possible with carriers supporting HPC FMC connections. In such systems, the LPC
pins from the carrier are directly routed to channel 1 of the Radio420M. The HPC pins from the carrier are routed,
through channel 1 LPC connection, directly to channel 2 of the Radio420M.

Figure 2-15 Channel 1 routing in a Radio420S

WARNING

Cascading Radio420S with a Radio420E to make a Radio420M is only possible with these two FMCs because HPC
connectors do not have enough pins to route more channels.

2.2.8 FMC Interface

The Radio420X is equipped with a VITA 57.1 FMC high-pin-count connector to interface with FMC carriers such as
the Nutaq Perseus. The FMC interface creates a high-bandwidth path between the carrier card and the Radio420X.
A low-pin-count carrier or a high-pin-count carrier can be used with a Radio420S but a high-pin-count one is
necessary when using a Radio420M.
Vadj setting

To function, the Radio420X 2.5V needs the FMC carrier Vadj output to be 2.5V. For the Radio420X 1.8V, the FMC
carrier needs the Vadj output to be 1.8V

25

WARNING

A Vadj value other than 2.5V could damage the Radio420X FMC 2.5V.
A Vadj value other than 1.8V could damage the Radio420X FMC 1.8V.
FMC connector pin assignments

To function correctly, the FMC carrier connected to the Radio420X must have the following connected pins: LA00
to LA33, HA00 to HA11. The following tables show the Radio420X FMC connector pin assignment on the FMC bus.
The assignments are divided into three sections: A/D data path, D/A data path, and Radio420X control.
Radio420S low-pin-count connector
FMC pin on
P1

Pin name

Design
name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

LMS6002D

D14

LA09_P

RXEN

LVCMOS25 / LVCMOS18

Output

RXEN

G6

LA00_P_CC

RXCLK

LVCMOS25 / LVCMOS18

Input

RXCLKOUT

G7

LA00_N_CC

RXIQSEL

LVCMOS25 / LVCMOS18

Input

RXIQSEL

D8

LA01_P

RXD0

LVCMOS25 / LVCMOS18

Input

RXD0

D9

LA01_N

RXD1

LVCMOS25 / LVCMOS18

Input

RXD1

H7

LA02_P

RXD2

LVCMOS25 / LVCMOS18

Input

RXD2

H8

LA02_N

RXD3

LVCMOS25 / LVCMOS18

Input

RXD3

G9

LA03_P

RXD4

LVCMOS25 / LVCMOS18

Input

RXD4

G10

LA03_N

RXD5

LVCMOS25 / LVCMOS18

Input

RXD5

H10

LA04_P

RXD6

LVCMOS25 / LVCMOS18

Input

RXD6

H11

LA04_N

RXD7

LVCMOS25 / LVCMOS18

Input

RXD7

D11

LA05_P

RXD8

LVCMOS25 / LVCMOS18

Input

RXD8

D12

LA05_N

RXD9

LVCMOS25 / LVCMOS18

Input

RXD9

C10

LA06_P

RXD10

LVCMOS25 / LVCMOS18

Input

RXD10

C11

LA06_N

RXD11

LVCMOS25 / LVCMOS18

Input

RXD11

Table 8 Radio420S A/D conversion data path related pin assignments

26

Radio420X User's Guide 1.7

FMC pin on
P1

Pin name

Design
name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

LMS6002D

D15

LA09_N

TXEN

LVCMOS25 / LVCMOS18

Output

TXEN

D21

LA17_N

TXIQSEL

LVCMOS25 / LVCMOS18

Output

TXIQSEL

C22

LA18_P

TXD0

LVCMOS25 / LVCMOS18

Output

TXD0

C23

LA18_N

TXD1

LVCMOS25 / LVCMOS18

Output

TXD1

H22

LA19_P

TXD2

LVCMOS25 / LVCMOS18

Output

TXD2

H23

LA19_N

TXD3

LVCMOS25 / LVCMOS18

Output

TXD3

G21

LA20_P

TXD4

LVCMOS25 / LVCMOS18

Output

TXD4

G22

LA20_N

TXD5

LVCMOS25 / LVCMOS18

Output

TXD5

H25

LA21_P

TXD6

LVCMOS25 / LVCMOS18

Output

TXD6

H26

LA21_N

TXD7

LVCMOS25 / LVCMOS18

Output

TXD7

G24

LA22_P

TXD8

LVCMOS25 / LVCMOS18

Output

TXD8

G25

LA22_N

TXD9

LVCMOS25 / LVCMOS18

Output

TXD9

D23

LA23_P

TXD10

LVCMOS25 / LVCMOS18

Output

TXD10

D24

LA23_N

TXD11

LVCMOS25 / LVCMOS18

Output

TXD11

Table 9 Radio420S D/A conversion data path related pin assignments

FMC pin
on P1

Pin name

Design name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

Connection

H4

CLK0_M2C_P

FMC_CLK0_P

LVDS

Input

CLK MUX1

H5

CLK0_M2C_N

FMC_CLK0_N

LVDS

Input

CLK MUX1

G2

CLK1_M2C_P

FMC_CLK1_P

LVDS

Input

CLK MUX1

G3

CLK1_M2C_N

FMC_CLK1_N

LVDS

Input

CLK MUX1

H16

LA11_P

CLKMUX_SOUT0

LVCMOS25 / -

Input

CLK MUX1

H17

LA11_N

CLKMUX_SOUT1

LVCMOS25 / -

Input

CLK MUX1

G15

LA12_P

CLKMUX_SIN0

LVCMOS25 / -

Output

CLK MUX1

G16

LA12_N

CLKMUX_SIN1

LVCMOS25 / -

Output

CLK MUX1

27

28

D17

LA13_P

CLKMUX_CONF

LVCMOS25 / -

Output

CLK MUX1

D18

LA13_N

CLKMUX_LOAD

LVCMOS25 / -

Output

CLK MUX1

C18

LA14_P

PPS

LVCMOS25 / LVCMOS18

Input

FRONT PANEL

C30

SCL

SCL

LVCMOS25 / LVCMOS18

Output

EEPROM

C31

SDA

SDA

LVCMOS25 / LVCMOS18

Output

EEPROM

C34

GA0

GA0

LVCMOS25 / LVCMOS18

Output

N/A

D35

GA1

GA1

LVCMOS25 / LVCMOS18

Output

N/A

C15

LA10_N

CUSTOMIO_0

LVCMOS25 / LVCMOS18

Input2

HDMI connector

D20

LA17_P

CUSTOMIO_1

LVCMOS25 / LVCMOS18

Input2

HDMI connector

H32

LA28_N

CUSTOMIO_2

LVCMOS25 / LVCMOS18

Output2

HDMI connector

D26

LA26_P

CUSTOMIO_3

LVCMOS25 / LVCMOS18

Output2

HDMI connector

D27

LA26_N

CUSTOMIO_4

LVCMOS25 / LVCMOS18

Output2

HDMI connector

G27

LA25_P

CUSTOMIO_5

LVCMOS25 / LVCMOS18

Output2

HDMI connector

H28

LA24_P

CUSTOMIO_6

LVCMOS25 / LVCMOS18

Output2

HDMI connector

H29

LA24_N

CUSTOMIO_7

LVCMOS25 / LVCMOS18

Output2

HDMI connector

H13

LA07_P

RF_SACLK

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

H14

LA07_N

RF_SAEN

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

G12

LA08_P

RF_SADO

LVCMOS25 / LVCMOS18

Input

Lime
Microsystems

G13

LA08_N

RF_SADIO

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

C14

LA10_P

RF_RESET_N

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

H19

LA15_P

PLL_MISO

LVCMOS25 / LVCMOS18

Input

PLL

H20

LA15_N

PLL_MOSI

LVCMOS25 / LVCMOS18

Output

PLL

G18

LA16_P

PLL_CS

LVCMOS25 / LVCMOS18

Output

PLL

G30

LA29_P

CPLD_CS

LVCMOS25 / LVCMOS18

Input

CPLD

G19

LA16_N

PLL_CLK

LVCMOS25 / LVCMOS18

Output

PLL

Radio420X User's Guide 1.7

G28

LA25_N

PLL_LOCK

LVCMOS25 / LVCMOS18

Output

PLL

C26

LA27_P

UDAC_SDI

LVCMOS25 / LVCMOS18

Output

UDAC

C27

LA27_N

UDAC_SPI_SCLK

LVCMOS25 / LVCMOS18

Output

UDAC

H31

LA28_P

UDAC_SDEN_N

LVCMOS25 / LVCMOS18

Output

UDAC

G34

LA31_N

TRX_A_RDA1005
L_LE_RX

LVCMOS25 / LVCMOS18

Output

RX amplifier

H34

LA30_P

TRX_A_RDA1005
L_CLK_RX

LVCMOS25 / LVCMOS18

Output

RX amplifier

H35

LA30_N

TRX_A_RDA1005
L_DATA_RX

LVCMOS25 / LVCMOS18

Output

RX amplifier

G33

LA31_P

TRX_A_RDA1005
L_LE_TX

LVCMOS25 / LVCMOS18

Output

TX amplifier

H37

LA32_P

TRX_A_RDA1005
L_DATA_TX

LVCMOS25 / LVCMOS18

Output

TX amplifier

H38

LA32_N

TRX_A_RDA1005
L_CLK_TX

LVCMOS25 / LVCMOS18

Output

TX amplifier

Table 10 Radio420S clock, control and SPI pin assignments

1
2

These signals are unused for the Radio420X 1.8V since the clock switch (SY89540UMG) is not powered and can be left floating.
These I/O directions are default states. They can be modified by reprogramming CPLD 2 of Radio420X. Contact Nutaq for details.

Radio420M high-pin-count connector

Note:

Radio420M HPC connectors share all the pins of the LPC connector above. Only the additional HPC pins are
described below.
FMC pin on
P1

Pin name

Design name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

LMS6002D

E9

HA09_P

CH2_RXEN

LVCMOS25 / LVCMOS18

Output

RXEN

F4

HA00_P_CC

CH2_RXCLK

LVCMOS25 / LVCMOS18

Input

RXCLKOUT

F5

HA00_N_CC

CH2_RXIQSEL

LVCMOS25 / LVCMOS18

Input

RXIQSEL

E2

HA01_P_CC

CH2_RXD0

LVCMOS25 / LVCMOS18

Input

RXD0

E3

HA01_N_CC

CH2_RXD1

LVCMOS25 / LVCMOS18

Input

RXD1

K7

HA02_P

CH2_RXD2

LVCMOS25 / LVCMOS18

Input

RXD2

K8

HA02_N

CH2_RXD3

LVCMOS25 / LVCMOS18

Input

RXD3

J6

HA03_P

CH2_RXD4

LVCMOS25 / LVCMOS18

Input

RXD4

29

FMC pin on
P1

Pin name

Design name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

LMS6002D

J7

HA03_N

CH2_RXD5

LVCMOS25 / LVCMOS18

Input

RXD5

F7

HA04_P

CH2_RXD6

LVCMOS25 / LVCMOS18

Input

RXD6

F8

HA04_N

CH2_RXD7

LVCMOS25 / LVCMOS18

Input

RXD7

E6

HA05_P

CH2_RXD8

LVCMOS25 / LVCMOS18

Input

RXD8

E7

HA05_N

CH2_RXD9

LVCMOS25 / LVCMOS18

Input

RXD9

K10

HA06_P

CH2_RXD10

LVCMOS25 / LVCMOS18

Input

RXD10

K11

HA06_N

CH2_RXD11

LVCMOS25 / LVCMOS18

Input

RXD11

Table 11 Radio420M A/D conversion data path related pin assignments

FMC Pin
on P1

Pin name

Design name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

LMS6002D

K26

HB00_N_CC

CH2 _TXEN

LVCMOS25 / LVCMOS18

Output

TXEN

K25

HB00_P_CC

CH2_TXIQSEL

LVCMOS25 / LVCMOS18

Output

TXIQSEL

J24

HB01_P

CH2_TXD0

LVCMOS25 / LVCMOS18

Output

TXD0

J25

HB01_N

CH2_TXD1

LVCMOS25 / LVCMOS18

Output

TXD1

F22

HB02_P

CH2_TXD2

LVCMOS25 / LVCMOS18

Output

TXD2

F23

HB02_N

CH2_TXD3

LVCMOS25 / LVCMOS18

Output

TXD3

E21

HB03_P

CH2_TXD4

LVCMOS25 / LVCMOS18

Output

TXD4

E22

HB03_N

CH2_TXD5

LVCMOS25 / LVCMOS18

Output

TXD5

F25

HB04_P

CH2_TXD6

LVCMOS25 / LVCMOS18

Output

TXD6

F26

HB04_N

CH2_TXD7

LVCMOS25 / LVCMOS18

Output

TXD7

E24

HB05_P

CH2_TXD8

LVCMOS25 / LVCMOS18

Output

TXD8

E25

HB05_N

CH2_TXD9

LVCMOS25 / LVCMOS18

Output

TXD9

K28

HB06_P_CC

CH2_TXD10

LVCMOS25 / LVCMOS18

Output

TXD10

K29

HB06_N_CC

CH2_TXD11

LVCMOS25 / LVCMOS18

Output

TXD11

Table 12 Radio420M D/A conversion data path related pin assignments

30

Radio420X User's Guide 1.7

FMC pin
on P1

Pin name

Design name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

Connection

J2

CLK2_BIDIR_P

FMC_CLK3_BIDIR_P

LVDS

Output

CLK MUX1

J3

CLK2_BIDIR_N

FMC_CLK3_BIDIR_N

LVDS

Output

CLK MUX1

K4

CLK3_BIDIR_P

FMC_CLK2_BIDIR_P

LVDS

Output

CLK MUX1

K5

CLK3_BIDIR_N

FMC_CLK2_BIDIR_N

LVDS

Output

CLK MUX1

E12

HA13_P

CH2_CLKMUX_CONFIG

LVCMOS25 / -

Output

CLK MUX1

E13

HA13_N

CH2_CLKMUX_LOAD

LVCMOS25 / -

Output

CLK MUX1

J12

HA11_P

CH2_CLKMUX_SOUT0

LVCMOS25 / -

Input

CLK MUX1

J13

HA11_N

CH2_CLKMUX_SOUT1

LVCMOS25 / -

Input

CLK MUX1

F13

HA12_P

CH2_CLKMUX_SIN0

LVCMOS25 / -

Output

CLK MUX1

F14

HA12_N

CH2_CLKMUX_SIN1

LVCMOS25 / -

Output

CLK MUX1

E30

HB13_P

CH2_PPS

LVCMOS25 / LVCMOS18

Input

FRONT PANEL

K13

HA10_P

RF_RESET_N

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

F10

HA08_P

RF_SADO

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

F11

HA08_N

RF_SADIO

LVCMOS25 / LVCMOS18

Input

Lime
Microsystems

J9

HA07_P

RF_SACLK

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

J10

HA07_N

RF_SAEN

LVCMOS25 / LVCMOS18

Output

Lime
Microsystems

K14

HA10_N

CH2_CUSTOMIO0

LVCMOS25 / LVCMOS18

Input2

HDMI connector

K16

HA17_P_CC

CH2_CUSTOMIO1

LVCMOS25 / LVCMOS18

Input2

HDMI connector

K17

HA17_N_CC

CH2_CUSTOMIO2

LVCMOS25 / LVCMOS18

Output2

HDMI connector

J16

HA14_N

CH2_CUSTOMIO3

LVCMOS25 / LVCMOS18

Output2

HDMI connector

J18

HA18_P

CH2_CUSTOMIO4

LVCMOS25 / LVCMOS18

Output2

HDMI connector

J19

HA18_N

CH2_CUSTOMIO5

LVCMOS25 / LVCMOS18

Output2

HDMI connector

K31

HB10_P

CH2_CUSTOMIO6

LVCMOS25 / LVCMOS18

Output2

HDMI connector

31

FMC pin
on P1

Pin name

Design name

I/O/Standard
(Radio420X 2.5V / 1.8V)

Direction
(Carrier POV)

Connection

K32

HB10_N

CH2_CUSTOMIO7

LVCMOS25 / LVCMOS18

Output2

HDMI connector

E15

HA16_P

CH2_PLL

LVCMOS25 / LVCMOS18

Output

PLL

E16

HA16_N

CH2_PLL_CLK

LVCMOS25 / LVCMOS18

Output

PLL

J30

HB11_P

CH2_PLL_LOCK

LVCMOS25 / LVCMOS18

Output

PLL

F16

HA15_P

CH2_PLL_MISO

LVCMOS25 / LVCMOS18

Input

PLL

F17

HA15_N

CH2_PLL_MOSI

LVCMOS25 / LVCMOS18

Output

PLL

E27

HB09_P

CH2_UDAC_SDI

LVCMOS25 / LVCMOS18

Output

UDAC

E28

HB09_N

CH2_UDAC_SCLK

LVCMOS25 / LVCMOS18

Output

UDAC

J15

HA14_P

CH2_UDAC_SDEN

LVCMOS25 / LVCMOS18

Output

UDAC

J27

HB07_P

CH2_RDA1005L_CLK_R
X

LVCMOS25 / LVCMOS18

Output

RX amplifier

J28

HB07_N

CH2_RDA1005L_DATA_
RX

LVCMOS25 / LVCMOS18

Output

RX amplifier

F32

HB12_N

CH2_RDA1005L_LE_RX
1

LVCMOS25 / LVCMOS18

Output

RX amplifier

F28

HB08_P

CH2_RDA1005L_DATA_
TX

LVCMOS25 / LVCMOS18

Output

TX amplifier

F29

HB08_N

CH2_RDA1005L_CLK_T
X

LVCMOS25 / LVCMOS18

Output

TX amplifier

F31

HB12_P

CH2_RDA1005L_LE_TX

LVCMOS25 / LVCMOS18

Output

TX amplifier

Table 13 Radio420M clock, control and SPI pin assignments

1
2

These signals are unused for the Radio420X 1.8V since the clock switch (SY89540UMG) is not powered and can be left floating.
These I/O directions are default states. They can be modified by reprogramming CPLD 2 of Radio420X. Contact Nutaq for details.

Full Radio420X pin assignments

Radio420S

32

No.

NC

GND

PG_M2C

GND

PG_C2M

GND

GND

FMC_CLK1_P1

GND

NC

GND

NC

GND

FMC_CLK1_N1

GND

NC

GND

NC

FMC_CLK0_P1

GND

NC

GND

NC

GND

Radio420X User's Guide 1.7

No.

FMC_CLK0_N1

GND

NC

GND

NC

GND

GND

TRX_A_RXCLK

GND

NC

GND

NC

CH1_RXD2

CH1_RXIQSEL

NC

NC

GND

NC

CH1_RXD3

GND

NC

GND

CH1_RXD0

GND

GND

CH1_RXD4

GND

NC

CH1_RXD1

GND

10

CH1_RXD6

CH1_RXD5

NC

NC

GND

CH1_RXD10

11

CH1_RXD7

GND

NC

GND

CH1_RXD8

CH1_RXD11

12

GND

TRX_A_SADO

GND

NC

CH1_RXD9

GND

13

TRX_SACLK

TRX_A_SADIO

NC

NC

GND

GND

14

TRX_SAEN

GND

NC

GND

CH1_RXEN

TRX_RESET

15

GND

CLKMUX_SIN01

GND

NC

CH1_TXEN

CUSTOMIO_0

16

CLKMUX_SOUT01

CLKMUX_SIN11

NC

NC

GND

GND

17

CLKMUX_SOUT11

GND

NC

GND

CLKMUX_CON
F1

GND

18

GND

PLL_SPI_CS

GND

NC

CLKMUX_LOA
D1

PPS

19

PLL_SPI_MISO

PLL_SPI_CLK

NC

NC

GND

NC

20

PLL_SPI_MOSI

GND

NC

GND

CUSTOMIO_1

GND

21

GND

CH1_TXD4

GND

NC

TRX_A_TXIQS
EL

GND

22

CH1_TXD2

CH1_TXD5

NC

NC

GND

CH1_TXD0

23

CH1_TXD3

GND

NC

GND

CH1_TXD10

CH1_TXD1

24

GND

CH1_TXD8

GND

NC

CH1_TXD11

GND

25

CH1_TXD6

CH1_TXD9

NC

NC

GND

GND

26

CH1_TXD7

GND

NC

GND

CUSTOMIO_3

UDAC_SPI_SDI

27

GND

CUSTOMIO_5

GND

NC

CUSTOMIO_4

UDAC_SPI_SCL
K

28

CUSTOMIO_6

PLL_LOCK

NC

NC

GND

GND

33

No.

29

CUSTOMIO_7

GND

NC

GND

TCK

GND

30

GND

CPLD_SPI_CS

GND

NC

TDI

SCL

31

UDAC_SDEN_N

NC

NC

NC

TDO

SDA

32

CUSTOMIO_2

GND

NC

GND

3P3VAUX

GND

33

GND

TRX_A_RDA1005L
_LE_TX

GND

NC

TMS

GND

34

TRX_A_RDA1005L
_CLK_RX

TRX_A_RDA1005L
_LE_RX

NC

NC

TRST_L

GA0

35

TRX_A_RDA1005L
_DATA_RX

GND

NC

GND

GA1

12V

36

GND

NC

GND

NC

3P3V

GND

37

TRX_A_RDA1005L
_DATA_TX

NC

NC

NC

GND

12V

38

TRX_A_RDA1005L
_CLK_TX

GND

NC

GND

3P3V

GND

39

GND

2P5V

GND

2P5V

GND

3P3V

40

2P5V

GND

2P5V

GND

3P3V

GND

Table 14 Radio420S low-pin-count connector pin assignments

1

34

These signals are unused for the Radio420X 1.8V since the clock switch (SY89540UMG) is not powered and can be left floating.

Radio420X User's Guide 1.7

Radio420M
In addition to the C, D, G, and H rows of the low-pin-count connector pin assignments above, the
Radio420M (equipped with a high-pin-count connector) also has the following rows.
No.

NC

GND

GND

FMC_CLK3_BIDIR_P1

GND

FMC_CLK3_BIDIR_N1

FMC_CLK2_BIDIR_P1

GND

FMC_CLK2_BIDIR_N1

GND

GND

CH2_RXD4

CH2_RXD2

CH2_RXD5

CH2_RXD3

GND

GND

CH2_SACLK

10

CH2_RXD10

CH2_SAEN

11

CH2_RXD11

GND

12

GND

CH2_CLK_MUX_SOUT01

13

CH2_RESET

CH2_CLK_MUX_SOUT11

14

CH2_CUSTOMIO0

GND

15

GND

CH2_UDAC_SDEN

16

CH2_CUSTOMIO1

CH2_CUSTOMIO3

17

CH2_CUSTOMIO2

GND

18

GND

CH2_CUSTOMIO4

19

NC

CH2_CUSTOMIO5

20

NC

GND

21

GND

NC

22

NC

NC

23

NC

GND

35

No.

24

GND

CH2_TXD0

25

CH2_TX_IQ_SEL

CH2_TXD1

26

CH2_TXEN

GND

27

GND

CH2_RDA1005L_CLK_RX

28

CH2_TXD10

CH2_RDA1005L_DATA_RX

29

CH2_TXD11

GND

30

GND

CH2_PLL_LOCK

31

CH2_CUSTOMIO6

NC

32

CH2_CUSTOMIO7

GND

33

GND

NC

34

CPLD_SPI_CS

NC

35

NC

GND

36

GND

NC

37

NC

NC

38

NC

GND

39

GND

2P5V

40

2P5V

GND

Table 15 Radio420M high-pin-count connector pin assignments (1)

1

36

These signals are unused for the Radio420X 1.8V since the clock switch (SY89540UMG) is not powered and can be left floating.

No.

PG_M2C

GND

0V

GND

GND

CH2_RXD0

GND

NC

GND

CH2_RXD1

GND

NC

CH2_RXD6

GND

GND

GND

CH2_RXD7

GND

GND

GND

GND

CH2_RXD8

GND

NC

Radio420X User's Guide 1.7

No.

CH2_SADO

CH2_RXD9

GND

NC

CH2_SADIO

GND

GND

GND

GND

CH2_RXEN

GND

GND

10

RF_SADO

NC

GND

NC

11

RF_SADIO

GND

GND

NC

12

GND

CH2_CLKMUX_CON
FIG1

NC

GND

13

CH2_CLKMUX_SIN01

CH2_CLKMUX_LOA
D1

NC

GND

14

CH2_CLKMUX_SIN11

GND

GND

NC

15

GND

CH2_PLL_CS

GND

NC

16

CH2_PLL_MISO

CH2_PLL_CLK

NC

GND

17

CH2_PLL_MOSI

GND

NC

GND

18

GND

NC

GND

NC

19

NC

NC

GND

NC

20

NC

GND

NC

GND

21

GND

CH2_TXD4

NC

GND

22

CH2_TXD2

CH2_TXD5

GND

NC

23

CH2_TXD3

GND

GND

NC

24

GND

CH2_TXD8

GND

GND

25

CH2_TXD6

CH2_TXD9

GND

GND

26

CH2_TXD7

GND

GND

NC

27

GND

CH2_UDAC_SDI

GND

NC

28

CH2_RDA1005L_DA
TA_TX

CH2_UDAC_SCLK

GND

GND

29

CH2_RDA1005L_CLK
_TX

GND

GND

GND

30

GND

CH2_PPS

GND

NC

37

No.

31

CH2_RDA1005L_LE_
TX

NC

GND

NC

32

CH2_RDA1005L_LE_
RX1

GND

NC

GND

33

GND

NC

NC

GND

34

NC

NC

GND

NC

35

NC

GND

GND

NC

36

GND

NC

NC

GND

37

NC

NC

NC

GND

38

NC

GND

GND

NC

39

GND

2P5V

GND

NC

40

2P5V

GND

NC

GND

Table 16 Radio420M high-pin-count connector pin assignments (2)

1

38

These signals are unused for the Radio420X 1.8V since the clock switch (SY89540UMG) is not powered and can be left floating.

Radio420X User's Guide 1.7

3 Specifications

This chapter presents the main technical specifications of the Radio420X FMC.
Note:

The specifications presented here are subject to change without notice.

3.1 Mechanical
3.1.1 Radio420S
Dimensions (WHD): 69 mm 10 mm 84 mm
Mass: 80 g

3.1.2 Radio420E
Dimensions (WHD): 69 mm 15.4 mm 84 mm
Mass: 90 g

3.1.3 Radio420M
Dimensions (WHD): 69 mm 20 mm 84 mm
Mass: 170 g

3.2 Electrical
3.2.1 Currents
12 V: 0.6 A
3V3: 0.7 A
3V3MP: 0.05 A

3.2.2 Overall Power Consumption

7W

39

3.3 Analog Specifications

Parameter

Specification

Number of channels

Channel resolution

12 bits

ENOB

10 bits

Maximum I/Q sampling rate

40 MHz

Input voltage range

1 Vp-p

Impedance

50

Connectors

MMCX

Table 17 Analog input

Parameter

Specification

Number of channels

Channel resolution

12 bits

Sampling rate

40 MHz

Maximum I/Q sampling rate

40 MHz

Output voltage range

2502000 mV

Impedance

50

Connectors

MMCX

Table 18 Analog output

3.4 Reference Clock Input and Output

3.4.1 External Clock Output
VOH:

2.7 V

VOL:

0.3 V

Impedance:

50

Coupling:

DC

40

Radio420X User's Guide 1.7

3.4.2 Clock Input

VIH:

2.0 V

VIL:

0.8 V

Impedance:

50

Frequency range:

up to 250 MHz

Coupling:

AC

3.5 Onboard Reference TCVCXO

Parameter

Condition

Minimum

Frequency range

Typical

Maximum

up to 250 MHz

Frequency output
Tuning voltage variation
Ageing variation

30.72 MHz

6 ppm

18 ppm

TBD

Temperature variation

30 C to 75 C

100 ppb

Phase noise

1 kHz

106 dB/Hz

10 kHz

121 dB/Hz

100 kHz

122 dB/Hz

1 MHz

130 dB/Hz

03333
(minimum deviation of the
reference)

0.5 V

0FFFF
(maximum deviation of the
reference)

2.5 V

Voltage-control DAC
output

Table 19 Onboard reference TCVCXO specifications

41

3.6 Acquisition Clock

Parameter

Condition

Typical

Phase noise @ 75 MHz

1 kHz

105 dBc/Hz

10 kHz

110 dBc/Hz

100 kHz

115 dBc/Hz

1 MHz

132 dBc/Hz

Table 20 Acquisition clock specifications

3.7 Local RF Oscillator

Parameter

Conditions

Typical Value

Frequency ranges (GHz)

Low-Band

Local
RF Oscillator
Phase Noise

Variable Gains
LPF = 2.5MHz
Output power = 0dBm

High-Band

0.300
1.500

1.500
2.000

1.000
1.500

1.500
2.500

2.500
3.500

3.500
3.900

1kHz

-92dBc/Hz

-87dBc/Hz

-90dBc/Hz

-85dBc/Hz

-82dBc/Hz

-80dBc/Hz

10kHz

-97dBc/Hz

-92dBc/Hz

-94dBc/Hz

-91dBc/Hz

-87dBc/Hz

-84dBc/Hz

100kHz

-102dBc/Hz

-96dBc/Hz

-94dBc/Hz

-94dBc/Hz

-90dBc/Hz

-89dBc/Hz

1MHz

-126dBc/Hz

-123dBc/Hz

-124dBc/Hz

-123dBc/Hz

-121dBc/Hz

-120dBc/Hz

Table 21 Local RF oscillator specifications

3.8 Acquisition PLL Output Frequency Ranges

Parameter

PLL output

Minimum

Typical

Maximum

LMS6200D reference clock

23 MHz

41 MHz

LMS6200D TX clock

80 MHz

LMS6200D RX clock

80 MHz

External clock

250 MHz

FPGA design clock (FMC CLK0)

80 MHz

Table 22 Acquisition PLL output frequency ranges

42

Radio420X User's Guide 1.7

3.9 Transmitter
Parameter

Condition

Minimum

Typical

Maximum

Low-band RF range

300 MHz

1500 MHz

High-band RF range

1500 MHz

3800 MHz

2.4 Hz

20 s

70 dB

1.5 MHz

28.0 MHz

Frequency resolution
PLL settling time

Total gain control

Baseband filter bandwidth

1 ppm, 50 kHz loop

bandwidth

Table 23 Transmitter specifications (1)

43

Parameter

Conditions

Typical Value
Frequency ranges (GHz)
Low-Band
0.300

Low-Band

High-Band
1.500

1.000

1.500

2.500

3.500

High-Band
1.500

2.000

1.500

2.500

3.500

3.900

-10dB

-2dB

-8dB

-5dB

-8dB

-12dB

Output Signal
Power
Roll-off

VGA1 = -20dB
VGA2 = 6dB
Ext. = 0dB

Spurious-Free
Dynamic Range
(SFDR)

Variable Gains
LPF = 2.5MHz
Output power = -10dBm

3rd
Intermodulation
Distortion
(IMD3)

Variable Gains
Generated Signal:
1MHz-spaced dual-tone /
1.25MHz carrier offset

-59dBc

1-dB
compression
point (P1dB)

VGA1 = Variable
VGA2 = 25dB
Ext. = 18dB
LPF = 2.5MHz

20.2dBm

19.5dBm

Sideband
Supp.

-47dBc

-45dBc

-45dBc

-46dBc

-44dBc

-38dBc

Sideband
Carrier
Suppression

Variable
Gains
LPF
=
2.5MHz
Output
power
=
0dBm

Carrier
Supp.

-47dBc

-49dBc

-50dBc

-51dBc

-52dBc

-55dBc

&

-60dBc

-59dBc

-61dBc

-60dBc

-59dBc

-59dBc
(Sig.=0dBm)

-58dBc
(Sig.=0dBm)

-42dBc
(Sig.=0dBm)

-63dBc
(Sig.=
-10dBm)

-63dBc
(Sig.=
-10dBm)

-62dBc
(Sig.=-10dBm)

-58dBc
(Sig.=
-10dBm)

19.8dBm

18.2dBm

15.0dBm

13.8dBm

-49dBc
(Sig.=0dBm)

Table 24 Transmitter specifications (2)

3.10 Receiver
Parameter

Minimum

Typical

Maximum

Low-band RF range

300 MHz

1500 MHz

High-band RF range

1500 MHz

3800 MHz

20 s

Low-band RX gain control

79 dB

High-band RX gain control

73 dB

1.5 MHz

28.0 MHz

PLL settling time

Baseband filter bandwidth

Condition

1 ppm, 50 kHz loop bandwidth

Digitally selected

Table 25 Receiver specifications (1)

44

Radio420X User's Guide 1.7

Parameters

Conditions

Typical Value
Frequency ranges (GHz)
Low-Band

Input Signal
Power
Roll-off

Minimum
Detectable
Signal
(Sensitivity)

SpuriousFree
Dynamic
Range (SFDR)

3rd
Intermodulat
ion
Distortion
(IMD3)

1-dB
Compression
Point (P1dB)

LowBand

HighBand

LNA =
6dB

LNA=6
dB

VGA1 =
30dB

VGA1=
19dB

VGA2 =
12dB

VGA2=
9dB

Ext. =
18dB

Ext.=1
8dB

LNA = 6dB
VGA2 = 0dB
Ext. = 18dB
LPF = 2.5MHz
UDSNR = 5dB
BW = 200kHz
Tone: 500kHz/100dBm

LNA = 6dB
VGA1 = 19dB
VGA2 = 0dB
Ext. = 18dB
Input Signal:
Variable power
Measured Signal:
-8dBFS
LPF = 5MHz
LNA = 6dB
VGA1 = 19dB
VGA2 = 0dB
Ext. = 18dB
Input Signal:
100kHz-spaced
dual-tone
(-40dBm LB / 47dBm HB)
LNA = 6dB

0.300

1.500

1.000

1.500

2.500

3.500

1.500

2.000

1.500

2.500

3.500

3.900

3dB

4dB

2dB

5dB

8dB

8dB

-104dBm
(VGA1=30dB)

-104dBm
(VGA1=30dB)

-103dBm
(VGA1=30dB)

-98dBm
(VGA1=30dB)

-104dBm
(VGA1=19dB)

-104dBm
(VGA1=19dB)

-103dBm
(VGA1=19dB)

-97dBm
(VGA1=19dB)

-103dBm
(VGA1=5dB)

-102dBm
(VGA1=5dB)

-97dBm
(VGA1=5dB)

-92dBm
(VGA1=5dB)

-104dBm
(VGA1=30dB)
-102dBm
(VGA1=19dB)
-94dBm
(VGA1=5dB)

-102dBm
(VGA1=30dB)
-100dBm
(VGA1=19dB)
-90dBm
(VGA1=5dB)

57dBc

51dBc

53dBc

51dBc

47dBc

43dBc

-62dBc

-59dBc

-54dBc

-53dBc

-52dBc

-49dBm
(VGA1=19dB)

-46dBm
(VGA1=19dB)

-37dBm
(VGA1=5dB)

-34dBm
(VGA1=5dB)

-38dBm
(VGA1=19dB)

-32dBm
(VGA1=19dB)

VGA1 = 19dB /
5dB
-34dBm
VGA2 = 0dB

High-Band

-31dbm

Ext. = 18dB
LPF = 2.5MHz

Table 26 Receiver specifications (2)

45

3.11 Full-Scale Input and Output Levels

All the RF inputs and outputs of the Radio420X are equipped with ESD protection diodes.
Parameter
REFIN clock input

RX input

REFOUT clock output

TX output

Minimum

Maximum

Notes

0V

3.3 V

20.0 dBm

The RX input level on connector J19 is limited by the RDA1005LDS

variable gain amplifier, which has an absolute maximum input power
rating of 20 dBm. Exceeding this value can cause permanent damage
to the amplifier.

0V

3.3 V

The clock output on connector J16 is an LVCMOS signal with a typical

minimum of 0 V and typical maximum of 3.3 V.

20.5 dBm

The reference clock input level on connector J17 should be a 3.3-V

LVTTL or LVCMOS signal. The connector drives the MC10EPT20
translator, which requires that the input voltage stays below 3.3 V.

The TX output on connector J18 is limited by the RDA1005LDS variable

gain amplifier and depends on the operating frequency. The 1-dB
output compression point (P1dB) is 20.5 dBm at 500 MHz and drops to
14.7 dBm at 4 GHz. Refer to the RDA1005LDS data sheet for details.

Table 27 Full-scale input and output levels

3.12 Local Oscillator Phase Noise

Figure 3-1 Low-Band local oscillator phase noise

46

Radio420X User's Guide 1.7

Figure 3-2 High-Band local oscillator phase noise

3.13 Minimum Detectable Signal Thresholds

Figure 3-3 Minimum detectable signal as a function of VGA1 setting

47

3.14 Receiver Operating Curves

Figure 3-4 Low-band receiver operating curves

Figure 3-5 High-band receiver operating curves

48

Radio420X User's Guide 1.7

3.15 Transmitter Operating Curves

Figure 3-6 Low-band transmitter operating curves

Figure 3-7 High-band transmitter operating curves

49

3.16 Rx Signal Power Roll-Off

Figure 3-8 Rx signal power roll-off (see table x in section 3.10 for detailed roll off)

50