Questions to be taken in first and fifth units

QUESTION BANK FOR ADVANCED DIGITAL SYSTEM DESIGN

Unit I
Part A

1.
2.
3.
4.

Differentiate between Synchronous and Asynchronous Sequential circuits.

Obtain the next state equation for JK flip flop
Write down the application table of all types of flip flops.
Design a serial binary adder in a MEALY network form.
5. What is meant by state assignment?
6. State the rules for State Assignment

7. Obtain the next state equation for JK flip flop for the following :
a.J1=y, K1=y+xQ2
b. J2= xQ1+xyQ1, K2=xy+yQ1
8. Write down the Characteristic Equation for all types of flip flops.
9. Draw the block diagram of mealy machine.
10. List few applications of Iterative circuits.
11. Give the general model of a sequential circuit. Which feature distinguishes sequential
network from combinational networks?
12. A reduced state table has 14 rows. What is the minimum number of Flip flop s needed to
build the sequential circuit?
13. What are the components of ASM chart?
14. When two states are considered equivalent in sequential circuits?
15. Draw the block diagram of Moore machine.
Part B
1. Design a sequential circuit to convert BCD to excess 3 codes. (16)
2. Design a Synchronous Up/Down Counter using D FF for four stages (16)
3. A Moore sequential network has one input and one output. The output should be 1 if the total
number of 1s received is odd and the total number of 0s received is an even number greater
than 0.derive the state graph and state table.(16)
4. Design a counter that goes through the following sequence of states that are not in

numeric order. 0,3,2,4,1,5,7 and repeat.(8)

Design a synchronous sequential circuit for the following count sequence 6-4-3-7-1-6-43-7-1-6.(8)
6. Design a mod- 6 CSSN counter using state table reduction method. (12)
7. What are iterative circuits? Give examples. (4)
5.

8. Construct an ASM block for state S1 that has two input variables, x1 and x2 and one output
variable z. the output is asserted if x1 =0 and x2 =1. The block exist to state S2 unless x1 = x2 =1,
9.

in which case the block exist to state S3. (16)

Using D-flip flops design a counter that goes through the following sequence 0, 5,7,2,6
and repeat. (10)
With an example explain state table assignment and reduction. (6)
Design a BCD counter using state table assignment and reduction method. (10)
Write short notes on ASM Realization. (6)

10.
11.
12.
13. Design a modulo 6 counter ,which counts in the sequence 0,1,2,3,4,5,0,1 ..... Construct the
circuit using D Flip flop and JK flip flop. (16)
14. which counts in the sequence 0,1,2,3,4,5,0,1.. Constructs the circuit using D flip flop.
(16)
15. Obtain the State table and State diagram for sequence 0110/1010. (16)
16. Design a serial binary adder network using state assignment method. (8)

17. By using following equations

JA=xB+yB
KA=xyB
JB=xA
KB=xy+A
Z=xyA+xyB
Obtain the logic diagram, State Table, state diagram. (16)
18. Design a modulo-6 counter, which counts in the sequence 0, 1, 2, 3, 4, 5, 0, 1..
Constructs the circuit using D flip flop. (16)
19. Design a Modulo-4 Counter or modulo-four up-counter: 0, 1, 2, 3, 0, 1, 2, 3, etc.
Unit II
Part A

1. What is meant by critical race?

2. What is meant by primitive flow table?
3. What is essential hazard?
4. Give an example circuit for dynamic hazard.
5. What is a fundamental mode asynchronous sequential circuit?
6. What is Row matching?
7. In what type of circuit Essential hazards may be generated
8. Define static 0 Hazard.
9. Name the races that happen in an asynchronous circuit.
10. What are dynamic and static Hazards?
11. What is a critical race with reference to asynchoronous sequential circuit.
12. What is Static 1 Hazard?
Part B

1.Explain Races in Asynchronous Sequential Circuit. (8)

2.Design a fundamental mode asynchronous sequential network meeting the following
requirements.There are two inputs X1 and X2 and a single output Z. The inputs of Z=1 is to

occur only during the input state X1X2=01 and then if and if only if the input state X1X2=01 is
preceded by the input sequence X1X2=01, 00, 10, 00, 10, 00.
(16)
3.Draw The Logic diagram for the following excitation equation (8)
D1=Q2Q3x
D2=Q2Q3+Q1X+Q2Q3X
D3= Q3X+Q2X
Z=Q2X+Q3X
4.An asynchronous sequential circuit is described by the following excitation and output function
Y = X`1X2 + (X1+X2) y
Z=Y

5.Draw the logic diagram of the circuit. Derive the transition table and output map.Describe the
behaviour of the circuit. (16)
6. An asynchronous sequential circuit has two internal states and one output.The excitation and output
function describing the circuit are as follows.

Y1 x1 x2 x1 y 2 x2 y1
Y2 x2 x1 y1 y 2 x1 y1
Z x2 y1
7. Discuss static and dynamic hazards in asynchronous circuits through example.(8)
8. Explain Races in ASC.

Unit III
Part A

1.
2.
3.
4.

What do you mean by Test Generation?

What is ETV ?
What is signature analysis?
What is Shrikange Faults?

5.
6.
7.
8.
9.

What are the three conditions in the digital circuits to apply Kohavi Algorithm?
Differentiate Weak & Strong faults with suitable examples.
Define a Growth Fault.
Name the test vectors which will result in Fault Table Method.
Give the steps used in Path sensitization Method.

10. What are the different types of Stuck at Faults?

11. What is Vanishing Fault? What are types of cross point faults?

12. Sate the uses of Built in Test facility in digital system

Part B
1.A circuit realises the function z= x1x4+x2x3 +x1x4 Using the Boolean difference method find the test
vectors for SA0 fault on all input lines of the circuit.
2.Using Path Senstization methods to find the test vector for SA0 for x2 Path (8)

3.Explain in Detail about Fauit Tolerance Technique (8)

4.Explain About BIST
(8)
5.Identify test vectors for the given fig. using Path Sensitization Method. (6)

6.Explain Compact Algorithm.

(16)

7. Explain fault tolerance in PLA for sequential circuit.(8)discuss the test generation using any
programmable devices.(8)
8.write PLD distribuition for binary to excess 3 code converter(8)

9.explain boolean difference method.(8)

10.write the PLD description for the 3 to 8 line decoder.(8)

Unit IV
Part A
1. Distinguish between PLA and PAL.

2. List out the faults in PLA.

3. Name any two IC of PLD.
4. What are the advantages of Xilinx 3000 over Xilinx 2000?
5. What are the different types of mode used for reconfiguration of LCA?
6. What are the advantages of FPGA?
7. Compare Xilinx 2000 with Xilinx 3000?
8. What capability does a polarity fuse give a PLD designer?
9. List two advantages of GAL devices over PAL devices.
10. Plot the cost of FPGAs as function of capacity.
11. Draw the general structure of PLA.
12. Distinguish between a PAL and a PLA.
13. What is the primary distinction between a GAL and EPLD?
Part B

1.Realize the function given below using PLA . Give the PLA table and connection diagram for
the PLA.
F1 (a,b,c,d) = (1,2,4,5,6,8,10,12,14)
F2 (a,b,c,d) = (2,4,6,8,10,11,12,14,15)
(16)
2.Design a Synchronous Sequential machine using a GAL
(16)
3. Explain the architecture of FPGA and Discuss its function.
(16)
4.Distinguish between GAL and EPLD
(6)
5.Draw and describe the structure of an Altera EPLD
(10)
6. Explain the Architecture of Xilinx 3000.
(16)
7.Draw the PAL equivalent for following Boolean Equation
(16)
x=abcd+abc+a
y=ab+cd
z=c+ab
8.Draw Explain the architecture of Xilinx FPGA

9. Explain the Typical FPLS (16)

(16)

10.Illustrate thedesign of any combinational circuit and sequential circuit with PLA (16)
11. write PLD distribuition for the following
A 4X1 multiplexer.
A four bit even parity checker